Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit b0aaad915bf70782db181bd1c774fb7efbae31b3

Authored by Peng Fan
Committed by Ye Li
1 parent 9926803828
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-18243-16 arm: dts: add imx8mm dtsi and binding files 

Sync dts from 4.14.98 Linux kernel commit
e88899128d81ea8b82dfd7d294572f21c388e568
("MLK-21424 can: flexcan: fix normal CAN can't receive
 remote frame after setting fd mode").

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0e7a5484878338d0dff871b6d21092a0479f07b4)
(cherry picked from commit 54a97f31802ea568e04285e0f18689811eecedcb)
Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 3 changed files with 2405 additions and 0 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8mm.dtsi
Diff comments   View file @ b0aaad9
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2017-2019 NXP
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version 2
  7 + * of the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + */
  14 +
  15 +#include "fsl-imx8-ca53.dtsi"
  16 +#include <dt-bindings/clock/imx8mm-clock.h>
  17 +#include <dt-bindings/gpio/gpio.h>
  18 +#include <dt-bindings/input/input.h>
  19 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  20 +#include <dt-bindings/pinctrl/pins-imx8mm.h>
  21 +#include <dt-bindings/thermal/thermal.h>
  22 +
  23 +/ {
  24 + compatible = "fsl,imx8mm";
  25 + interrupt-parent = <&gpc>;
  26 + #address-cells = <2>;
  27 + #size-cells = <2>;
  28 +
  29 + aliases {
  30 + ethernet0 = &fec1;
  31 + i2c0 = &i2c1;
  32 + i2c1 = &i2c2;
  33 + i2c2 = &i2c3;
  34 + i2c3 = &i2c4;
  35 + serial0 = &uart1;
  36 + serial1 = &uart2;
  37 + serial2 = &uart3;
  38 + serial3 = &uart4;
  39 + mmc0 = &usdhc1;
  40 + mmc1 = &usdhc2;
  41 + mmc2 = &usdhc3;
  42 + gpio0 = &gpio1;
  43 + gpio1 = &gpio2;
  44 + gpio2 = &gpio3;
  45 + gpio3 = &gpio4;
  46 + gpio4 = &gpio5;
  47 + spi0 = &flexspi;
  48 + usb0 = &usbotg1;
  49 + usb1 = &usbotg2;
  50 + };
  51 +
  52 + cpus {
  53 + idle-states {
  54 + entry-method = "psci";
  55 +
  56 + CPU_SLEEP: cpu-sleep {
  57 + compatible = "arm,idle-state";
  58 + arm,psci-suspend-param = <0x0010033>;
  59 + local-timer-stop;
  60 + entry-latency-us = <1000>;
  61 + exit-latency-us = <700>;
  62 + min-residency-us = <2700>;
  63 + wakeup-latency-us = <1500>;
  64 + };
  65 + };
  66 + };
  67 +
  68 + memory@40000000 {
  69 + device_type = "memory";
  70 + reg = <0x0 0x40000000 0 0x80000000>;
  71 + };
  72 +
  73 + resmem: reserved-memory {
  74 + #address-cells = <2>;
  75 + #size-cells = <2>;
  76 + ranges;
  77 +
  78 + /* global autoconfigured region for contiguous allocations */
  79 + linux,cma {
  80 + compatible = "shared-dma-pool";
  81 + reusable;
  82 + size = <0 0x28000000>;
  83 + alloc-ranges = <0 0x40000000 0 0x60000000>;
  84 + linux,cma-default;
  85 + };
  86 +
  87 + rpmsg_reserved: rpmsg@0xb8000000 {
  88 + no-map;
  89 + reg = <0 0xb8000000 0 0x400000>;
  90 + };
  91 + };
  92 +
  93 + gic: interrupt-controller@38800000 {
  94 + compatible = "arm,gic-v3";
  95 + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
  96 + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
  97 + #interrupt-cells = <3>;
  98 + interrupt-controller;
  99 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  100 + interrupt-parent = <&gic>;
  101 + };
  102 +
  103 + timer {
  104 + compatible = "arm,armv8-timer";
  105 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
  106 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
  107 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
  108 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
  109 + clock-frequency = <8000000>;
  110 + arm,no-tick-in-suspend;
  111 + interrupt-parent = <&gic>;
  112 + };
  113 +
  114 + pmu {
  115 + interrupt-parent = <&gic>;
  116 + };
  117 +
  118 + busfreq { /* BUSFREQ */
  119 + compatible = "fsl,imx_busfreq";
  120 + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT_SRC>,
  121 + <&clk IMX8MM_CLK_DRAM_APB_SRC>, <&clk IMX8MM_CLK_DRAM_APB_PRE_DIV>,
  122 + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>,
  123 + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>,
  124 + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC_DIV>,
  125 + <&clk IMX8MM_CLK_AHB_DIV>, <&clk IMX8MM_CLK_MAIN_AXI_SRC>,
  126 + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>;
  127 + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
  128 + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
  129 + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
  130 + "sys_pll1_800m";
  131 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
  132 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  133 + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
  134 + };
  135 +
  136 + ddr_pmu0: ddr_pmu@3d800000 {
  137 + compatible = "fsl,imx8m-ddr-pmu", "fsl,imx8-ddr-pmu";
  138 + reg = <0x0 0x3d800000 0x0 0x400000>;
  139 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  140 + };
  141 +
  142 + clocks {
  143 + #address-cells = <1>;
  144 + #size-cells = <0>;
  145 +
  146 + osc_32k: clock@0 {
  147 + compatible = "fixed-clock";
  148 + reg = <0>;
  149 + #clock-cells = <0>;
  150 + clock-frequency = <32768>;
  151 + clock-output-names = "osc_32k";
  152 + };
  153 +
  154 + osc_24m: clock@1 {
  155 + compatible = "fixed-clock";
  156 + reg = <1>;
  157 + #clock-cells = <0>;
  158 + clock-frequency = <24000000>;
  159 + clock-output-names = "osc_24m";
  160 + };
  161 +
  162 + clk_ext1: clock@2 {
  163 + compatible = "fixed-clock";
  164 + reg = <3>;
  165 + #clock-cells = <0>;
  166 + clock-frequency = <133000000>;
  167 + clock-output-names = "clk_ext1";
  168 + };
  169 +
  170 + clk_ext2: clock@3 {
  171 + compatible = "fixed-clock";
  172 + reg = <4>;
  173 + #clock-cells = <0>;
  174 + clock-frequency = <133000000>;
  175 + clock-output-names = "clk_ext2";
  176 + };
  177 +
  178 + clk_ext3: clock@4 {
  179 + compatible = "fixed-clock";
  180 + reg = <5>;
  181 + #clock-cells = <0>;
  182 + clock-frequency = <133000000>;
  183 + clock-output-names = "clk_ext3";
  184 + };
  185 +
  186 + clk_ext4: clock@5 {
  187 + compatible = "fixed-clock";
  188 + reg = <6>;
  189 + #clock-cells = <0>;
  190 + clock-frequency= <133000000>;
  191 + clock-output-names = "clk_ext4";
  192 + };
  193 + };
  194 +
  195 + power-domains {
  196 + compatible = "simple-bus";
  197 + #address-cells = <1>;
  198 + #size-cells = <0>;
  199 +
  200 + /* HSIOMIX */
  201 + hsio_pd: power-domain@0 {
  202 + compatible = "fsl,imx8mm-pm-domain";
  203 + #address-cells = <1>;
  204 + #size-cells = <0>;
  205 + domain-id = <0>;
  206 + #power-domain-cells = <0>;
  207 + domain-name = "HSIO_PD";
  208 + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>,
  209 + <&clk IMX8MM_CLK_SIM_HSIO>;
  210 +
  211 + pcie0_pd: power-domain@1 {
  212 + domain-id = <1>;
  213 + #power-domain-cells = <0>;
  214 + domain-name = "PCIE0_PD";
  215 + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
  216 + };
  217 +
  218 + usb_otg1_pd: power-domain@2 {
  219 + domain-id = <2>;
  220 + #power-domain-cells = <0>;
  221 + domain-name = "USB_OTG1_PD";
  222 + };
  223 +
  224 + usb_otg2_pd: power-domain@3 {
  225 + domain-id = <3>;
  226 + #power-domain-cells = <0>;
  227 + domain-name = "USB_OTG2_PD";
  228 + };
  229 + };
  230 +
  231 + /* GPU2D&3D */
  232 + gpumix_pd: power-domain@4 {
  233 + compatible = "fsl,imx8mm-pm-domain";
  234 + domain-id = <4>;
  235 + #power-domain-cells = <0>;
  236 + domain-name = "GPUMIX_PD";
  237 + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
  238 + <&clk IMX8MM_CLK_GPU2D_ROOT>,
  239 + <&clk IMX8MM_CLK_GPU3D_ROOT>,
  240 + <&clk IMX8MM_CLK_GPU_AHB_DIV>;
  241 + };
  242 +
  243 + vpumix_pd: power-domain@5 {
  244 + compatible = "fsl,imx8mm-pm-domain";
  245 + #address-cells = <1>;
  246 + #size-cells = <0>;
  247 + domain-id = <5>;
  248 + #power-domain-cells = <0>;
  249 + domain-name = "VPUMIX_PD";
  250 + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
  251 +
  252 + vpu_g1_pd: power-domain@6 {
  253 + domain-id = <6>;
  254 + #power-domain-cells = <0>;
  255 + domain-name = "VPU_G1_PD";
  256 + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
  257 + };
  258 +
  259 + vpu_g2_pd: power-domain@7 {
  260 + domain-id = <7>;
  261 + #power-domain-cells = <0>;
  262 + domain-name = "VPU_G2_PD";
  263 + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
  264 + };
  265 +
  266 + vpu_h1_pd: power-domain@8 {
  267 + domain-id = <8>;
  268 + #power-domain-cells = <0>;
  269 + domain-name = "VPU_H1_PD";
  270 + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>;
  271 + };
  272 + };
  273 +
  274 + dispmix_pd: power-domain@9 {
  275 + compatible = "fsl,imx8mm-pm-domain";
  276 + #address-cells = <1>;
  277 + #size-cells = <0>;
  278 + domain-id = <9>;
  279 + #power-domain-cells = <0>;
  280 + domain-name = "DISPMIX_PD";
  281 + clocks = <&clk IMX8MM_CLK_DISP_ROOT>;
  282 +
  283 + mipi_pd: power-domain@10 {
  284 + domain-id = <10>;
  285 + #power-domain-cells = <0>;
  286 + domain-name = "MIPI_PD";
  287 + };
  288 + };
  289 + };
  290 +
  291 + csi1_bridge: csi1_bridge@32e20000 {
  292 + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
  293 + reg = <0x0 0x32e20000 0x0 0x10000>;
  294 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  295 + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
  296 + <&clk IMX8MM_CLK_CSI1_ROOT>,
  297 + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
  298 + clock-names = "disp-axi", "csi_mclk", "disp_dcic";
  299 + power-domains = <&dispmix_pd>;
  300 + status = "disabled";
  301 + };
  302 +
  303 + mipi_csi_1: mipi_csi@32e30000 {
  304 + compatible = "fsl,imx8mm-mipi-csi";
  305 + reg = <0x0 0x32e30000 0x0 0x1000>;
  306 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  307 + clock-frequency = <333000000>;
  308 + clocks = <&clk IMX8MM_CLK_CSI1_CORE_DIV>,
  309 + <&clk IMX8MM_CLK_CSI1_PHY_REF_DIV>,
  310 + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
  311 + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
  312 + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
  313 + bus-width = <4>;
  314 + csi-gpr = <&dispmix_gpr>;
  315 + power-domains = <&mipi_pd>;
  316 + status = "disabled";
  317 + };
  318 +
  319 + gpio1: gpio@30200000 {
  320 + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  321 + reg = <0x0 0x30200000 0x0 0x10000>;
  322 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
  323 + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  324 + gpio-controller;
  325 + #gpio-cells = <2>;
  326 + interrupt-controller;
  327 + #interrupt-cells = <2>;
  328 + };
  329 +
  330 + gpio2: gpio@30210000 {
  331 + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  332 + reg = <0x0 0x30210000 0x0 0x10000>;
  333 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
  334 + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  335 + gpio-controller;
  336 + #gpio-cells = <2>;
  337 + interrupt-controller;
  338 + #interrupt-cells = <2>;
  339 + };
  340 +
  341 + gpio3: gpio@30220000 {
  342 + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  343 + reg = <0x0 0x30220000 0x0 0x10000>;
  344 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  345 + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  346 + gpio-controller;
  347 + #gpio-cells = <2>;
  348 + interrupt-controller;
  349 + #interrupt-cells = <2>;
  350 + };
  351 +
  352 + gpio4: gpio@30230000 {
  353 + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  354 + reg = <0x0 0x30230000 0x0 0x10000>;
  355 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
  356 + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  357 + gpio-controller;
  358 + #gpio-cells = <2>;
  359 + interrupt-controller;
  360 + #interrupt-cells = <2>;
  361 + };
  362 +
  363 + gpio5: gpio@30240000 {
  364 + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  365 + reg = <0x0 0x30240000 0x0 0x10000>;
  366 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  367 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  368 + gpio-controller;
  369 + #gpio-cells = <2>;
  370 + interrupt-controller;
  371 + #interrupt-cells = <2>;
  372 + };
  373 +
  374 + tmu: tmu@30260000 {
  375 + compatible = "fsl,imx8mm-tmu";
  376 + reg = <0x0 0x30260000 0x0 0x10000>;
  377 + clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
  378 + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  379 + little-endian;
  380 + u-boot,dm-pre-reloc;
  381 + #thermal-sensor-cells = <0>;
  382 + };
  383 +
  384 + thermal-zones {
  385 + /* cpu thermal */
  386 + cpu-thermal {
  387 + polling-delay-passive = <250>;
  388 + polling-delay = <2000>;
  389 + thermal-sensors = <&tmu>;
  390 + trips {
  391 + cpu_alert0: trip0 {
  392 + temperature = <85000>;
  393 + hysteresis = <2000>;
  394 + type = "passive";
  395 + };
  396 + cpu_crit0: trip1 {
  397 + temperature = <95000>;
  398 + hysteresis = <2000>;
  399 + type = "critical";
  400 + };
  401 + };
  402 +
  403 + cooling-maps {
  404 + map0 {
  405 + trip = <&cpu_alert0>;
  406 + cooling-device =
  407 + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  408 + };
  409 + };
  410 + };
  411 + };
  412 +
  413 + iomuxc: pinctrl@30330000 {
  414 + compatible = "fsl,imx8mm-iomuxc";
  415 + reg = <0x0 0x30330000 0x0 0x10000>;
  416 + };
  417 +
  418 + gpr: iomuxc-gpr@30340000 {
  419 + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
  420 + reg = <0x0 0x30340000 0x0 0x10000>;
  421 + };
  422 +
  423 + anatop: anatop@30360000 {
  424 + compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
  425 + reg = <0x0 0x30360000 0x0 0x10000>;
  426 + };
  427 +
  428 + snvs: snvs@30370000 {
  429 + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
  430 + reg = <0x0 0x30370000 0x0 0x10000>;
  431 +
  432 + snvs_rtc: snvs-rtc-lp{
  433 + compatible = "fsl,sec-v4.0-mon-rtc-lp";
  434 + regmap =<&snvs>;
  435 + offset = <0x34>;
  436 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  437 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  438 + };
  439 +
  440 + snvs_pwrkey: snvs-powerkey {
  441 + compatible = "fsl,sec-v4.0-pwrkey";
  442 + regmap = <&snvs>;
  443 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  444 + linux,keycode = <KEY_POWER>;
  445 + wakeup-source;
  446 + };
  447 + };
  448 +
  449 + clk: clock-controller@30380000 {
  450 + compatible = "fsl,imx8mm-ccm";
  451 + reg = <0x0 0x30380000 0x0 0x10000>;
  452 + #clock-cells = <1>;
  453 + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
  454 + <&clk_ext3>, <&clk_ext4>;
  455 + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
  456 + "clk_ext3", "clk_ext4";
  457 + };
  458 +
  459 + src: src@30390000 {
  460 + compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
  461 + reg = <0x0 0x30390000 0x0 0x10000>;
  462 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  463 + #reset-cells = <1>;
  464 + };
  465 +
  466 + gpc: gpc@303a0000 {
  467 + compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc", "syscon";
  468 + reg = <0x0 0x303a0000 0x0 0x10000>;
  469 + interrupt-controller;
  470 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  471 + #interrupt-cells = <3>;
  472 + interrupt-parent = <&gic>;
  473 + };
  474 +
  475 + system_counter: timer@306a0000 {
  476 + compatible = "nxp,sysctr-timer";
  477 + reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */
  478 + <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */
  479 + <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */
  480 + clock-frequency = <8000000>;
  481 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  482 + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  483 + };
  484 +
  485 + uart1: serial@30860000 {
  486 + compatible = "fsl,imx8mm-uart",
  487 + "fsl,imx6q-uart", "fsl,imx21-uart";
  488 + reg = <0x0 0x30860000 0x0 0x10000>;
  489 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  490 + clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
  491 + <&clk IMX8MM_CLK_UART1_ROOT>;
  492 + clock-names = "ipg", "per";
  493 + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
  494 + dma-names = "rx", "tx";
  495 + status = "disabled";
  496 + };
  497 +
  498 + uart3: serial@30880000 {
  499 + compatible = "fsl,imx8mm-uart",
  500 + "fsl,imx6q-uart", "fsl,imx21-uart";
  501 + reg = <0x0 0x30880000 0x0 0x10000>;
  502 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  503 + clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
  504 + <&clk IMX8MM_CLK_UART3_ROOT>;
  505 + clock-names = "ipg", "per";
  506 + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
  507 + dma-names = "rx", "tx";
  508 + status = "disabled";
  509 + };
  510 +
  511 + uart2: serial@30890000 {
  512 + compatible = "fsl,imx8mm-uart",
  513 + "fsl,imx6q-uart", "fsl,imx21-uart";
  514 + reg = <0x0 0x30890000 0x0 0x10000>;
  515 + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  516 + clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
  517 + <&clk IMX8MM_CLK_UART2_ROOT>;
  518 + clock-names = "ipg", "per";
  519 + status = "disabled";
  520 + };
  521 +
  522 + i2c1: i2c@30a20000 {
  523 + #address-cells = <1>;
  524 + #size-cells = <0>;
  525 + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  526 + reg = <0x0 0x30a20000 0x0 0x10000>;
  527 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  528 + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
  529 + status = "disabled";
  530 + };
  531 +
  532 + i2c2: i2c@30a30000 {
  533 + #address-cells = <1>;
  534 + #size-cells = <0>;
  535 + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  536 + reg = <0x0 0x30a30000 0x0 0x10000>;
  537 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  538 + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
  539 + status = "disabled";
  540 + };
  541 +
  542 + i2c3: i2c@30a40000 {
  543 + #address-cells = <1>;
  544 + #size-cells = <0>;
  545 + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  546 + reg = <0x0 0x30a40000 0x0 0x10000>;
  547 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  548 + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
  549 + status = "disabled";
  550 + };
  551 +
  552 + i2c4: i2c@30a50000 {
  553 + #address-cells = <1>;
  554 + #size-cells = <0>;
  555 + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  556 + reg = <0x0 0x30a50000 0x0 0x10000>;
  557 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  558 + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
  559 + status = "disabled";
  560 + };
  561 +
  562 + uart4: serial@30a60000 {
  563 + compatible = "fsl,imx8mq-uart",
  564 + "fsl,imx6q-uart", "fsl,imx21-uart";
  565 + reg = <0x0 0x30a60000 0x0 0x10000>;
  566 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  567 + clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
  568 + <&clk IMX8MM_CLK_UART4_ROOT>;
  569 + clock-names = "ipg", "per";
  570 + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
  571 + dma-names = "rx", "tx";
  572 + status = "disabled";
  573 + };
  574 +
  575 +
  576 + imx_rpmsg: imx_rpmsg {
  577 + compatible = "fsl,rpmsg-bus", "simple-bus";
  578 + #address-cells = <2>;
  579 + #size-cells = <2>;
  580 + ranges;
  581 +
  582 + mu: mu@30aa0000 {
  583 + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
  584 + reg = <0x0 0x30aa0000 0x0 0x10000>;
  585 + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  586 + clocks = <&clk IMX8MM_CLK_MU_ROOT>;
  587 + clock-names = "mu";
  588 + status = "disabled";
  589 + };
  590 +
  591 + rpmsg: rpmsg{
  592 + compatible = "fsl,imx8mq-rpmsg";
  593 + status = "disabled";
  594 + };
  595 + };
  596 +
  597 + ocotp: ocotp-ctrl@30350000 {
  598 + compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
  599 + reg = <0 0x30350000 0 0x10000>;
  600 + clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
  601 + /* For nvmem subnodes */
  602 + #address-cells = <1>;
  603 + #size-cells = <1>;
  604 + };
  605 +
  606 + dispmix_gpr: display-gpr@32e28000 {
  607 + compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
  608 + reg = <0x0 0x32e28000 0x0 0x100>;
  609 + };
  610 +
  611 + usbotg1: usb@32e40000 {
  612 + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
  613 + reg = <0x0 0x32e40000 0x0 0x200>;
  614 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  615 + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
  616 + clock-names = "usb1_ctrl_root_clk";
  617 + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>,
  618 + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>;
  619 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
  620 + <&clk IMX8MM_SYS_PLL1_100M>;
  621 + fsl,usbphy = <&usbphynop1>;
  622 + fsl,usbmisc = <&usbmisc1 0>;
  623 + power-domains = <&usb_otg1_pd>;
  624 + status = "disabled";
  625 + };
  626 +
  627 + usbphynop1: usbphynop1 {
  628 + compatible = "usb-nop-xceiv";
  629 + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
  630 + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
  631 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
  632 + clock-names = "main_clk";
  633 + };
  634 +
  635 + usbmisc1: usbmisc@32e40200 {
  636 + #index-cells = <1>;
  637 + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  638 + reg = <0x0 0x32e40200 0x0 0x200>;
  639 + };
  640 +
  641 + usbotg2: usb@32e50000 {
  642 + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
  643 + reg = <0x0 0x32e50000 0x0 0x200>;
  644 + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  645 + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
  646 + clock-names = "usb1_ctrl_root_clk";
  647 + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>,
  648 + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>;
  649 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
  650 + <&clk IMX8MM_SYS_PLL1_100M>;
  651 + fsl,usbphy = <&usbphynop2>;
  652 + fsl,usbmisc = <&usbmisc2 0>;
  653 + power-domains = <&usb_otg2_pd>;
  654 + status = "disabled";
  655 + };
  656 +
  657 + usbphynop2: usbphynop2 {
  658 + compatible = "usb-nop-xceiv";
  659 + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
  660 + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
  661 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
  662 + clock-names = "main_clk";
  663 + };
  664 +
  665 + usbmisc2: usbmisc@32e50200 {
  666 + #index-cells = <1>;
  667 + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  668 + reg = <0x0 0x32e50200 0x0 0x200>;
  669 + };
  670 +
  671 + usdhc1: mmc@30b40000 {
  672 + compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  673 + reg = <0x0 0x30b40000 0x0 0x10000>;
  674 + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  675 + clocks = <&clk IMX8MM_CLK_DUMMY>,
  676 + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
  677 + <&clk IMX8MM_CLK_USDHC1_ROOT>;
  678 + clock-names = "ipg", "ahb", "per";
  679 + assigned-clocks = <&clk IMX8MM_CLK_USDHC1_DIV>;
  680 + assigned-clock-rates = <400000000>;
  681 + fsl,tuning-start-tap = <20>;
  682 + fsl,tuning-step= <2>;
  683 + bus-width = <4>;
  684 + status = "disabled";
  685 + };
  686 +
  687 + usdhc2: mmc@30b50000 {
  688 + compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  689 + reg = <0x0 0x30b50000 0x0 0x10000>;
  690 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  691 + clocks = <&clk IMX8MM_CLK_DUMMY>,
  692 + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
  693 + <&clk IMX8MM_CLK_USDHC2_ROOT>;
  694 + clock-names = "ipg", "ahb", "per";
  695 + fsl,tuning-start-tap = <20>;
  696 + fsl,tuning-step= <2>;
  697 + bus-width = <4>;
  698 + status = "disabled";
  699 + };
  700 +
  701 + usdhc3: mmc@30b60000 {
  702 + compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  703 + reg = <0x0 0x30b60000 0x0 0x10000>;
  704 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  705 + clocks = <&clk IMX8MM_CLK_DUMMY>,
  706 + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
  707 + <&clk IMX8MM_CLK_USDHC3_ROOT>;
  708 + clock-names = "ipg", "ahb", "per";
  709 + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
  710 + assigned-clock-rates = <400000000>;
  711 + fsl,tuning-start-tap = <20>;
  712 + fsl,tuning-step= <2>;
  713 + bus-width = <4>;
  714 + status = "disabled";
  715 + };
  716 +
  717 + sai1: sai@30010000 {
  718 + compatible = "fsl,imx8mq-sai",
  719 + "fsl,imx6sx-sai";
  720 + reg = <0x0 0x30010000 0x0 0x10000>;
  721 + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  722 + clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
  723 + <&clk IMX8MM_CLK_DUMMY>,
  724 + <&clk IMX8MM_CLK_SAI1_ROOT>,
  725 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
  726 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  727 + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
  728 + dma-names = "rx", "tx";
  729 + fsl,dataline = <0 0xff 0xff>;
  730 + status = "disabled";
  731 + };
  732 +
  733 + sai2: sai@30020000 {
  734 + compatible = "fsl,imx8mq-sai",
  735 + "fsl,imx6sx-sai";
  736 + reg = <0x0 0x30020000 0x0 0x10000>;
  737 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  738 + clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
  739 + <&clk IMX8MM_CLK_DUMMY>,
  740 + <&clk IMX8MM_CLK_SAI2_ROOT>,
  741 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
  742 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  743 + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
  744 + dma-names = "rx", "tx";
  745 + status = "disabled";
  746 + };
  747 +
  748 + sai3: sai@30030000 {
  749 + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
  750 + reg = <0x0 0x30030000 0x0 0x10000>;
  751 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  752 + clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
  753 + <&clk IMX8MM_CLK_DUMMY>,
  754 + <&clk IMX8MM_CLK_SAI3_ROOT>,
  755 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
  756 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  757 + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
  758 + dma-names = "rx", "tx";
  759 + status = "disabled";
  760 + };
  761 +
  762 + sai5: sai@30050000 {
  763 + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
  764 + reg = <0x0 0x30050000 0x0 0x10000>;
  765 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  766 + clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
  767 + <&clk IMX8MM_CLK_DUMMY>,
  768 + <&clk IMX8MM_CLK_SAI5_ROOT>,
  769 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
  770 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  771 + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
  772 + dma-names = "rx", "tx";
  773 + fsl,shared-interrupt;
  774 + fsl,dataline = <0 0xf 0xf>;
  775 + status = "disabled";
  776 + };
  777 +
  778 + sai6: sai@30060000 {
  779 + compatible = "fsl,imx8mq-sai",
  780 + "fsl,imx6sx-sai";
  781 + reg = <0x0 0x30060000 0x0 0x10000>;
  782 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  783 + clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
  784 + <&clk IMX8MM_CLK_DUMMY>,
  785 + <&clk IMX8MM_CLK_SAI6_ROOT>,
  786 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
  787 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
  788 + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
  789 + dma-names = "rx", "tx";
  790 + fsl,shared-interrupt;
  791 + status = "disabled";
  792 + };
  793 +
  794 + micfil: micfil@30080000 {
  795 + compatible = "fsl,imx8mm-micfil";
  796 + reg = <0x0 0x30080000 0x0 0x10000>;
  797 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
  798 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  799 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  800 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  801 + clocks = <&clk IMX8MM_CLK_PDM_IPG>,
  802 + <&clk IMX8MM_CLK_PDM_ROOT>,
  803 + <&clk IMX8MM_AUDIO_PLL1_OUT>,
  804 + <&clk IMX8MM_AUDIO_PLL2_OUT>,
  805 + <&clk IMX8MM_CLK_EXT3>;
  806 + clock-names = "ipg_clk", "ipg_clk_app",
  807 + "pll8k", "pll11k", "clkext3";
  808 + dmas = <&sdma2 24 26 0x80000000>;
  809 + dma-names = "rx";
  810 + status = "disabled";
  811 + };
  812 +
  813 + spdif1: spdif@30090000 {
  814 + compatible = "fsl,imx8mm-spdif";
  815 + reg = <0x0 0x30090000 0x0 0x10000>;
  816 + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  817 + clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* core */
  818 + <&clk IMX8MM_CLK_24M>, /* rxtx0 */
  819 + <&clk IMX8MM_CLK_SPDIF1_DIV>, /* rxtx1 */
  820 + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
  821 + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
  822 + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
  823 + <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* rxtx5 */
  824 + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
  825 + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
  826 + <&clk IMX8MM_CLK_DUMMY>; /* spba */
  827 + clock-names = "core", "rxtx0",
  828 + "rxtx1", "rxtx2",
  829 + "rxtx3", "rxtx4",
  830 + "rxtx5", "rxtx6",
  831 + "rxtx7", "spba";
  832 + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
  833 + dma-names = "rx", "tx";
  834 + status = "disabled";
  835 + };
  836 +
  837 + sdma1: dma-controller@30bd0000 {
  838 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
  839 + reg = <0x0 0x30bd0000 0x0 0x10000>;
  840 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  841 + clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
  842 + <&clk IMX8MM_CLK_SDMA1_ROOT>;
  843 + clock-names = "ipg", "ahb";
  844 + #dma-cells = <3>;
  845 + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  846 + status = "okay";
  847 + };
  848 +
  849 + sdma2: dma-controller@302c0000 {
  850 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
  851 + reg = <0x0 0x302c0000 0x0 0x10000>;
  852 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  853 + clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
  854 + <&clk IMX8MM_CLK_SDMA2_ROOT>;
  855 + clock-names = "ipg", "ahb";
  856 + #dma-cells = <3>;
  857 + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  858 + fsl,ratio-1-1;
  859 + status = "okay";
  860 + };
  861 +
  862 + sdma3: dma-controller@302b0000 {
  863 + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
  864 + reg = <0x0 0x302b0000 0x0 0x10000>;
  865 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  866 + clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
  867 + <&clk IMX8MM_CLK_SDMA3_ROOT>;
  868 + clock-names = "ipg", "ahb";
  869 + #dma-cells = <3>;
  870 + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  871 + fsl,ratio-1-1;
  872 + status = "okay";
  873 + };
  874 +
  875 + wdog1: wdog@30280000 {
  876 + compatible = "fsl,imx21-wdt";
  877 + reg = <0 0x30280000 0 0x10000>;
  878 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  879 + clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
  880 + status = "disabled";
  881 + };
  882 +
  883 + wdog2: wdog@30290000 {
  884 + compatible = "fsl,imx21-wdt";
  885 + reg = <0 0x30290000 0 0x10000>;
  886 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  887 + clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
  888 + status = "disabled";
  889 + };
  890 +
  891 + wdog3: wdog@302a0000 {
  892 + compatible = "fsl,imx21-wdt";
  893 + reg = <0 0x302a0000 0 0x10000>;
  894 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  895 + clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
  896 + status = "disabled";
  897 + };
  898 +
  899 + flexspi: flexspi@30bb0000 {
  900 + #address-cells = <1>;
  901 + #size-cells = <0>;
  902 + compatible = "fsl,imx8mm-flexspi";
  903 + reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
  904 + reg-names = "FlexSPI", "FlexSPI-memory";
  905 + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  906 + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>;
  907 + clock-names = "fspi";
  908 + assigned-clock-rates = <80000000>;
  909 + assigned-clocks = <&clk IMX8MM_CLK_QSPI_SRC>;
  910 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
  911 + status = "disabled";
  912 + };
  913 +
  914 + ecspi1: ecspi@30820000 {
  915 + #address-cells = <1>;
  916 + #size-cells = <0>;
  917 + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  918 + reg = <0x0 0x30820000 0x0 0x10000>;
  919 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  920 + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
  921 + <&clk IMX8MM_CLK_ECSPI1_ROOT>;
  922 + clock-names = "ipg", "per";
  923 + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
  924 + dma-names = "rx", "tx";
  925 + status = "disabled";
  926 + };
  927 +
  928 + ecspi2: ecspi@30830000 {
  929 + #address-cells = <1>;
  930 + #size-cells = <0>;
  931 + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  932 + reg = <0x0 0x30830000 0x0 0x10000>;
  933 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  934 + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
  935 + <&clk IMX8MM_CLK_ECSPI2_ROOT>;
  936 + clock-names = "ipg", "per";
  937 + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
  938 + dma-names = "rx", "tx";
  939 + status = "disabled";
  940 + };
  941 +
  942 + ecspi3: ecspi@30840000 {
  943 + #address-cells = <1>;
  944 + #size-cells = <0>;
  945 + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  946 + reg = <0x0 0x30840000 0x0 0x10000>;
  947 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  948 + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
  949 + <&clk IMX8MM_CLK_ECSPI3_ROOT>;
  950 + clock-names = "ipg", "per";
  951 + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
  952 + dma-names = "rx", "tx";
  953 + status = "disabled";
  954 + };
  955 +
  956 + fec1: ethernet@30be0000 {
  957 + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
  958 + reg = <0x0 0x30be0000 0x0 0x10000>;
  959 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  960 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
  961 + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
  962 + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
  963 + <&clk IMX8MM_CLK_ENET1_ROOT>,
  964 + <&clk IMX8MM_CLK_ENET_TIMER_DIV>,
  965 + <&clk IMX8MM_CLK_ENET_REF_DIV>,
  966 + <&clk IMX8MM_CLK_ENET_PHY_REF_DIV>;
  967 + clock-names = "ipg", "ahb", "ptp",
  968 + "enet_clk_ref", "enet_out";
  969 + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI_SRC>,
  970 + <&clk IMX8MM_CLK_ENET_TIMER_SRC>,
  971 + <&clk IMX8MM_CLK_ENET_REF_SRC>,
  972 + <&clk IMX8MM_CLK_ENET_TIMER_DIV>;
  973 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
  974 + <&clk IMX8MM_SYS_PLL2_100M>,
  975 + <&clk IMX8MM_SYS_PLL2_125M>;
  976 + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
  977 + stop-mode = <&gpr 0x10 3>;
  978 + fsl,num-tx-queues=<3>;
  979 + fsl,num-rx-queues=<3>;
  980 + fsl,wakeup_irq = <2>;
  981 + status = "disabled";
  982 + };
  983 +
  984 + dma_cap: dma_cap {
  985 + compatible = "dma-capability";
  986 + only-dma-mask32 = <1>;
  987 + };
  988 +
  989 + imx_ion: imx_ion {
  990 + compatible = "fsl,mxc-ion";
  991 + fsl,heap-id = <0>;
  992 + };
  993 +
  994 + lcdif: lcdif@32E00000 {
  995 + #address-cells = <1>;
  996 + #size-cells = <0>;
  997 + compatible = "fsl,imx8mm-lcdif";
  998 + reg = <0x0 0x32e00000 0x0 0x10000>;
  999 + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>,
  1000 + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
  1001 + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
  1002 + clock-names = "pix", "disp-axi", "disp-apb";
  1003 + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>,
  1004 + <&clk IMX8MM_CLK_DISP_AXI_SRC>,
  1005 + <&clk IMX8MM_CLK_DISP_APB_SRC>;
  1006 + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
  1007 + <&clk IMX8MM_SYS_PLL2_1000M>,
  1008 + <&clk IMX8MM_SYS_PLL1_800M>;
  1009 + assigned-clock-rate = <594000000>, <500000000>, <200000000>;
  1010 + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  1011 + lcdif-gpr = <&dispmix_gpr>;
  1012 + power-domains = <&dispmix_pd>;
  1013 + status = "disabled";
  1014 +
  1015 + lcdif_disp0: port@0 {
  1016 + reg = <0>;
  1017 +
  1018 + lcdif_to_dsim: endpoint {
  1019 + remote-endpoint = <&dsim_from_lcdif>;
  1020 + };
  1021 + };
  1022 + };
  1023 +
  1024 + mipi_dsi: mipi_dsi@32E10000 {
  1025 + #address-cells = <1>;
  1026 + #size-cells = <0>;
  1027 + compatible = "fsl,imx8mm-mipi-dsim";
  1028 + reg = <0x0 0x32e10000 0x0 0x400>;
  1029 + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>,
  1030 + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>;
  1031 + clock-names = "cfg", "pll-ref";
  1032 + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>,
  1033 + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>;
  1034 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
  1035 + <&clk IMX8MM_VIDEO_PLL1_OUT>;
  1036 + assigned-clock-rates = <266000000>, <594000000>;
  1037 + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  1038 + dsi-gpr = <&dispmix_gpr>;
  1039 + power-domains = <&mipi_pd>;
  1040 + status = "disabled";
  1041 +
  1042 + port@0 {
  1043 + dsim_from_lcdif: endpoint {
  1044 + remote-endpoint = <&lcdif_to_dsim>;
  1045 + };
  1046 + };
  1047 + };
  1048 +
  1049 + display-subsystem {
  1050 + compatible = "fsl,imx-display-subsystem";
  1051 + ports = <&lcdif_disp0>;
  1052 + };
  1053 +
  1054 + pcie0: pcie@0x33800000 {
  1055 + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
  1056 + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x32f00000 0x0 0x10000>,
  1057 + <0x0 0x1ff00000 0x0 0x80000>;
  1058 + reg-names = "dbi", "phy", "config";
  1059 + reserved-region = <&rpmsg_reserved>;
  1060 + #address-cells = <3>;
  1061 + #size-cells = <2>;
  1062 + device_type = "pci";
  1063 + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
  1064 + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
  1065 + num-lanes = <1>;
  1066 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  1067 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
  1068 + interrupt-names = "msi";
  1069 + #interrupt-cells = <1>;
  1070 + interrupt-map-mask = <0 0 0 0x7>;
  1071 + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  1072 + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  1073 + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  1074 + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  1075 + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
  1076 + <&clk IMX8MM_CLK_PCIE1_AUX_CG>,
  1077 + <&clk IMX8MM_CLK_PCIE1_PHY_CG>;
  1078 + clock-names = "pcie", "pcie_bus", "pcie_phy";
  1079 + fsl,max-link-speed = <2>;
  1080 + ctrl-id = <0>;
  1081 + power-domains = <&pcie0_pd>;
  1082 + status = "disabled";
  1083 + };
  1084 +
  1085 + pwm1: pwm@30660000 {
  1086 + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  1087 + reg = <0x0 0x30660000 0x0 0x10000>;
  1088 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  1089 + clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
  1090 + <&clk IMX8MM_CLK_PWM1_ROOT>;
  1091 + clock-names = "ipg", "per";
  1092 + #pwm-cells = <2>;
  1093 + status = "disabled";
  1094 + };
  1095 +
  1096 + pwm2: pwm@30670000 {
  1097 + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  1098 + reg = <0x0 0x30670000 0x0 0x10000>;
  1099 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  1100 + clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
  1101 + <&clk IMX8MM_CLK_PWM2_ROOT>;
  1102 + clock-names = "ipg", "per";
  1103 + #pwm-cells = <2>;
  1104 + status = "disabled";
  1105 + };
  1106 +
  1107 + pwm3: pwm@30680000 {
  1108 + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  1109 + reg = <0x0 0x30680000 0x0 0x10000>;
  1110 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  1111 + clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
  1112 + <&clk IMX8MM_CLK_PWM3_ROOT>;
  1113 + clock-names = "ipg", "per";
  1114 + #pwm-cells = <2>;
  1115 + status = "disabled";
  1116 + };
  1117 +
  1118 + pwm4: pwm@30690000 {
  1119 + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  1120 + reg = <0x0 0x30690000 0x0 0x10000>;
  1121 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  1122 + clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
  1123 + <&clk IMX8MM_CLK_PWM4_ROOT>;
  1124 + clock-names = "ipg", "per";
  1125 + #pwm-cells = <2>;
  1126 + status = "disabled";
  1127 + };
  1128 +
  1129 + vpu_h1: vpu_h1@38320000 {
  1130 + compatible = "nxp,imx8mm-hantro-h1";
  1131 + reg = <0x0 0x38320000 0x0 0x10000>;
  1132 + reg-names = "regs_hantro_h1";
  1133 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1134 + interrupt-names = "irq_hantro_h1";
  1135 + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
  1136 + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus";
  1137 + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1_SRC>,<&clk IMX8MM_CLK_VPU_BUS_SRC>;
  1138 + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
  1139 + assigned-clock-rates = <600000000>, <800000000>;
  1140 + power-domains = <&vpu_h1_pd>;
  1141 + status = "disabled";
  1142 + };
  1143 +
  1144 + vpu_g1: vpu_g1@38300000 {
  1145 + compatible = "nxp,imx8mm-hantro";
  1146 + reg = <0x0 0x38300000 0x0 0x100000>;
  1147 + reg-names = "regs_hantro";
  1148 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  1149 + interrupt-names = "irq_hantro";
  1150 + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
  1151 + clock-names = "clk_hantro", "clk_hantro_bus";
  1152 + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>;
  1153 + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
  1154 + assigned-clock-rates = <600000000>, <800000000>;
  1155 + power-domains = <&vpu_g1_pd>;
  1156 + status = "disabled";
  1157 + };
  1158 +
  1159 + vpu_g2: vpu_g2@38310000 {
  1160 + compatible = "nxp,imx8mm-hantro";
  1161 + reg = <0x0 0x38310000 0x0 0x100000>;
  1162 + reg-names = "regs_hantro";
  1163 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  1164 + interrupt-names = "irq_hantro";
  1165 + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
  1166 + clock-names = "clk_hantro", "clk_hantro_bus";
  1167 + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>;
  1168 + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
  1169 + assigned-clock-rates = <600000000>, <800000000>;
  1170 + power-domains = <&vpu_g2_pd>;
  1171 + status = "disabled";
  1172 + };
  1173 +
  1174 + gpu: gpu@38000000 {
  1175 + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu";
  1176 + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>,
  1177 + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>;
  1178 + reg-names = "iobase_3d", "iobase_2d",
  1179 + "phys_baseaddr", "contiguous_mem";
  1180 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  1181 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  1182 + interrupt-names = "irq_3d", "irq_2d";
  1183 + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>,
  1184 + <&clk IMX8MM_CLK_DUMMY>,
  1185 + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
  1186 + <&clk IMX8MM_CLK_GPU_AHB_DIV>,
  1187 + <&clk IMX8MM_CLK_GPU2D_ROOT>,
  1188 + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
  1189 + <&clk IMX8MM_CLK_GPU_AHB_DIV>;
  1190 + clock-names = "gpu3d_clk", "gpu3d_shader_clk",
  1191 + "gpu3d_axi_clk", "gpu3d_ahb_clk",
  1192 + "gpu2d_clk", "gpu2d_axi_clk",
  1193 + "gpu2d_ahb_clk";
  1194 +
  1195 + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_CLK_GPU_AHB_DIV>;
  1196 + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_SYS_PLL1_800M>;
  1197 + assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>, <400000000>;
  1198 +
  1199 + power-domains = <&gpumix_pd>;
  1200 +
  1201 + status = "disabled";
  1202 + };
  1203 +
  1204 + crypto: caam@30900000 {
  1205 + compatible = "fsl,sec-v4.0";
  1206 + #address-cells = <0x1>;
  1207 + #size-cells = <0x1>;
  1208 + reg = <0 0x30900000 0 0x40000>;
  1209 + ranges = <0 0 0x30900000 0x40000>;
  1210 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  1211 +
  1212 + sec_jr0: jr0@1000 {
  1213 + compatible = "fsl,sec-v4.0-job-ring";
  1214 + reg = <0x1000 0x1000>;
  1215 + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  1216 + };
  1217 +
  1218 + sec_jr1: jr1@2000 {
  1219 + compatible = "fsl,sec-v4.0-job-ring";
  1220 + reg = <0x2000 0x1000>;
  1221 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  1222 + };
  1223 +
  1224 + sec_jr2: jr2@3000 {
  1225 + compatible = "fsl,sec-v4.0-job-ring";
  1226 + reg = <0x3000 0x1000>;
  1227 + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  1228 + };
  1229 + };
  1230 +
  1231 + caam_sm: caam-sm@00100000 {
  1232 + compatible = "fsl,imx6q-caam-sm";
  1233 + reg = <0 0x00100000 0 0x8000>;
  1234 + };
  1235 +
  1236 + caam_snvs: caam-snvs@30370000 {
  1237 + compatible = "fsl,imx6q-caam-snvs";
  1238 + reg = <0 0x30370000 0 0x10000>;
  1239 + };
  1240 +
  1241 + irq_sec_vio: caam_secvio {
  1242 + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
  1243 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  1244 + jtag-tamper = "disabled";
  1245 + watchdog-tamper = "enabled";
  1246 + internal-boot-tamper = "enabled";
  1247 + external-pin-tamper = "disabled";
  1248 + };
  1249 +
  1250 + dma_apbh: dma-apbh@33000000 {
  1251 + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
  1252 + reg = <0 0x33000000 0 0x2000>;
  1253 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  1254 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  1255 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  1256 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  1257 + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  1258 + #dma-cells = <1>;
  1259 + dma-channels = <4>;
  1260 + clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
  1261 + };
  1262 +
  1263 + gpmi: gpmi-nand@33002000{
  1264 + compatible = "fsl,imx7d-gpmi-nand";
  1265 + #address-cells = <1>;
  1266 + #size-cells = <1>;
  1267 + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
  1268 + reg-names = "gpmi-nand", "bch";
  1269 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  1270 + interrupt-names = "bch";
  1271 + clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
  1272 + <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
  1273 + clock-names = "gpmi_io", "gpmi_bch_apb";
  1274 + dmas = <&dma_apbh 0>;
  1275 + dma-names = "rx-tx";
  1276 + status = "disabled";
  1277 + };
  1278 +};
  1279 +
  1280 +&A53_0 {
  1281 + operating-points = <
  1282 + /* kHz uV */
  1283 + 1800000 1000000
  1284 + 1600000 950000
  1285 + 1200000 850000
  1286 + >;
  1287 + clocks = <&clk IMX8MM_CLK_A53_DIV>, <&clk IMX8MM_CLK_A53_SRC>,
  1288 + <&clk IMX8MM_ARM_PLL>, <&clk IMX8MM_ARM_PLL_OUT>,
  1289 + <&clk IMX8MM_SYS_PLL1_800M>;
  1290 + clock-names = "a53", "arm_a53_src", "arm_pll",
  1291 + "arm_pll_out", "sys1_pll_800m";
  1292 + clock-latency = <61036>;
  1293 + #cooling-cells = <2>;
  1294 +};
include/dt-bindings/clock/imx8mm-clock.h
Diff comments   View file @ b0aaad9
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
  10 +#define __DT_BINDINGS_CLOCK_IMX8MM_H
  11 +
  12 +#define IMX8MM_CLK_DUMMY 0
  13 +#define IMX8MM_CLK_32K 1
  14 +#define IMX8MM_CLK_24M 2
  15 +#define IMX8MM_OSC_HDMI_CLK 3
  16 +#define IMX8MM_CLK_EXT1 4
  17 +#define IMX8MM_CLK_EXT2 5
  18 +#define IMX8MM_CLK_EXT3 6
  19 +#define IMX8MM_CLK_EXT4 7
  20 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8
  21 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9
  22 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10
  23 +#define IMX8MM_DRAM_PLL_REF_SEL 11
  24 +#define IMX8MM_GPU_PLL_REF_SEL 12
  25 +#define IMX8MM_VPU_PLL_REF_SEL 13
  26 +#define IMX8MM_ARM_PLL_REF_SEL 14
  27 +#define IMX8MM_SYS_PLL1_REF_SEL 15
  28 +#define IMX8MM_SYS_PLL2_REF_SEL 16
  29 +#define IMX8MM_SYS_PLL3_REF_SEL 17
  30 +#define IMX8MM_AUDIO_PLL1 18
  31 +#define IMX8MM_AUDIO_PLL2 19
  32 +#define IMX8MM_VIDEO_PLL1 20
  33 +#define IMX8MM_DRAM_PLL 21
  34 +#define IMX8MM_GPU_PLL 22
  35 +#define IMX8MM_VPU_PLL 23
  36 +#define IMX8MM_ARM_PLL 24
  37 +#define IMX8MM_SYS_PLL1 25
  38 +#define IMX8MM_SYS_PLL2 26
  39 +#define IMX8MM_SYS_PLL3 27
  40 +#define IMX8MM_AUDIO_PLL1_BYPASS 28
  41 +#define IMX8MM_AUDIO_PLL2_BYPASS 29
  42 +#define IMX8MM_VIDEO_PLL1_BYPASS 30
  43 +#define IMX8MM_DRAM_PLL_BYPASS 31
  44 +#define IMX8MM_GPU_PLL_BYPASS 32
  45 +#define IMX8MM_VPU_PLL_BYPASS 33
  46 +#define IMX8MM_ARM_PLL_BYPASS 34
  47 +#define IMX8MM_SYS_PLL1_BYPASS 35
  48 +#define IMX8MM_SYS_PLL2_BYPASS 36
  49 +#define IMX8MM_SYS_PLL3_BYPASS 37
  50 +#define IMX8MM_AUDIO_PLL1_OUT 38
  51 +#define IMX8MM_AUDIO_PLL2_OUT 39
  52 +#define IMX8MM_VIDEO_PLL1_OUT 40
  53 +#define IMX8MM_DRAM_PLL_OUT 41
  54 +#define IMX8MM_GPU_PLL_OUT 42
  55 +#define IMX8MM_VPU_PLL_OUT 43
  56 +#define IMX8MM_ARM_PLL_OUT 44
  57 +#define IMX8MM_SYS_PLL1_OUT 45
  58 +#define IMX8MM_SYS_PLL2_OUT 46
  59 +#define IMX8MM_SYS_PLL3_OUT 47
  60 +#define IMX8MM_SYS_PLL1_40M 48
  61 +#define IMX8MM_SYS_PLL1_80M 49
  62 +#define IMX8MM_SYS_PLL1_100M 50
  63 +#define IMX8MM_SYS_PLL1_133M 51
  64 +#define IMX8MM_SYS_PLL1_160M 52
  65 +#define IMX8MM_SYS_PLL1_200M 53
  66 +#define IMX8MM_SYS_PLL1_266M 54
  67 +#define IMX8MM_SYS_PLL1_400M 55
  68 +#define IMX8MM_SYS_PLL1_800M 56
  69 +#define IMX8MM_SYS_PLL2_50M 57
  70 +#define IMX8MM_SYS_PLL2_100M 58
  71 +#define IMX8MM_SYS_PLL2_125M 59
  72 +#define IMX8MM_SYS_PLL2_166M 60
  73 +#define IMX8MM_SYS_PLL2_200M 61
  74 +#define IMX8MM_SYS_PLL2_250M 62
  75 +#define IMX8MM_SYS_PLL2_333M 63
  76 +#define IMX8MM_SYS_PLL2_500M 64
  77 +#define IMX8MM_SYS_PLL2_1000M 65
  78 +#define IMX8MM_CLK_A53_SRC 66
  79 +#define IMX8MM_CLK_M4_SRC 67
  80 +#define IMX8MM_CLK_VPU_SRC 68
  81 +#define IMX8MM_CLK_GPU3D_SRC 69
  82 +#define IMX8MM_CLK_GPU2D_SRC 70
  83 +#define IMX8MM_CLK_A53_CG 71
  84 +#define IMX8MM_CLK_M4_CG 72
  85 +#define IMX8MM_CLK_VPU_CG 73
  86 +#define IMX8MM_CLK_GPU3D_CG 74
  87 +#define IMX8MM_CLK_GPU2D_CG 75
  88 +#define IMX8MM_CLK_A53_DIV 76
  89 +#define IMX8MM_CLK_M4_DIV 77
  90 +#define IMX8MM_CLK_VPU_DIV 78
  91 +#define IMX8MM_CLK_GPU3D_DIV 79
  92 +#define IMX8MM_CLK_GPU2D_DIV 80
  93 +#define IMX8MM_CLK_MAIN_AXI_SRC 81
  94 +#define IMX8MM_CLK_ENET_AXI_SRC 82
  95 +#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
  96 +#define IMX8MM_CLK_VPU_BUS_SRC 84
  97 +#define IMX8MM_CLK_DISP_AXI_SRC 85
  98 +#define IMX8MM_CLK_DISP_APB_SRC 86
  99 +#define IMX8MM_CLK_DISP_RTRM_SRC 87
  100 +#define IMX8MM_CLK_USB_BUS_SRC 88
  101 +#define IMX8MM_CLK_GPU_AXI_SRC 89
  102 +#define IMX8MM_CLK_GPU_AHB_SRC 90
  103 +#define IMX8MM_CLK_NOC_SRC 91
  104 +#define IMX8MM_CLK_NOC_APB_SRC 92
  105 +#define IMX8MM_CLK_MAIN_AXI_CG 93
  106 +#define IMX8MM_CLK_ENET_AXI_CG 94
  107 +#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
  108 +#define IMX8MM_CLK_VPU_BUS_CG 96
  109 +#define IMX8MM_CLK_DISP_AXI_CG 97
  110 +#define IMX8MM_CLK_DISP_APB_CG 98
  111 +#define IMX8MM_CLK_DISP_RTRM_CG 99
  112 +#define IMX8MM_CLK_USB_BUS_CG 100
  113 +#define IMX8MM_CLK_GPU_AXI_CG 101
  114 +#define IMX8MM_CLK_GPU_AHB_CG 102
  115 +#define IMX8MM_CLK_NOC_CG 103
  116 +#define IMX8MM_CLK_NOC_APB_CG 104
  117 +#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
  118 +#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
  119 +#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
  120 +#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
  121 +#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
  122 +#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
  123 +#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
  124 +#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
  125 +#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
  126 +#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
  127 +#define IMX8MM_CLK_NOC_PRE_DIV 115
  128 +#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
  129 +#define IMX8MM_CLK_MAIN_AXI_DIV 117
  130 +#define IMX8MM_CLK_ENET_AXI_DIV 118
  131 +#define IMX8MM_CLK_NAND_USDHC_BUS_DIV 119
  132 +#define IMX8MM_CLK_VPU_BUS_DIV 120
  133 +#define IMX8MM_CLK_DISP_AXI_DIV 121
  134 +#define IMX8MM_CLK_DISP_APB_DIV 122
  135 +#define IMX8MM_CLK_DISP_RTRM_DIV 123
  136 +#define IMX8MM_CLK_USB_BUS_DIV 124
  137 +#define IMX8MM_CLK_GPU_AXI_DIV 125
  138 +#define IMX8MM_CLK_GPU_AHB_DIV 126
  139 +#define IMX8MM_CLK_NOC_DIV 127
  140 +#define IMX8MM_CLK_NOC_APB_DIV 128
  141 +#define IMX8MM_CLK_AHB_SRC 129
  142 +#define IMX8MM_CLK_AUDIO_AHB_SRC 130
  143 +#define IMX8MM_CLK_DSI_ESC_RX_SRC 131
  144 +#define IMX8MM_CLK_AHB_CG 132
  145 +#define IMX8MM_CLK_AUDIO_AHB_CG 133
  146 +#define IMX8MM_CLK_DSI_ESC_RX_CG 134
  147 +#define IMX8MM_CLK_AHB_PRE_DIV 135
  148 +#define IMX8MM_CLK_AUDIO_AHB_PRE_DIV 136
  149 +#define IMX8MM_CLK_DSI_ESC_RX_PRE_DIV 137
  150 +#define IMX8MM_CLK_AHB_DIV 138
  151 +#define IMX8MM_CLK_AUDIO_AHB_DIV 139
  152 +#define IMX8MM_CLK_DSI_ESC_RX_DIV 140
  153 +#define IMX8MM_CLK_IPG_ROOT 141
  154 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 142
  155 +#define IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT 143
  156 +#define IMX8MM_CLK_DRAM_ALT_SRC 144
  157 +#define IMX8MM_CLK_DRAM_APB_SRC 145
  158 +#define IMX8MM_CLK_VPU_G1_SRC 146
  159 +#define IMX8MM_CLK_VPU_G2_SRC 147
  160 +#define IMX8MM_CLK_DISP_DTRC_SRC 148
  161 +#define IMX8MM_CLK_DISP_DC8000_SRC 149
  162 +#define IMX8MM_CLK_PCIE1_CTRL_SRC 150
  163 +#define IMX8MM_CLK_PCIE1_PHY_SRC 151
  164 +#define IMX8MM_CLK_PCIE1_AUX_SRC 152
  165 +#define IMX8MM_CLK_DC_PIXEL_SRC 153
  166 +#define IMX8MM_CLK_LCDIF_PIXEL_SRC 154
  167 +#define IMX8MM_CLK_SAI1_SRC 155
  168 +#define IMX8MM_CLK_SAI2_SRC 156
  169 +#define IMX8MM_CLK_SAI3_SRC 157
  170 +#define IMX8MM_CLK_SAI4_SRC 158
  171 +#define IMX8MM_CLK_SAI5_SRC 159
  172 +#define IMX8MM_CLK_SAI6_SRC 160
  173 +#define IMX8MM_CLK_SPDIF1_SRC 161
  174 +#define IMX8MM_CLK_SPDIF2_SRC 162
  175 +#define IMX8MM_CLK_ENET_REF_SRC 163
  176 +#define IMX8MM_CLK_ENET_TIMER_SRC 164
  177 +#define IMX8MM_CLK_ENET_PHY_REF_SRC 165
  178 +#define IMX8MM_CLK_NAND_SRC 166
  179 +#define IMX8MM_CLK_QSPI_SRC 167
  180 +#define IMX8MM_CLK_USDHC1_SRC 168
  181 +#define IMX8MM_CLK_USDHC2_SRC 169
  182 +#define IMX8MM_CLK_I2C1_SRC 170
  183 +#define IMX8MM_CLK_I2C2_SRC 171
  184 +#define IMX8MM_CLK_I2C3_SRC 172
  185 +#define IMX8MM_CLK_I2C4_SRC 173
  186 +#define IMX8MM_CLK_UART1_SRC 174
  187 +#define IMX8MM_CLK_UART2_SRC 175
  188 +#define IMX8MM_CLK_UART3_SRC 176
  189 +#define IMX8MM_CLK_UART4_SRC 177
  190 +#define IMX8MM_CLK_USB_CORE_REF_SRC 178
  191 +#define IMX8MM_CLK_USB_PHY_REF_SRC 179
  192 +#define IMX8MM_CLK_ECSPI1_SRC 180
  193 +#define IMX8MM_CLK_ECSPI2_SRC 181
  194 +#define IMX8MM_CLK_PWM1_SRC 182
  195 +#define IMX8MM_CLK_PWM2_SRC 183
  196 +#define IMX8MM_CLK_PWM3_SRC 184
  197 +#define IMX8MM_CLK_PWM4_SRC 185
  198 +#define IMX8MM_CLK_GPT1_SRC 186
  199 +#define IMX8MM_CLK_WDOG_SRC 187
  200 +#define IMX8MM_CLK_WRCLK_SRC 188
  201 +#define IMX8MM_CLK_DSI_CORE_SRC 189
  202 +#define IMX8MM_CLK_DSI_PHY_REF_SRC 190
  203 +#define IMX8MM_CLK_DSI_DBI_SRC 191
  204 +#define IMX8MM_CLK_USDHC3_SRC 192
  205 +#define IMX8MM_CLK_CSI1_CORE_SRC 193
  206 +#define IMX8MM_CLK_CSI1_PHY_REF_SRC 194
  207 +#define IMX8MM_CLK_CSI1_ESC_SRC 195
  208 +#define IMX8MM_CLK_CSI2_CORE_SRC 196
  209 +#define IMX8MM_CLK_CSI2_PHY_REF_SRC 197
  210 +#define IMX8MM_CLK_CSI2_ESC_SRC 198
  211 +#define IMX8MM_CLK_PCIE2_CTRL_SRC 199
  212 +#define IMX8MM_CLK_PCIE2_PHY_SRC 200
  213 +#define IMX8MM_CLK_PCIE2_AUX_SRC 201
  214 +#define IMX8MM_CLK_ECSPI3_SRC 202
  215 +#define IMX8MM_CLK_PDM_SRC 203
  216 +#define IMX8MM_CLK_VPU_H1_SRC 204
  217 +#define IMX8MM_CLK_DRAM_ALT_CG 205
  218 +#define IMX8MM_CLK_DRAM_APB_CG 206
  219 +#define IMX8MM_CLK_VPU_G1_CG 207
  220 +#define IMX8MM_CLK_VPU_G2_CG 208
  221 +#define IMX8MM_CLK_DISP_DTRC_CG 209
  222 +#define IMX8MM_CLK_DISP_DC8000_CG 210
  223 +#define IMX8MM_CLK_PCIE1_CTRL_CG 211
  224 +#define IMX8MM_CLK_PCIE1_PHY_CG 212
  225 +#define IMX8MM_CLK_PCIE1_AUX_CG 213
  226 +#define IMX8MM_CLK_DC_PIXEL_CG 214
  227 +#define IMX8MM_CLK_LCDIF_PIXEL_CG 215
  228 +#define IMX8MM_CLK_SAI1_CG 216
  229 +#define IMX8MM_CLK_SAI2_CG 217
  230 +#define IMX8MM_CLK_SAI3_CG 218
  231 +#define IMX8MM_CLK_SAI4_CG 219
  232 +#define IMX8MM_CLK_SAI5_CG 220
  233 +#define IMX8MM_CLK_SAI6_CG 221
  234 +#define IMX8MM_CLK_SPDIF1_CG 222
  235 +#define IMX8MM_CLK_SPDIF2_CG 223
  236 +#define IMX8MM_CLK_ENET_REF_CG 224
  237 +#define IMX8MM_CLK_ENET_TIMER_CG 225
  238 +#define IMX8MM_CLK_ENET_PHY_REF_CG 226
  239 +#define IMX8MM_CLK_NAND_CG 227
  240 +#define IMX8MM_CLK_QSPI_CG 228
  241 +#define IMX8MM_CLK_USDHC1_CG 229
  242 +#define IMX8MM_CLK_USDHC2_CG 230
  243 +#define IMX8MM_CLK_I2C1_CG 231
  244 +#define IMX8MM_CLK_I2C2_CG 232
  245 +#define IMX8MM_CLK_I2C3_CG 233
  246 +#define IMX8MM_CLK_I2C4_CG 234
  247 +#define IMX8MM_CLK_UART1_CG 235
  248 +#define IMX8MM_CLK_UART2_CG 236
  249 +#define IMX8MM_CLK_UART3_CG 237
  250 +#define IMX8MM_CLK_UART4_CG 238
  251 +#define IMX8MM_CLK_USB_CORE_REF_CG 239
  252 +#define IMX8MM_CLK_USB_PHY_REF_CG 240
  253 +#define IMX8MM_CLK_ECSPI1_CG 241
  254 +#define IMX8MM_CLK_ECSPI2_CG 242
  255 +#define IMX8MM_CLK_PWM1_CG 243
  256 +#define IMX8MM_CLK_PWM2_CG 244
  257 +#define IMX8MM_CLK_PWM3_CG 245
  258 +#define IMX8MM_CLK_PWM4_CG 246
  259 +#define IMX8MM_CLK_GPT1_CG 247
  260 +#define IMX8MM_CLK_WDOG_CG 248
  261 +#define IMX8MM_CLK_WRCLK_CG 249
  262 +#define IMX8MM_CLK_DSI_CORE_CG 250
  263 +#define IMX8MM_CLK_DSI_PHY_REF_CG 251
  264 +#define IMX8MM_CLK_DSI_DBI_CG 252
  265 +#define IMX8MM_CLK_USDHC3_CG 253
  266 +#define IMX8MM_CLK_CSI1_CORE_CG 254
  267 +#define IMX8MM_CLK_CSI1_PHY_REF_CG 255
  268 +#define IMX8MM_CLK_CSI1_ESC_CG 256
  269 +#define IMX8MM_CLK_CSI2_CORE_CG 257
  270 +#define IMX8MM_CLK_CSI2_PHY_REF_CG 258
  271 +#define IMX8MM_CLK_CSI2_ESC_CG 259
  272 +#define IMX8MM_CLK_PCIE2_CTRL_CG 260
  273 +#define IMX8MM_CLK_PCIE2_PHY_CG 261
  274 +#define IMX8MM_CLK_PCIE2_AUX_CG 262
  275 +#define IMX8MM_CLK_ECSPI3_CG 263
  276 +#define IMX8MM_CLK_PDM_CG 264
  277 +#define IMX8MM_CLK_VPU_H1_CG 265
  278 +#define IMX8MM_CLK_DRAM_ALT_PRE_DIV 266
  279 +#define IMX8MM_CLK_DRAM_APB_PRE_DIV 267
  280 +#define IMX8MM_CLK_VPU_G1_PRE_DIV 268
  281 +#define IMX8MM_CLK_VPU_G2_PRE_DIV 269
  282 +#define IMX8MM_CLK_DISP_DTRC_PRE_DIV 270
  283 +#define IMX8MM_CLK_DISP_DC8000_PRE_DIV 271
  284 +#define IMX8MM_CLK_PCIE1_CTRL_PRE_DIV 272
  285 +#define IMX8MM_CLK_PCIE1_PHY_PRE_DIV 273
  286 +#define IMX8MM_CLK_PCIE1_AUX_PRE_DIV 274
  287 +#define IMX8MM_CLK_DC_PIXEL_PRE_DIV 275
  288 +#define IMX8MM_CLK_LCDIF_PIXEL_PRE_DIV 276
  289 +#define IMX8MM_CLK_SAI1_PRE_DIV 277
  290 +#define IMX8MM_CLK_SAI2_PRE_DIV 278
  291 +#define IMX8MM_CLK_SAI3_PRE_DIV 279
  292 +#define IMX8MM_CLK_SAI4_PRE_DIV 280
  293 +#define IMX8MM_CLK_SAI5_PRE_DIV 281
  294 +#define IMX8MM_CLK_SAI6_PRE_DIV 282
  295 +#define IMX8MM_CLK_SPDIF1_PRE_DIV 283
  296 +#define IMX8MM_CLK_SPDIF2_PRE_DIV 284
  297 +#define IMX8MM_CLK_ENET_REF_PRE_DIV 285
  298 +#define IMX8MM_CLK_ENET_TIMER_PRE_DIV 286
  299 +#define IMX8MM_CLK_ENET_PHY_REF_PRE_DIV 287
  300 +#define IMX8MM_CLK_NAND_PRE_DIV 288
  301 +#define IMX8MM_CLK_QSPI_PRE_DIV 289
  302 +#define IMX8MM_CLK_USDHC1_PRE_DIV 290
  303 +#define IMX8MM_CLK_USDHC2_PRE_DIV 291
  304 +#define IMX8MM_CLK_I2C1_PRE_DIV 292
  305 +#define IMX8MM_CLK_I2C2_PRE_DIV 293
  306 +#define IMX8MM_CLK_I2C3_PRE_DIV 294
  307 +#define IMX8MM_CLK_I2C4_PRE_DIV 295
  308 +#define IMX8MM_CLK_UART1_PRE_DIV 296
  309 +#define IMX8MM_CLK_UART2_PRE_DIV 297
  310 +#define IMX8MM_CLK_UART3_PRE_DIV 298
  311 +#define IMX8MM_CLK_UART4_PRE_DIV 299
  312 +#define IMX8MM_CLK_USB_CORE_REF_PRE_DIV 300
  313 +#define IMX8MM_CLK_USB_PHY_REF_PRE_DIV 301
  314 +#define IMX8MM_CLK_ECSPI1_PRE_DIV 302
  315 +#define IMX8MM_CLK_ECSPI2_PRE_DIV 303
  316 +#define IMX8MM_CLK_PWM1_PRE_DIV 304
  317 +#define IMX8MM_CLK_PWM2_PRE_DIV 305
  318 +#define IMX8MM_CLK_PWM3_PRE_DIV 306
  319 +#define IMX8MM_CLK_PWM4_PRE_DIV 307
  320 +#define IMX8MM_CLK_GPT1_PRE_DIV 308
  321 +#define IMX8MM_CLK_WDOG_PRE_DIV 309
  322 +#define IMX8MM_CLK_WRCLK_PRE_DIV 310
  323 +#define IMX8MM_CLK_DSI_CORE_PRE_DIV 311
  324 +#define IMX8MM_CLK_DSI_PHY_REF_PRE_DIV 312
  325 +#define IMX8MM_CLK_DSI_DBI_PRE_DIV 313
  326 +#define IMX8MM_CLK_USDHC3_PRE_DIV 314
  327 +#define IMX8MM_CLK_CSI1_CORE_PRE_DIV 315
  328 +#define IMX8MM_CLK_CSI1_PHY_REF_PRE_DIV 316
  329 +#define IMX8MM_CLK_CSI1_ESC_PRE_DIV 317
  330 +#define IMX8MM_CLK_CSI2_CORE_PRE_DIV 318
  331 +#define IMX8MM_CLK_CSI2_PHY_REF_PRE_DIV 319
  332 +#define IMX8MM_CLK_CSI2_ESC_PRE_DIV 320
  333 +#define IMX8MM_CLK_PCIE2_CTRL_PRE_DIV 321
  334 +#define IMX8MM_CLK_PCIE2_PHY_PRE_DIV 322
  335 +#define IMX8MM_CLK_PCIE2_AUX_PRE_DIV 323
  336 +#define IMX8MM_CLK_ECSPI3_PRE_DIV 324
  337 +#define IMX8MM_CLK_PDM_PRE_DIV 325
  338 +#define IMX8MM_CLK_VPU_H1_PRE_DIV 326
  339 +#define IMX8MM_CLK_DRAM_ALT_DIV 327
  340 +#define IMX8MM_CLK_DRAM_APB_DIV 328
  341 +#define IMX8MM_CLK_VPU_G1_DIV 329
  342 +#define IMX8MM_CLK_VPU_G2_DIV 330
  343 +#define IMX8MM_CLK_DISP_DTRC_DIV 331
  344 +#define IMX8MM_CLK_DISP_DC8000_DIV 332
  345 +#define IMX8MM_CLK_PCIE1_CTRL_DIV 333
  346 +#define IMX8MM_CLK_PCIE1_PHY_DIV 334
  347 +#define IMX8MM_CLK_PCIE1_AUX_DIV 335
  348 +#define IMX8MM_CLK_DC_PIXEL_DIV 336
  349 +#define IMX8MM_CLK_LCDIF_PIXEL_DIV 337
  350 +#define IMX8MM_CLK_SAI1_DIV 338
  351 +#define IMX8MM_CLK_SAI2_DIV 339
  352 +#define IMX8MM_CLK_SAI3_DIV 340
  353 +#define IMX8MM_CLK_SAI4_DIV 341
  354 +#define IMX8MM_CLK_SAI5_DIV 342
  355 +#define IMX8MM_CLK_SAI6_DIV 343
  356 +#define IMX8MM_CLK_SPDIF1_DIV 344
  357 +#define IMX8MM_CLK_SPDIF2_DIV 345
  358 +#define IMX8MM_CLK_ENET_REF_DIV 346
  359 +#define IMX8MM_CLK_ENET_TIMER_DIV 347
  360 +#define IMX8MM_CLK_ENET_PHY_REF_DIV 348
  361 +#define IMX8MM_CLK_NAND_DIV 349
  362 +#define IMX8MM_CLK_QSPI_DIV 350
  363 +#define IMX8MM_CLK_USDHC1_DIV 351
  364 +#define IMX8MM_CLK_USDHC2_DIV 352
  365 +#define IMX8MM_CLK_I2C1_DIV 353
  366 +#define IMX8MM_CLK_I2C2_DIV 354
  367 +#define IMX8MM_CLK_I2C3_DIV 355
  368 +#define IMX8MM_CLK_I2C4_DIV 356
  369 +#define IMX8MM_CLK_UART1_DIV 357
  370 +#define IMX8MM_CLK_UART2_DIV 358
  371 +#define IMX8MM_CLK_UART3_DIV 359
  372 +#define IMX8MM_CLK_UART4_DIV 360
  373 +#define IMX8MM_CLK_USB_CORE_REF_DIV 361
  374 +#define IMX8MM_CLK_USB_PHY_REF_DIV 362
  375 +#define IMX8MM_CLK_ECSPI1_DIV 363
  376 +#define IMX8MM_CLK_ECSPI2_DIV 364
  377 +#define IMX8MM_CLK_PWM1_DIV 365
  378 +#define IMX8MM_CLK_PWM2_DIV 366
  379 +#define IMX8MM_CLK_PWM3_DIV 367
  380 +#define IMX8MM_CLK_PWM4_DIV 368
  381 +#define IMX8MM_CLK_GPT1_DIV 369
  382 +#define IMX8MM_CLK_WDOG_DIV 370
  383 +#define IMX8MM_CLK_WRCLK_DIV 371
  384 +#define IMX8MM_CLK_DSI_CORE_DIV 372
  385 +#define IMX8MM_CLK_DSI_PHY_REF_DIV 373
  386 +#define IMX8MM_CLK_DSI_DBI_DIV 374
  387 +#define IMX8MM_CLK_USDHC3_DIV 375
  388 +#define IMX8MM_CLK_CSI1_CORE_DIV 376
  389 +#define IMX8MM_CLK_CSI1_PHY_REF_DIV 377
  390 +#define IMX8MM_CLK_CSI1_ESC_DIV 378
  391 +#define IMX8MM_CLK_CSI2_CORE_DIV 379
  392 +#define IMX8MM_CLK_CSI2_PHY_REF_DIV 380
  393 +#define IMX8MM_CLK_CSI2_ESC_DIV 381
  394 +#define IMX8MM_CLK_PCIE2_CTRL_DIV 382
  395 +#define IMX8MM_CLK_PCIE2_PHY_DIV 383
  396 +#define IMX8MM_CLK_PCIE2_AUX_DIV 384
  397 +#define IMX8MM_CLK_ECSPI3_DIV 385
  398 +#define IMX8MM_CLK_PDM_DIV 386
  399 +#define IMX8MM_CLK_VPU_H1_DIV 387
  400 +#define IMX8MM_CLK_ECSPI1_ROOT 388
  401 +#define IMX8MM_CLK_ECSPI2_ROOT 389
  402 +#define IMX8MM_CLK_ECSPI3_ROOT 390
  403 +#define IMX8MM_CLK_ENET1_ROOT 391
  404 +#define IMX8MM_CLK_GPT1_ROOT 392
  405 +#define IMX8MM_CLK_I2C1_ROOT 393
  406 +#define IMX8MM_CLK_I2C2_ROOT 394
  407 +#define IMX8MM_CLK_I2C3_ROOT 395
  408 +#define IMX8MM_CLK_I2C4_ROOT 396
  409 +#define IMX8MM_CLK_OCOTP_ROOT 397
  410 +#define IMX8MM_CLK_PCIE1_ROOT 398
  411 +#define IMX8MM_CLK_PWM1_ROOT 399
  412 +#define IMX8MM_CLK_PWM2_ROOT 400
  413 +#define IMX8MM_CLK_PWM3_ROOT 401
  414 +#define IMX8MM_CLK_PWM4_ROOT 402
  415 +#define IMX8MM_CLK_QSPI_ROOT 403
  416 +#define IMX8MM_CLK_NAND_ROOT 404
  417 +#define IMX8MM_CLK_SAI1_ROOT 405
  418 +#define IMX8MM_CLK_SAI1_IPG 406
  419 +#define IMX8MM_CLK_SAI2_ROOT 407
  420 +#define IMX8MM_CLK_SAI2_IPG 408
  421 +#define IMX8MM_CLK_SAI3_ROOT 409
  422 +#define IMX8MM_CLK_SAI3_IPG 410
  423 +#define IMX8MM_CLK_SAI4_ROOT 411
  424 +#define IMX8MM_CLK_SAI4_IPG 412
  425 +#define IMX8MM_CLK_SAI5_ROOT 413
  426 +#define IMX8MM_CLK_SAI5_IPG 414
  427 +#define IMX8MM_CLK_SAI6_ROOT 415
  428 +#define IMX8MM_CLK_SAI6_IPG 416
  429 +#define IMX8MM_CLK_UART1_ROOT 417
  430 +#define IMX8MM_CLK_UART2_ROOT 418
  431 +#define IMX8MM_CLK_UART3_ROOT 419
  432 +#define IMX8MM_CLK_UART4_ROOT 420
  433 +#define IMX8MM_CLK_USB1_CTRL_ROOT 421
  434 +#define IMX8MM_CLK_GPU3D_ROOT 422
  435 +#define IMX8MM_CLK_USDHC1_ROOT 423
  436 +#define IMX8MM_CLK_USDHC2_ROOT 424
  437 +#define IMX8MM_CLK_WDOG1_ROOT 425
  438 +#define IMX8MM_CLK_WDOG2_ROOT 426
  439 +#define IMX8MM_CLK_WDOG3_ROOT 427
  440 +#define IMX8MM_CLK_VPU_G1_ROOT 428
  441 +#define IMX8MM_CLK_GPU_BUS_ROOT 429
  442 +#define IMX8MM_CLK_VPU_H1_ROOT 430
  443 +#define IMX8MM_CLK_VPU_G2_ROOT 431
  444 +#define IMX8MM_CLK_PDM_ROOT 432
  445 +#define IMX8MM_CLK_DISP_ROOT 433
  446 +#define IMX8MM_CLK_DISP_AXI_ROOT 434
  447 +#define IMX8MM_CLK_DISP_APB_ROOT 435
  448 +#define IMX8MM_CLK_DISP_RTRM_ROOT 436
  449 +#define IMX8MM_CLK_USDHC3_ROOT 437
  450 +#define IMX8MM_CLK_TMU_ROOT 438
  451 +#define IMX8MM_CLK_VPU_DEC_ROOT 439
  452 +#define IMX8MM_CLK_SDMA1_ROOT 440
  453 +#define IMX8MM_CLK_SDMA2_ROOT 441
  454 +#define IMX8MM_CLK_SDMA3_ROOT 442
  455 +#define IMX8MM_CLK_GPT_3M 443
  456 +#define IMX8MM_CLK_ARM 444
  457 +#define IMX8MM_CLK_PDM_IPG 445
  458 +#define IMX8MM_CLK_GPU2D_ROOT 446
  459 +#define IMX8MM_CLK_MU_ROOT 447
  460 +#define IMX8MM_CLK_CSI1_ROOT 448
  461 +#define IMX8MM_CLK_CLKO1_SRC 449
  462 +#define IMX8MM_CLK_CLKO1_CG 450
  463 +#define IMX8MM_CLK_CLKO1_PRE_DIV 451
  464 +#define IMX8MM_CLK_CLKO1_DIV 452
  465 +
  466 +#define IMX8MM_CLK_DRAM_CORE 453
  467 +#define IMX8MM_CLK_DRAM_ALT_ROOT 454
  468 +
  469 +#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 455
  470 +#define IMX8MM_CLK_SIM_HSIO 456
  471 +
  472 +#define IMX8MM_CLK_END 457
  473 +#endif
include/dt-bindings/pinctrl/pins-imx8mm.h
Diff comments   View file @ b0aaad9
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version 2
  7 + * of the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + */
  14 +
  15 +#ifndef __DTS_IMX8MM_PINFUNC_H
  16 +#define __DTS_IMX8MM_PINFUNC_H
  17 +
  18 +/*
  19 + * The pin function ID is a tuple of
  20 + * <mux_reg conf_reg input_reg mux_mode input_val>
  21 + */
  22 +
  23 +#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
  24 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
  25 +#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
  26 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
  27 +#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
  28 +#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
  29 +#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
  30 +#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
  31 +#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
  32 +#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
  33 +#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
  34 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
  35 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
  36 +#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
  37 +#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
  38 +#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
  39 +#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
  40 +#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
  41 +#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
  42 +#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
  43 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
  44 +#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
  45 +#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
  46 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
  47 +#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
  48 +#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
  49 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
  50 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
  51 +#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
  52 +#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
  53 +#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
  54 +#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
  55 +#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
  56 +#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
  57 +#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
  58 +#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
  59 +#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
  60 +#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
  61 +#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
  62 +#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
  63 +#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
  64 +#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
  65 +#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
  66 +#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
  67 +#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
  68 +#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
  69 +#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
  70 +#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
  71 +#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
  72 +#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
  73 +#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
  74 +#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
  75 +#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
  76 +#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
  77 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
  78 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
  79 +#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
  80 +#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
  81 +#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
  82 +#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
  83 +#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
  84 +#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
  85 +#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
  86 +#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
  87 +#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
  88 +#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
  89 +#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
  90 +#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
  91 +#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
  92 +#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
  93 +#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
  94 +#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
  95 +#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
  96 +#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
  97 +#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
  98 +#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
  99 +#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
  100 +#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
  101 +#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
  102 +#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
  103 +#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
  104 +#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
  105 +#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
  106 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
  107 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
  108 +#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
  109 +#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
  110 +#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
  111 +#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
  112 +#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
  113 +#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
  114 +#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
  115 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
  116 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
  117 +#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
  118 +#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
  119 +#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
  120 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
  121 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
  122 +#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
  123 +#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
  124 +#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
  125 +#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
  126 +#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
  127 +#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
  128 +#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
  129 +#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
  130 +#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
  131 +#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
  132 +#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
  133 +#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
  134 +#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
  135 +#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
  136 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
  137 +#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
  138 +#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
  139 +#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
  140 +#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
  141 +#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
  142 +#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
  143 +#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
  144 +#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
  145 +#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
  146 +#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
  147 +#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
  148 +#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
  149 +#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
  150 +#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
  151 +#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
  152 +#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
  153 +#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
  154 +#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
  155 +#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
  156 +#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
  157 +#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
  158 +#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
  159 +#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
  160 +#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
  161 +#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
  162 +#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
  163 +#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
  164 +#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
  165 +#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
  166 +#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
  167 +#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
  168 +#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
  169 +#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
  170 +#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
  171 +#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
  172 +#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
  173 +#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
  174 +#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
  175 +#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
  176 +#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
  177 +#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
  178 +#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
  179 +#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
  180 +#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
  181 +#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
  182 +#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
  183 +#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
  184 +#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
  185 +#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
  186 +#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
  187 +#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
  188 +#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
  189 +#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
  190 +#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
  191 +#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
  192 +#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
  193 +#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
  194 +#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
  195 +#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
  196 +#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0
  197 +#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
  198 +#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
  199 +#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
  200 +#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
  201 +#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0
  202 +#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
  203 +#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
  204 +#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
  205 +#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
  206 +#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0
  207 +#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
  208 +#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
  209 +#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
  210 +#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
  211 +#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0
  212 +#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
  213 +#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
  214 +#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
  215 +#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
  216 +#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
  217 +#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
  218 +#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
  219 +#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
  220 +#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
  221 +#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
  222 +#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
  223 +#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
  224 +#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
  225 +#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
  226 +#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
  227 +#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
  228 +#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
  229 +#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
  230 +#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
  231 +#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
  232 +#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0
  233 +#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
  234 +#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
  235 +#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
  236 +#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
  237 +#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0
  238 +#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
  239 +#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
  240 +#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
  241 +#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
  242 +#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0
  243 +#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
  244 +#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
  245 +#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
  246 +#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
  247 +#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0
  248 +#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
  249 +#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
  250 +#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
  251 +#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
  252 +#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
  253 +#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
  254 +#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
  255 +#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
  256 +#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0
  257 +#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
  258 +#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
  259 +#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
  260 +#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
  261 +#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
  262 +#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
  263 +#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0
  264 +#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
  265 +#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
  266 +#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
  267 +#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0
  268 +#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
  269 +#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
  270 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
  271 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
  272 +#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
  273 +#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
  274 +#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
  275 +#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0
  276 +#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
  277 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
  278 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
  279 +#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0
  280 +#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
  281 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
  282 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
  283 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
  284 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
  285 +#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0
  286 +#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
  287 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
  288 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
  289 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
  290 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
  291 +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0
  292 +#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
  293 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
  294 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
  295 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
  296 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
  297 +#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0
  298 +#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
  299 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
  300 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
  301 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
  302 +#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
  303 +#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
  304 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
  305 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
  306 +#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
  307 +#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
  308 +#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
  309 +#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
  310 +#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
  311 +#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
  312 +#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
  313 +#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
  314 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
  315 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
  316 +#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1
  317 +#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
  318 +#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
  319 +#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
  320 +#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
  321 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
  322 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
  323 +#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1
  324 +#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
  325 +#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
  326 +#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
  327 +#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
  328 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
  329 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
  330 +#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1
  331 +#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
  332 +#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
  333 +#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
  334 +#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
  335 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
  336 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
  337 +#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1
  338 +#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
  339 +#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
  340 +#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
  341 +#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
  342 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
  343 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
  344 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
  345 +#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
  346 +#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
  347 +#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
  348 +#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
  349 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
  350 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
  351 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
  352 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
  353 +#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
  354 +#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
  355 +#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
  356 +#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
  357 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
  358 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
  359 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
  360 +#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
  361 +#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
  362 +#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
  363 +#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
  364 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
  365 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
  366 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
  367 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
  368 +#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
  369 +#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
  370 +#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
  371 +#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
  372 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
  373 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
  374 +#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
  375 +#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
  376 +#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
  377 +#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
  378 +#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
  379 +#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
  380 +#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
  381 +#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
  382 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
  383 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
  384 +#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
  385 +#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
  386 +#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
  387 +#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
  388 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
  389 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
  390 +#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
  391 +#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
  392 +#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
  393 +#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
  394 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
  395 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
  396 +#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
  397 +#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
  398 +#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
  399 +#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
  400 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
  401 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
  402 +#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
  403 +#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
  404 +#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
  405 +#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
  406 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
  407 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
  408 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
  409 +#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
  410 +#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
  411 +#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
  412 +#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
  413 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
  414 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
  415 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
  416 +#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
  417 +#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
  418 +#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
  419 +#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
  420 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
  421 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
  422 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
  423 +#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
  424 +#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
  425 +#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
  426 +#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
  427 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
  428 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
  429 +#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0
  430 +#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
  431 +#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
  432 +#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
  433 +#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
  434 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
  435 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
  436 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
  437 +#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0
  438 +#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
  439 +#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
  440 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
  441 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
  442 +#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
  443 +#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
  444 +#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
  445 +#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
  446 +#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
  447 +#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
  448 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
  449 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
  450 +#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
  451 +#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
  452 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
  453 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
  454 +#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
  455 +#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
  456 +#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
  457 +#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
  458 +#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
  459 +#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
  460 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
  461 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
  462 +#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
  463 +#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
  464 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
  465 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
  466 +#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
  467 +#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
  468 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
  469 +#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
  470 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
  471 +#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
  472 +#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
  473 +#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
  474 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
  475 +#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
  476 +#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
  477 +#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
  478 +#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
  479 +#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
  480 +#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
  481 +#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
  482 +#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
  483 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
  484 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
  485 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
  486 +#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
  487 +#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
  488 +#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
  489 +#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
  490 +#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
  491 +#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
  492 +#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
  493 +#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
  494 +#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
  495 +#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
  496 +#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
  497 +#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
  498 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
  499 +#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
  500 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
  501 +#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
  502 +#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
  503 +#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
  504 +#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
  505 +#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
  506 +#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
  507 +#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
  508 +#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
  509 +#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
  510 +#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
  511 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
  512 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
  513 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
  514 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
  515 +#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
  516 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
  517 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
  518 +#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
  519 +#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
  520 +#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
  521 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
  522 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
  523 +#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
  524 +#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
  525 +#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
  526 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
  527 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
  528 +#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
  529 +#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
  530 +#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
  531 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
  532 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
  533 +#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
  534 +#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
  535 +#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
  536 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
  537 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
  538 +#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
  539 +#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
  540 +#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
  541 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
  542 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
  543 +#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
  544 +#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
  545 +#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
  546 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
  547 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
  548 +#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
  549 +#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
  550 +#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
  551 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
  552 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
  553 +#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
  554 +#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
  555 +#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
  556 +#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
  557 +#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
  558 +#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
  559 +#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
  560 +#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
  561 +#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
  562 +#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
  563 +#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
  564 +#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
  565 +#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
  566 +#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
  567 +#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
  568 +#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
  569 +#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
  570 +#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
  571 +#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
  572 +#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
  573 +#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
  574 +#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
  575 +#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
  576 +#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
  577 +#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
  578 +#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
  579 +#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
  580 +#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
  581 +#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
  582 +#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
  583 +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0
  584 +#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
  585 +#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
  586 +#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
  587 +#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
  588 +#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
  589 +#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
  590 +#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
  591 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
  592 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
  593 +#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
  594 +#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
  595 +#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
  596 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
  597 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
  598 +#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
  599 +#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
  600 +#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
  601 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
  602 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
  603 +#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
  604 +#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
  605 +#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
  606 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
  607 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
  608 +#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
  609 +#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
  610 +#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
  611 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
  612 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
  613 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
  614 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
  615 +#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
  616 +#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
  617 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
  618 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
  619 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
  620 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
  621 +#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
  622 +#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
  623 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
  624 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
  625 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
  626 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
  627 +#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
  628 +#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
  629 +#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
  630 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
  631 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
  632 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
  633 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
  634 +#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
  635 +#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
  636 +#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
  637 +
  638 +#endif /* __DTS_IMX8MM_PINFUNC_H */