add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns

Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>

add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns
Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
Wolfgang Wegner · Wolfgang Denk
1 parent c87f6457bb
Showing 2 changed files with 7 additions and 0 deletions Side-by-side Diff
drivers/fpga/spartan3.c
include/spartan3.h
@@ -366,6 +366,8 @@
 			CONFIG_FPGA_DELAY ();
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to start.\n");
+				if (*fn->abort)
+					(*fn->abort) (cookie);
 				return FPGA_FAIL;
 			}
 		} while (!(*fn->init) (cookie));
@@ -380,6 +382,8 @@
 			CONFIG_FPGA_DELAY ();
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
+				if (*fn->abort)
+					(*fn->abort) (cookie);
 				return FPGA_FAIL;
 			}
 		} while ((*fn->init) (cookie));
@@ -394,6 +398,8 @@
 				   while DONE is low (inactive) */
 				if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
 					puts ("** CRC error during FPGA load.\n");
+					if (*fn->abort)
+						(*fn->abort) (cookie);
 					return (FPGA_FAIL);
 				}
 				val = data [bytecount ++];
@@ -58,6 +58,7 @@
 	Xilinx_wr_fn	wr;
 	Xilinx_post_fn	post;
 	Xilinx_bwr_fn	bwr; /* block write function */
+	Xilinx_abort_fn abort;
 } Xilinx_Spartan3_Slave_Serial_fns;
  
 /* Device Image Sizes
...	...	@@ -366,6 +366,8 @@
366	366	CONFIG_FPGA_DELAY ();
367	367	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
368	368	puts ("** Timeout waiting for INIT to start.\n");
	369	+ if (*fn->abort)
	370	+ (*fn->abort) (cookie);
369	371	return FPGA_FAIL;
370	372	}
371	373	} while (!(*fn->init) (cookie));
...	...	@@ -380,6 +382,8 @@
380	382	CONFIG_FPGA_DELAY ();
381	383	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
382	384	puts ("** Timeout waiting for INIT to clear.\n");
	385	+ if (*fn->abort)
	386	+ (*fn->abort) (cookie);
383	387	return FPGA_FAIL;
384	388	}
385	389	} while ((*fn->init) (cookie));
...	...	@@ -394,6 +398,8 @@
394	398	while DONE is low (inactive) */
395	399	if ((fn->done) (cookie) == 0 && (fn->init) (cookie)) {
396	400	puts ("** CRC error during FPGA load.\n");
	401	+ if (*fn->abort)
	402	+ (*fn->abort) (cookie);
397	403	return (FPGA_FAIL);
398	404	}
399	405	val = data [bytecount ++];
...	...	@@ -58,6 +58,7 @@
58	58	Xilinx_wr_fn wr;
59	59	Xilinx_post_fn post;
60	60	Xilinx_bwr_fn bwr; /* block write function */
	61	+ Xilinx_abort_fn abort;
61	62	} Xilinx_Spartan3_Slave_Serial_fns;
62	63
63	64	/* Device Image Sizes