Commit b0e49b4cd86b1b8617e2a671502f0fa25e848f04
Merge ../custodians
Showing 2 changed files Side-by-side Diff
drivers/serial/serial_sh.c
| 1 | 1 | /* |
| 2 | 2 | * SuperH SCIF device driver. |
| 3 | - * Copyright (c) 2007 Nobuhiro Iwamatsu | |
| 3 | + * Copyright (c) 2007,2008 Nobuhiro Iwamatsu | |
| 4 | 4 | * |
| 5 | 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | 6 | * it under the terms of the GNU General Public License as published by |
| ... | ... | @@ -36,7 +36,7 @@ |
| 36 | 36 | #define SCSCR (vu_short *)(SCIF_BASE + 0x8) |
| 37 | 37 | #define SCFCR (vu_short *)(SCIF_BASE + 0x18) |
| 38 | 38 | #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) |
| 39 | -#ifdef CONFIG_SH7720 /* SH7720 specific */ | |
| 39 | +#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ | |
| 40 | 40 | #define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ |
| 41 | 41 | #define SCFTDR (vu_char *)(SCIF_BASE + 0x20) |
| 42 | 42 | #define SCFRDR (vu_char *)(SCIF_BASE + 0x24) |
| 43 | 43 | |
| 44 | 44 | |
| 45 | 45 | |
| ... | ... | @@ -57,14 +57,21 @@ |
| 57 | 57 | #define SCLSR (vu_short *)(SCIF_BASE + 0x24) |
| 58 | 58 | #define LSR_ORER 1 |
| 59 | 59 | #elif defined (CONFIG_SH3) |
| 60 | -#ifdef CONFIG_SH7720 /* SH7720 specific */ | |
| 61 | -# define SCLSR SCFSR /* SCSSR */ | |
| 60 | +#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ | |
| 61 | +#define SCLSR (vu_short *)(SCIF_BASE + 0x24) | |
| 62 | +#define LSR_ORER 0x0200 | |
| 62 | 63 | #else |
| 63 | -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) | |
| 64 | +#define SCLSR SCFSR /* SCSSR */ | |
| 65 | +#define LSR_ORER 1 | |
| 64 | 66 | #endif |
| 65 | -#define LSR_ORER 0x0200 | |
| 66 | 67 | #endif |
| 67 | 68 | |
| 69 | +#if defined(CONFIG_CPU_SH7720) | |
| 70 | +#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | |
| 71 | +#else /* Generic SuperH */ | |
| 72 | +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
| 73 | +#endif | |
| 74 | + | |
| 68 | 75 | #define SCR_RE (1 << 4) |
| 69 | 76 | #define SCR_TE (1 << 5) |
| 70 | 77 | #define FCR_RFRST (1 << 1) /* RFCL */ |
| ... | ... | @@ -82,18 +89,7 @@ |
| 82 | 89 | void serial_setbrg (void) |
| 83 | 90 | { |
| 84 | 91 | DECLARE_GLOBAL_DATA_PTR; |
| 85 | - | |
| 86 | -#if defined(CONFIG_CPU_SH7720) | |
| 87 | - int divisor = gd->baudrate * 16; | |
| 88 | - | |
| 89 | - *SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) / | |
| 90 | - (gd->baudrate * 32) - 1; | |
| 91 | -#else | |
| 92 | - int divisor = gd->baudrate * 32; | |
| 93 | - | |
| 94 | - *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / | |
| 95 | - (gd->baudrate * 32) - 1; | |
| 96 | -#endif | |
| 92 | + *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); | |
| 97 | 93 | } |
| 98 | 94 | |
| 99 | 95 | int serial_init (void) |
include/configs/ms7720se.h
| ... | ... | @@ -40,13 +40,6 @@ |
| 40 | 40 | #define CONFIG_CMD_IDE |
| 41 | 41 | #define CONFIG_CMD_EXT2 |
| 42 | 42 | |
| 43 | -#define CFG_CMD_PCMCIA 0x01 | |
| 44 | -#define CFG_CMD_IDE 0x02 | |
| 45 | - | |
| 46 | -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ | |
| 47 | - CFG_CMD_IDE|CFG_CMD_PCMCIA) & \ | |
| 48 | - ~(CFG_CMD_FPGA)) | |
| 49 | - | |
| 50 | 43 | #define CONFIG_BAUDRATE 115200 |
| 51 | 44 | #define CONFIG_BOOTARGS "console=ttySC0,115200" |
| 52 | 45 | #define CONFIG_BOOTFILE /boot/zImage |