powerpc/mpc85xx: Add support for single source clocking

Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>

powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Priyanka Jain · York Sun
1 parent 562de1d6da
Showing 4 changed files with 32 additions and 2 deletions Side-by-side Diff
README
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
@@ -423,6 +423,11 @@
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
  
+		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+		Single Source Clock is clocking mode present in some of FSL SoC's.
+		In this mode, a single differential clock is used to supply
+		clocks to the sysclock, ddrclock and usbclock.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
  
@@ -74,12 +74,33 @@
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	uint single_src;
+#endif
  
 	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	/*
+	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+	 * are driven by separate DDR Refclock or single source
+	 * differential clock.
+	 */
+	single_src = (in_be32(&gur->rcwsr[5]) >>
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+	/*
+	 * For single source clocking, both ddrclock and syclock
+	 * are driven by differential sysclock.
+	 */
+	if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+		printf("Single Source Clock Configuration\n");
+		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+	} else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-	sys_info->freq_ddrbus = sysclk;
+		sys_info->freq_ddrbus = sysclk;
 #endif
  
 	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
@@ -711,6 +711,7 @@
 #define CONFIG_FM_PLAT_CLK_DIV	1
 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
@@ -1774,6 +1774,9 @@
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
  
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
...	...	@@ -423,6 +423,11 @@
423	423	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
424	424	This value denotes start offset of DSP CCSR space.
425	425
	426	+ CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
	427	+ Single Source Clock is clocking mode present in some of FSL SoC's.
	428	+ In this mode, a single differential clock is used to supply
	429	+ clocks to the sysclock, ddrclock and usbclock.
	430	+
426	431	- Generic CPU options:
427	432	CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
428	433
...	...	@@ -74,12 +74,33 @@
74	74	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75	75	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76	76	uint mem_pll_rat;
	77	+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
	78	+ uint single_src;
	79	+#endif
77	80
78	81	sys_info->freq_systembus = sysclk;
	82	+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
	83	+ /*
	84	+ * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
	85	+ * are driven by separate DDR Refclock or single source
	86	+ * differential clock.
	87	+ */
	88	+ single_src = (in_be32(&gur->rcwsr[5]) >>
	89	+ FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
	90	+ FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
	91	+ /*
	92	+ * For single source clocking, both ddrclock and syclock
	93	+ * are driven by differential sysclock.
	94	+ */
	95	+ if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
	96	+ printf("Single Source Clock Configuration\n");
	97	+ sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
	98	+ } else
	99	+#endif
79	100	#ifdef CONFIG_DDR_CLK_FREQ
80		- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
	101	+ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
81	102	#else
82		- sys_info->freq_ddrbus = sysclk;
	103	+ sys_info->freq_ddrbus = sysclk;
83	104	#endif
84	105
85	106	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
...	...	@@ -711,6 +711,7 @@
711	711	#define CONFIG_FM_PLAT_CLK_DIV 1
712	712	#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
713	713	#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
	714	+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
714	715	#define CONFIG_SYS_FSL_TBCLK_DIV 16
715	716	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
716	717	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
...	...	@@ -1774,6 +1774,9 @@
1774	1774	#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1775	1775	#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1776	1776	#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
	1777	+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
	1778	+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
	1779	+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1777	1780
1778	1781	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1779	1782	#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17