board/t208xqds: Add support of 2-stage NAND/SPI/SD boot

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH] Reviewed-by: York Sun <yorksun@freescale.com>

board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH] Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu · York Sun
1 parent d1c561cd54
Showing 6 changed files with 253 additions and 28 deletions Side-by-side Diff
board/freescale/t208xqds/Makefile
board/freescale/t208xqds/ddr.c
board/freescale/t208xqds/spl.c
board/freescale/t208xqds/tlb.c
boards.cfg
include/configs/T208xQDS.h
@@ -4,11 +4,16 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
  
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T2080QDS) += t208xqds.o
 obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
 obj-$(CONFIG_T2081QDS) += t208xqds.o
 obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
+endif
+
 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o
@@ -107,14 +107,17 @@
 {
 	phys_size_t dram_size;
  
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
  
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
  
-	puts("    DDR: ");
 	return dram_size;
 }
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	puts("\nNAND boot...\n");
+#endif
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
@@ -65,6 +65,7 @@
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
  
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -110,6 +111,7 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -141,6 +143,11 @@
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
  
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
 };
  
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
@@ -955,14 +955,14 @@
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1042RDB_PI_SPIFLASH                 T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                     Priyanka Jain  <Priyanka.Jain@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS                             T208xQDS:PPC_T2080                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SECURE_BOOT                 T208xQDS:PPC_T2080,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND                        T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD                      T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH                    T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND                        T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD                      T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH                    T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS                             T208xQDS:PPC_T2081                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND                        T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD                      T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND                        T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD                      T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD                                                                                             -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
@@ -46,16 +46,80 @@
 #define CONFIG_ENV_OVERWRITE
  
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
 #if defined(CONFIG_PPC_T2080)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
 #elif defined(CONFIG_PPC_T2081)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
 #endif
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
 #endif
  
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
@@ -85,11 +149,7 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
  
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
+#ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  
@@ -110,12 +170,12 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_OFFSET	(512 * 1658)
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -140,7 +200,16 @@
 /*
  * Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
  
 #define CONFIG_SYS_DCSRBAR	0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
@@ -345,7 +414,12 @@
 #define CONFIG_SYS_RAMBOOT
 #endif
  
-#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
  
  
@@ -461,15 +535,14 @@
  */
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_STMICRO
-#if defined(CONFIG_T2080QDS)
-#define CONFIG_SPI_FLASH_SPANSION
-#elif defined(CONFIG_T2081QDS)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_EON
 #endif
  
 #define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
 #endif
  
  
@@ -564,14 +637,14 @@
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
...	...	@@ -4,11 +4,16 @@
4	4	# SPDX-License-Identifier: GPL-2.0+
5	5	#
6	6
	7	+ifdef CONFIG_SPL_BUILD
	8	+obj-y += spl.o
	9	+else
7	10	obj-$(CONFIG_T2080QDS) += t208xqds.o
8	11	obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
9	12	obj-$(CONFIG_T2081QDS) += t208xqds.o
10	13	obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
11	14	obj-$(CONFIG_PCI) += pci.o
	15	+endif
	16	+
12	17	obj-y += ddr.o
13	18	obj-y += law.o
14	19	obj-y += tlb.o
...	...	@@ -107,14 +107,17 @@
107	107	{
108	108	phys_size_t dram_size;
109	109
	110	+#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
110	111	puts("Initializing....using SPD\n");
111		-
112	112	dram_size = fsl_ddr_sdram();
113	113
114	114	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
115	115	dram_size *= 0x100000;
	116	+#else
	117	+ /* DDR has been initialised by first stage boot loader */
	118	+ dram_size = fsl_ddr_sdram_size();
	119	+#endif
116	120
117		- puts(" DDR: ");
118	121	return dram_size;
119	122	}
	1	+/* Copyright 2013 Freescale Semiconductor, Inc.
	2	+ *
	3	+ * SPDX-License-Identifier: GPL-2.0+
	4	+ */
	5	+
	6	+#include <common.h>
	7	+#include <malloc.h>
	8	+#include <ns16550.h>
	9	+#include <nand.h>
	10	+#include <i2c.h>
	11	+#include <mmc.h>
	12	+#include <fsl_esdhc.h>
	13	+#include <spi_flash.h>
	14	+#include "../common/qixis.h"
	15	+#include "t208xqds_qixis.h"
	16	+
	17	+DECLARE_GLOBAL_DATA_PTR;
	18	+
	19	+phys_size_t get_effective_memsize(void)
	20	+{
	21	+ return CONFIG_SYS_L3_SIZE;
	22	+}
	23	+
	24	+unsigned long get_board_sys_clk(void)
	25	+{
	26	+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	27	+
	28	+ switch (sysclk_conf & 0x0F) {
	29	+ case QIXIS_SYSCLK_83:
	30	+ return 83333333;
	31	+ case QIXIS_SYSCLK_100:
	32	+ return 100000000;
	33	+ case QIXIS_SYSCLK_125:
	34	+ return 125000000;
	35	+ case QIXIS_SYSCLK_133:
	36	+ return 133333333;
	37	+ case QIXIS_SYSCLK_150:
	38	+ return 150000000;
	39	+ case QIXIS_SYSCLK_160:
	40	+ return 160000000;
	41	+ case QIXIS_SYSCLK_166:
	42	+ return 166666666;
	43	+ }
	44	+ return 66666666;
	45	+}
	46	+
	47	+unsigned long get_board_ddr_clk(void)
	48	+{
	49	+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	50	+
	51	+ switch ((ddrclk_conf & 0x30) >> 4) {
	52	+ case QIXIS_DDRCLK_100:
	53	+ return 100000000;
	54	+ case QIXIS_DDRCLK_125:
	55	+ return 125000000;
	56	+ case QIXIS_DDRCLK_133:
	57	+ return 133333333;
	58	+ }
	59	+ return 66666666;
	60	+}
	61	+
	62	+void board_init_f(ulong bootflag)
	63	+{
	64	+ u32 plat_ratio, sys_clk, ccb_clk;
	65	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	66	+
	67	+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
	68	+ memcpy((void )CONFIG_SPL_GD_ADDR, (void )gd, sizeof(gd_t));
	69	+
	70	+ /* Update GD pointer */
	71	+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
	72	+
	73	+ console_init_f();
	74	+
	75	+ /* initialize selected port with appropriate baud rate */
	76	+ sys_clk = get_board_sys_clk();
	77	+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	78	+ ccb_clk = sys_clk * plat_ratio / 2;
	79	+
	80	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	81	+ ccb_clk / 16 / CONFIG_BAUDRATE);
	82	+
	83	+#if defined(CONFIG_SPL_MMC_BOOT)
	84	+ puts("\nSD boot...\n");
	85	+#elif defined(CONFIG_SPL_SPI_BOOT)
	86	+ puts("\nSPI boot...\n");
	87	+#elif defined(CONFIG_SPL_NAND_BOOT)
	88	+ puts("\nNAND boot...\n");
	89	+#endif
	90	+
	91	+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
	92	+}
	93	+
	94	+void board_init_r(gd_t *gd, ulong dest_addr)
	95	+{
	96	+ bd_t *bd;
	97	+
	98	+ bd = (bd_t *)(gd + sizeof(gd_t));
	99	+ memset(bd, 0, sizeof(bd_t));
	100	+ gd->bd = bd;
	101	+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
	102	+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
	103	+
	104	+ probecpu();
	105	+ get_clocks();
	106	+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	107	+ CONFIG_SPL_RELOC_MALLOC_SIZE);
	108	+
	109	+#ifdef CONFIG_SPL_NAND_BOOT
	110	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	111	+ (uchar *)CONFIG_ENV_ADDR);
	112	+#endif
	113	+#ifdef CONFIG_SPL_MMC_BOOT
	114	+ mmc_initialize(bd);
	115	+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	116	+ (uchar *)CONFIG_ENV_ADDR);
	117	+#endif
	118	+#ifdef CONFIG_SPL_SPI_BOOT
	119	+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	120	+ (uchar *)CONFIG_ENV_ADDR);
	121	+#endif
	122	+
	123	+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	124	+ gd->env_valid = 1;
	125	+
	126	+ i2c_init_all();
	127	+
	128	+ gd->ram_size = initdram(0);
	129	+
	130	+#ifdef CONFIG_SPL_MMC_BOOT
	131	+ mmc_boot();
	132	+#elif defined(CONFIG_SPL_SPI_BOOT)
	133	+ spi_boot();
	134	+#elif defined(CONFIG_SPL_NAND_BOOT)
	135	+ nand_boot();
	136	+#endif
	137	+}
...	...	@@ -65,6 +65,7 @@
65	65	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
66	66	0, 2, BOOKE_PAGESZ_256M, 1),
67	67
	68	+#ifndef CONFIG_SPL_BUILD
68	69	/* IG* - PCIe 1, 0x80000000 */
69	70	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70	71	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -110,6 +111,7 @@
110	111	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
111	112	0, 12, BOOKE_PAGESZ_16M, 1),
112	113	#endif
	114	+#endif
113	115	#ifdef CONFIG_SYS_DCSRBAR_PHYS
114	116	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
115	117	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -141,6 +143,11 @@
141	143	0, 18, BOOKE_PAGESZ_1M, 1),
142	144	#endif
143	145
	146	+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
	147	+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
	148	+ MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	149	+ 0, 19, BOOKE_PAGESZ_2G, 1)
	150	+#endif
144	151	};
145	152
146	153	int num_tlb_entries = ARRAY_SIZE(tlb_table);
...	...	@@ -955,14 +955,14 @@
955	955	Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
956	956	Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
957	957	Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
958		-Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
959		-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
960		-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
	958	+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
	959	+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
	960	+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
961	961	Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
962	962	Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
963		-Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
964		-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
965		-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
	963	+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
	964	+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
	965	+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
966	966	Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
967	967	Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
968	968	Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
...	...	@@ -46,16 +46,80 @@
46	46	#define CONFIG_ENV_OVERWRITE
47	47
48	48	#ifdef CONFIG_RAMBOOT_PBL
49		-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
50		-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
51	49	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
52	50	#if defined(CONFIG_PPC_T2080)
53	51	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
54	52	#elif defined(CONFIG_PPC_T2081)
55	53	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
56	54	#endif
	55	+
	56	+#define CONFIG_SPL
	57	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	58	+#define CONFIG_SPL_ENV_SUPPORT
	59	+#define CONFIG_SPL_SERIAL_SUPPORT
	60	+#define CONFIG_SPL_FLUSH_IMAGE
	61	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	62	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	63	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	64	+#define CONFIG_SPL_I2C_SUPPORT
	65	+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	66	+#define CONFIG_FSL_LAW /* Use common FSL init code */
	67	+#define CONFIG_SYS_TEXT_BASE 0x00201000
	68	+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
	69	+#define CONFIG_SPL_PAD_TO 0x40000
	70	+#define CONFIG_SPL_MAX_SIZE 0x28000
	71	+#define RESET_VECTOR_OFFSET 0x27FFC
	72	+#define BOOT_PAGE_OFFSET 0x27000
	73	+#ifdef CONFIG_SPL_BUILD
	74	+#define CONFIG_SPL_SKIP_RELOCATE
	75	+#define CONFIG_SPL_COMMON_INIT_DDR
	76	+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
	77	+#define CONFIG_SYS_NO_FLASH
57	78	#endif
58	79
	80	+#ifdef CONFIG_NAND
	81	+#define CONFIG_SPL_NAND_SUPPORT
	82	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	83	+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
	84	+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
	85	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
	86	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	87	+#define CONFIG_SPL_NAND_BOOT
	88	+#endif
	89	+
	90	+#ifdef CONFIG_SPIFLASH
	91	+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
	92	+#define CONFIG_SPL_SPI_SUPPORT
	93	+#define CONFIG_SPL_SPI_FLASH_SUPPORT
	94	+#define CONFIG_SPL_SPI_FLASH_MINIMAL
	95	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	96	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
	97	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
	98	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
	99	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	100	+#ifndef CONFIG_SPL_BUILD
	101	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	102	+#endif
	103	+#define CONFIG_SPL_SPI_BOOT
	104	+#endif
	105	+
	106	+#ifdef CONFIG_SDCARD
	107	+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
	108	+#define CONFIG_SPL_MMC_SUPPORT
	109	+#define CONFIG_SPL_MMC_MINIMAL
	110	+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	111	+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
	112	+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
	113	+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
	114	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	115	+#ifndef CONFIG_SPL_BUILD
	116	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	117	+#endif
	118	+#define CONFIG_SPL_MMC_BOOT
	119	+#endif
	120	+
	121	+#endif /* CONFIG_RAMBOOT_PBL */
	122	+
59	123	#define CONFIG_SRIO_PCIE_BOOT_MASTER
60	124	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
61	125	/* Set 1M boot space */
...	...	@@ -85,11 +149,7 @@
85	149	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
86	150	#endif
87	151
88		-#ifdef CONFIG_SYS_NO_FLASH
89		-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
90		-#define CONFIG_ENV_IS_NOWHERE
91		-#endif
92		-#else
	152	+#ifndef CONFIG_SYS_NO_FLASH
93	153	#define CONFIG_FLASH_CFI_DRIVER
94	154	#define CONFIG_SYS_FLASH_CFI
95	155	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96	156
...	...	@@ -110,12 +170,12 @@
110	170	#define CONFIG_ENV_IS_IN_MMC
111	171	#define CONFIG_SYS_MMC_ENV_DEV 0
112	172	#define CONFIG_ENV_SIZE 0x2000
113		-#define CONFIG_ENV_OFFSET (512 * 1658)
	173	+#define CONFIG_ENV_OFFSET (512 * 0x800)
114	174	#elif defined(CONFIG_NAND)
115	175	#define CONFIG_SYS_EXTRA_ENV_RELOC
116	176	#define CONFIG_ENV_IS_IN_NAND
117		-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
118		-#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
	177	+#define CONFIG_ENV_SIZE 0x2000
	178	+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
119	179	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
120	180	#define CONFIG_ENV_IS_IN_REMOTE
121	181	#define CONFIG_ENV_ADDR 0xffe20000
...	...	@@ -140,7 +200,16 @@
140	200	/*
141	201	* Config the L3 Cache as L3 SRAM
142	202	*/
143		-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
	203	+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	204	+#define CONFIG_SYS_L3_SIZE (512 << 10)
	205	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
	206	+#ifdef CONFIG_RAMBOOT_PBL
	207	+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
	208	+#endif
	209	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	210	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
	211	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
	212	+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
144	213
145	214	#define CONFIG_SYS_DCSRBAR 0xf0000000
146	215	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
...	...	@@ -345,7 +414,12 @@
345	414	#define CONFIG_SYS_RAMBOOT
346	415	#endif
347	416
348		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	417	+#ifdef CONFIG_SPL_BUILD
	418	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	419	+#else
	420	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	421	+#endif
	422	+
349	423	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
350	424	#define CONFIG_MISC_INIT_R
351	425	#define CONFIG_HWCONFIG
352	426
353	427
...	...	@@ -461,15 +535,14 @@
461	535	*/
462	536	#ifdef CONFIG_SPI_FLASH
463	537	#define CONFIG_FSL_ESPI
464		-#define CONFIG_SPI_FLASH_SST
465	538	#define CONFIG_SPI_FLASH_STMICRO
466		-#if defined(CONFIG_T2080QDS)
467		-#define CONFIG_SPI_FLASH_SPANSION
468		-#elif defined(CONFIG_T2081QDS)
	539	+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
	540	+#define CONFIG_SPI_FLASH_SST
469	541	#define CONFIG_SPI_FLASH_EON
470	542	#endif
471	543
472	544	#define CONFIG_CMD_SF
	545	+#define CONFIG_SPI_FLASH_BAR
473	546	#define CONFIG_SF_DEFAULT_SPEED 10000000
474	547	#define CONFIG_SF_DEFAULT_MODE 0
475	548	#endif
476	549
477	550
...	...	@@ -564,14 +637,14 @@
564	637	#elif defined(CONFIG_SDCARD)
565	638	/*
566	639	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
567		- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
568		- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
	640	+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
	641	+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
569	642	*/
570	643	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
571		-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
	644	+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
572	645	#elif defined(CONFIG_NAND)
573	646	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
574		-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
	647	+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
575	648	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
576	649	/*
577	650	* Slave has no ucode locally, it can fetch this from remote. When implementing