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Commit b1a2bd4bb3c23e48d60c4352b1c62037fd11435f

Authored by Wolfgang Denk
Committed by Albert ARIBAUD
1 parent 5bd3814bb7
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: remove broken "m501sk" board 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 8 changed files with 1 additions and 752 deletions Side-by-side Diff

board/m501sk/Makefile
View file @ b1a2bd4
1   -#
2   -# (C) Copyright 2003
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS := m501sk.o eeprom.o
29   -
30   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31   -OBJS := $(addprefix $(obj),$(COBJS))
32   -SOBJS := $(addprefix $(obj),$(SOBJS))
33   -
34   -$(LIB): $(OBJS) $(SOBJS)
35   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
36   -
37   -clean:
38   - rm -f $(SOBJS) $(OBJS)
39   -
40   -distclean: clean
41   - rm -f $(LIB) core *.bak $(obj).depend
42   -
43   -#########################################################################
44   -
45   -# defines $(obj).depend target
46   -include $(SRCTREE)/rules.mk
47   -
48   -sinclude $(obj).depend
49   -
50   -#########################################################################
board/m501sk/config.mk
View file @ b1a2bd4
1   -CONFIG_SYS_TEXT_BASE = 0x21f00000
board/m501sk/eeprom.c
View file @ b1a2bd4
1   -/*
2   - * Add by Alan Lu, 07-29-2005
3   - * For ATMEL AT24C16 EEPROM
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <i2c.h>
26   -#ifdef CONFIG_SYS_EEPROM_AT24C16
27   -#undef DEBUG
28   -
29   -void eeprom_init(void)
30   -{
31   -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
32   - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
33   -#endif
34   -}
35   -
36   -int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
37   - unsigned cnt)
38   -{
39   - int page, count = 0, i = 0;
40   - page = offset / 0x100;
41   - i = offset % 0x100;
42   -
43   - while (count < cnt) {
44   - if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
45   - return 1;
46   - if (i > 0xff) {
47   - page++;
48   - i = 0;
49   - }
50   - }
51   -
52   - return 0;
53   -}
54   -
55   -/*
56   - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
57   - * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
58   - *
59   - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
60   - * 0x00000nxx for EEPROM address selectors and page number at n.
61   - */
62   -int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
63   - unsigned cnt)
64   -{
65   - int page, i = 0, count = 0;
66   -
67   - page = offset / 0x100;
68   - i = offset % 0x100;
69   -
70   - while (count < cnt) {
71   - if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
72   - return 1;
73   - if (i > 0xff) {
74   - page++;
75   - i = 0;
76   - }
77   - }
78   -
79   -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
80   - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
81   -#endif
82   -
83   - return 0;
84   -}
85   -
86   -#ifndef CONFIG_SPI
87   -int eeprom_probe(unsigned dev_addr, unsigned offset)
88   -{
89   - unsigned char chip;
90   -
91   - /* Probe the chip address */
92   -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
93   - chip = offset >> 8; /* block number */
94   -#else
95   - chip = offset >> 16; /* block number */
96   -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
97   -
98   - chip |= dev_addr; /* insert device address */
99   - return (i2c_probe(chip));
100   -}
101   -#endif
102   -#endif
board/m501sk/m501sk.c
View file @ b1a2bd4
1   -/*
2   - * (C) Copyright 2008
3   - * Based on modifications by Alan Lu / Artila
4   - * Author : Timo Tuunainen / Sysart
5   - Kimmo Leppala / Sysart
6   - *
7   - * See file CREDITS for list of people who contributed to this
8   - * project.
9   - *
10   - * This program is free software; you can redistribute it and/or
11   - * modify it under the terms of the GNU General Public License as
12   - * published by the Free Software Foundation; either version 2 of
13   - * the License, or (at your option) any later version.
14   - *
15   - * This program is distributed in the hope that it will be useful,
16   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * You should have received a copy of the GNU General Public License
21   - * along with this program; if not, write to the Free Software
22   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   - * MA 02111-1307 USA
24   - */
25   -
26   -#include <common.h>
27   -#include <asm/io.h>
28   -#include <netdev.h>
29   -#if defined(CONFIG_DRIVER_ETHER)
30   -#include <at91rm9200_net.h>
31   -#include <dm9161.h>
32   -#endif
33   -
34   -#include "m501sk.h"
35   -#include "net.h"
36   -
37   -#ifdef CONFIG_M501SK
38   -
39   -void m501sk_gpio_init(void)
40   -{
41   - AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
42   - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
43   - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
44   -
45   - AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
46   - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
47   - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
48   -
49   - AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
50   - AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
51   - AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
52   - AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
53   - AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
54   -
55   - /* Power OFF all USART's LEDs */
56   - AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
57   - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
58   - AT91C_PA23_TXD2;
59   -
60   - AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
61   - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
62   - AT91C_PA23_TXD2;
63   -
64   - AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
65   - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
66   - AT91C_PA23_TXD2;
67   -
68   - AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
69   - AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
70   - AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
71   -}
72   -
73   -uchar m501sk_gpio_set(M501SK_PIO io)
74   -{
75   - uchar status = 0xff;
76   - switch (io) {
77   - case M501SK_DEBUG_LED1:
78   - case M501SK_DEBUG_LED2:
79   - case M501SK_DEBUG_LED3:
80   - case M501SK_DEBUG_LED4:
81   - case M501SK_READY_LED:
82   - AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
83   - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
84   - break;
85   - case M501SK_BUZZER:
86   - AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
87   - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
88   - break;
89   - }
90   - return status;
91   -}
92   -
93   -uchar m501sk_gpio_clear(M501SK_PIO io)
94   -{
95   - uchar status = 0xff;
96   - switch (io) {
97   - case M501SK_DEBUG_LED1:
98   - case M501SK_DEBUG_LED2:
99   - case M501SK_DEBUG_LED3:
100   - case M501SK_DEBUG_LED4:
101   - case M501SK_READY_LED:
102   - AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
103   - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
104   - break;
105   - case M501SK_BUZZER:
106   - AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
107   - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
108   - break;
109   - }
110   - return status;
111   -}
112   -
113   -/*
114   - * Miscelaneous platform dependent initialisations
115   - */
116   -DECLARE_GLOBAL_DATA_PTR;
117   -
118   -int board_init(void)
119   -{
120   - /* Enable Ctrlc */
121   - console_init_f();
122   -
123   - /* Correct IRDA resistor problem */
124   - /* Set PA23_TXD in Output */
125   - ((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
126   -
127   - /* memory and cpu-speed are setup before relocation */
128   - /* so we do _nothing_ here */
129   - gd->bd->bi_arch_number = MACH_TYPE_M501;
130   - /* adress of boot parameters */
131   - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
132   - m501sk_gpio_init();
133   -
134   - /* Do interrupt init here, because flash needs timers */
135   - timer_init();
136   - flash_init();
137   -
138   - return 0;
139   -}
140   -
141   -int dram_init(void)
142   -{
143   - int i = 0;
144   - gd->bd->bi_dram[0].start = PHYS_SDRAM;
145   - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
146   -
147   - for (i = 0; i < 500; i++) {
148   - m501sk_gpio_clear(M501SK_DEBUG_LED3);
149   - m501sk_gpio_clear(M501SK_BUZZER);
150   - udelay(250);
151   - m501sk_gpio_set(M501SK_DEBUG_LED3);
152   - m501sk_gpio_set(M501SK_BUZZER);
153   - udelay(80);
154   - }
155   - m501sk_gpio_clear(M501SK_BUZZER);
156   - m501sk_gpio_clear(M501SK_DEBUG_LED3);
157   -
158   - return 0;
159   -}
160   -
161   -int board_late_init(void)
162   -{
163   -#if defined(CONFIG_CMD_NET)
164   - eth_init(gd->bd);
165   - eth_halt();
166   -#endif
167   -
168   - /* Protect U-Boot, kernel & ramdisk memory addresses */
169   - run_command("protect on 10000000 1041ffff", 0);
170   - return 0;
171   -}
172   -
173   -#ifdef CONFIG_DRIVER_ETHER
174   -#if defined(CONFIG_CMD_NET)
175   -/*
176   - * Name:
177   - * at91rm9200_GetPhyInterface
178   - * Description:
179   - * Initialise the interface functions to the PHY
180   - * Arguments:
181   - * None
182   - * Return value:
183   - * None
184   - */
185   -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
186   -{
187   - p_phyops->Init = dm9161_InitPhy;
188   - p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
189   - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
190   - p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
191   -}
192   -#endif /* CONFIG_CMD_NET */
193   -#endif /* CONFIG_DRIVER_ETHER */
194   -
195   -#ifdef CONFIG_DRIVER_AT91EMAC
196   -int board_eth_init(bd_t *bis)
197   -{
198   - int rc = 0;
199   - rc = at91emac_register(bis, 0);
200   - return rc;
201   -}
202   -#endif
203   -#endif /* CONFIG_M501SK */
board/m501sk/m501sk.h
View file @ b1a2bd4
1   -/*
2   - * linux/include/asm/arch-at91/hardware.h
3   - *
4   - * Copyright (C) 2003 SAN People
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License as published by
8   - * the Free Software Foundation; either version 2 of the License, or
9   - * (at your option) any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -#ifndef __M501SK_H
21   -#define __M501SK_H
22   -
23   -#ifndef __ASSEMBLY__
24   -#include <asm/arch-at91rm9200/AT91RM9200.h>
25   -#else
26   -#include <asm/arch-at91rm9200/AT91RM9200_inc.h>
27   -#endif
28   -
29   -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
30   -#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */
31   -#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 TxD */
32   -#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */
33   -
34   -/* ========== Register definition for PIOD peripheral ========== */
35   -#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */
36   -#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */
37   -#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */
38   -#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */
39   -#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */
40   -#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */
41   -#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */
42   -#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */
43   -#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */
44   -#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */
45   -#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */
46   -#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */
47   -#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */
48   -#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */
49   -#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */
50   -#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */
51   -#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */
52   -#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */
53   -#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */
54   -#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */
55   -#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */
56   -#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */
57   -#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */
58   -#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */
59   -#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */
60   -#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */
61   -#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */
62   -#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */
63   -#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */
64   -
65   -#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */
66   -#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Enet MAC Tx Data 0*/
67   -#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */
68   -#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Enet MAC Tx Data 1*/
69   -#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
70   -#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/
71   -#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */
72   -#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
73   -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */
74   -#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */
75   -#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
76   -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */
77   -#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */
78   -#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
79   -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */
80   -#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */
81   -#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
82   -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */
83   -#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */
84   -#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
85   -#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */
86   -#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */
87   -#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
88   -#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */
89   -#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */
90   -#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
91   -#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */
92   -#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */
93   -#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
94   -#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Perip CS 1 */
95   -#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */
96   -#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
97   -#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Perip CS 2 */
98   -#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */
99   -#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */
100   -#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC TxD 2 */
101   -#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
102   -#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */
103   -#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */
104   -#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
105   -#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */
106   -#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */
107   -#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
108   -#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 RTS */
109   -#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */
110   -#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
111   -#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */
112   -#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */
113   -#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
114   -#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 RTS */
115   -#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */
116   -#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
117   -#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */
118   -#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */
119   -#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
120   -#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */
121   -#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
122   -#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */
123   -#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */
124   -#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Enet MAC TxD 3 */
125   -#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */
126   -#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */
127   -#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */
128   -#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Enet MAC TxCE */
129   -#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */
130   -#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */
131   -#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */
132   -#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/
133   -#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */
134   -#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */
135   -#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/
136   -#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */
137   -#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */
138   -#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */
139   -#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */
140   -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
141   -#define AT91C_PIO_PC5 ((unsigned int) 1 << 5)
142   -#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */
143   -#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */
144   -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */
145   -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */
146   -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8)
147   -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9)
148   -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10)
149   -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11)
150   -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17)
151   -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28)
152   -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29)
153   -
154   -typedef enum {
155   - M501SK_BUZZER = 38,
156   - M501SK_DEBUG_LED1 = 96,
157   - M501SK_DEBUG_LED2,
158   - M501SK_DEBUG_LED3,
159   - M501SK_DEBUG_LED4,
160   - M501SK_READY_LED = 102,
161   -} M501SK_PIO;
162   -
163   -void m501sk_gpio_init(void);
164   -uchar m501sk_gpio_set(M501SK_PIO io);
165   -uchar m501sk_gpio_clear(M501SK_PIO io);
166   -
167   -#endif
... ... @@ -57,7 +57,6 @@
57 57 eb_cpux9k2 arm arm920t - BuS at91
58 58 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
59 59 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
60   -m501sk arm arm920t - - at91rm9200
61 60 at91rm9200dk arm arm920t - atmel at91rm9200
62 61 mx1ads arm arm920t - - imx
63 62 scb9328 arm arm920t - - imx
doc/README.scrapyard
Diff comments   View file @ b1a2bd4
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +m501sk arm arm920t - 2011-07-17
14 15 kb9202 arm arm920t - 2011-07-17
15 16 csb637 arm arm920t - 2011-07-17
16 17 cmc_pu2 arm arm920t - 2011-07-17
include/configs/m501sk.h
View file @ b1a2bd4
1   -/*
2   - * Based on Modifications by Alan Lu / Artila and
3   - * Rick Bronson <rick@efn.org>
4   - *
5   - * Configuration settings for the Artila M-501 starter kit,
6   - * with V02 processor card.
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -#ifndef __CONFIG_H
28   -#define __CONFIG_H
29   -
30   -#define CONFIG_AT91_LEGACY
31   -
32   -/* ARM asynchronous clock */
33   -/* from 18.432 MHz crystal (18432000 / 4 * 39) */
34   -#define AT91C_MAIN_CLOCK 179712000
35   -/* Perip clock (AT91C_MASTER_CLOCK / 3) */
36   -#define AT91C_MASTER_CLOCK 59904000
37   -#define AT91_SLOW_CLOCK 32768 /* slow clock */
38   -
39   -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
40   -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
41   -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43   -#define CONFIG_SETUP_MEMORY_TAGS 1
44   -#define CONFIG_INITRD_TAG 1
45   -
46   -#define CONFIG_MENUPROMPT "."
47   -/*
48   - * LowLevel Init
49   - */
50   -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
51   -/* flash */
52   -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
53   -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
54   -
55   -/* clocks */
56   -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
57   -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
58   -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
59   -#define CONFIG_SYS_MCKR_VAL 0x00000202
60   -
61   -/* sdram */
62   -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63   -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64   -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65   -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66   -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
67   -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68   -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69   -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70   -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71   -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72   -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73   -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74   -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75   -
76   -/*
77   - * Size of malloc() pool
78   - */
79   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
80   -
81   -#define CONFIG_BAUDRATE 115200
82   -
83   -/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
84   -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
85   -
86   -/*
87   - * Hardware drivers
88   - */
89   -#define CONFIG_SYS_FLASH_CFI 1
90   -#define CONFIG_FLASH_CFI_DRIVER 1
91   -#define CONFIG_ENV_SECT_SIZE 0x20000
92   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
93   -#define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/
94   -#define CONFIG_HARD_I2C
95   -#define CONFIG_SYS_I2C_SPEED 100
96   -#define CONFIG_SYS_I2C_SLAVE 0
97   -#define CONFIG_SYS_CONSOLE_INFO_QUIET
98   -#undef CONFIG_ENV_IS_IN_EEPROM
99   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
101   -#define CONFIG_SYS_EEPROM_AT24C16
102   -#define CONFIG_SYS_I2C_RTC_ADDR 0x32
103   -#undef CONFIG_RTC_DS1338
104   -#define CONFIG_RTC_RS5C372A
105   -#undef CONFIG_POST
106   -#define CONFIG_M501SK
107   -#define CONFIG_CMC_PU2
108   -
109   -/* define one of these to choose the DBGU, USART0 or USART1 as console */
110   -#define CONFIG_AT91RM9200_USART
111   -#define CONFIG_DBGU
112   -#undef CONFIG_USART0
113   -#undef CONFIG_USART1
114   -
115   -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
116   -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
117   -
118   -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
119   - "initrd=0x20800000,8192000 ramdisk_size=15360 " \
120   - "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
121   - "128k(loader)ro,128k(reserved)ro,1408k(linux)" \
122   - "ro,2560k(ramdisk)ro,-(userdisk)"
123   -#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
124   -#define CONFIG_BOOTDELAY 1
125   -#define CONFIG_BAUDRATE 115200
126   -#define CONFIG_IPADDR 192.168.1.100
127   -#define CONFIG_SERVERIP 192.168.1.1
128   -#define CONFIG_GATEWAYIP 192.168.1.254
129   -#define CONFIG_NETMASK 255.255.255.0
130   -#define CONFIG_BOOTFILE uImage
131   -#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
132   -#define CONFIG_ENV_OVERWRITE 1
133   -#define BOARD_LATE_INIT
134   -
135   -#define CONFIG_EXTRA_ENV_SETTINGS \
136   - "unlock=yes\0"
137   -
138   -#define CONFIG_CMD_JFFS2
139   -#undef CONFIG_CMD_EEPROM
140   -#define CONFIG_CMD_NET
141   -#define CONFIG_CMD_RUN
142   -#define CONFIG_CMD_DHCP
143   -#define CONFIG_CMD_MEMORY
144   -#define CONFIG_CMD_PING
145   -#define CONFIG_CMD_SDRAM
146   -#define CONFIG_CMD_DIAG
147   -#define CONFIG_CMD_I2C
148   -#define CONFIG_CMD_DATE
149   -#define CONFIG_CMD_POST
150   -#define CONFIG_CMD_MISC
151   -#define CONFIG_CMD_LOADS
152   -#define CONFIG_CMD_IMI
153   -#define CONFIG_CMD_NFS
154   -#define CONFIG_CMD_FLASH
155   -#define CONFIG_CMD_SAVEENV
156   -
157   -#define CONFIG_SYS_HUSH_PARSER
158   -#define CONFIG_AUTO_COMPLETE
159   -#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
160   -
161   -#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
162   -
163   -#define CONFIG_NR_DRAM_BANKS 1
164   -#define PHYS_SDRAM 0x20000000
165   -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
166   -
167   -#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
168   -/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
169   -#define CONFIG_SYS_MEMTEST_END 0x00100000
170   -
171   -#define CONFIG_NET_MULTI 1
172   -#ifdef CONFIG_NET_MULTI
173   -#define CONFIG_DRIVER_AT91EMAC 1
174   -#define CONFIG_SYS_RX_ETH_BUFFER 8
175   -#else
176   -#define CONFIG_DRIVER_ETHER 1
177   -#endif
178   -#define CONFIG_NET_RETRY_COUNT 20
179   -#define CONFIG_AT91C_USE_RMII
180   -
181   -#define PHYS_FLASH_1 0x10000000
182   -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
183   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
184   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
185   -#define CONFIG_SYS_MAX_FLASH_SECT 256
186   -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
187   -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
188   -
189   -#ifdef CONFIG_ENV_IS_IN_DATAFLASH
190   -#define CONFIG_ENV_OFFSET 0x20000
191   -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
192   -#define CONFIG_ENV_SIZE 0x2000
193   -#else
194   -#define CONFIG_ENV_IS_IN_FLASH
195   -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
196   -#define CONFIG_ENV_SIZE 2048
197   -#endif
198   -
199   -#ifdef CONFIG_ENV_IS_IN_EEPROM
200   -#define CONFIG_ENV_OFFSET 1024
201   -#define CONFIG_ENV_SIZE 1024
202   -#endif
203   -
204   -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
205   -
206   -/* use for protect flash sectors */
207   -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
208   -#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
209   -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
210   -
211   -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
212   -
213   -#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
214   -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
215   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
216   -/* Print Buffer Size */
217   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
218   -
219   -#define CONFIG_SYS_HZ 1000
220   -#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2
221   -
222   -#define CONFIG_STACKSIZE (32*1024) /* regular stack */
223   -
224   -#ifdef CONFIG_USE_IRQ
225   -#error CONFIG_USE_IRQ not supported
226   -#endif
227   -
228   -#endif