net: stm32: add designware mac glue code for stm32

This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: stm32: add designware mac glue code for stm32
This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Kurz · Tom Rini
1 parent 081de09d49
Showing 7 changed files with 122 additions and 3 deletions Side-by-side Diff
arch/arm/include/asm/arch-stm32f7/stm32_periph.h
arch/arm/include/asm/arch-stm32f7/syscfg.h
arch/arm/mach-stm32/stm32f7/clock.c
board/st/stm32f746-disco/stm32f746-disco.c
configs/stm32f746-disco_defconfig
drivers/net/designware.c
include/configs/stm32f746-disco.h
@@ -36,6 +36,7 @@
 	SYSCFG_CLOCK_CFG,
 	TIMER2_CLOCK_CFG,
 	FMC_CLOCK_CFG,
+	STMMAC_CLOCK_CFG,
 };
  
 #endif /* __ASM_ARM_ARCH_PERIPH_H */
+/*
+ * (C) Copyright 2016
+ * Michael Kurz, michi.kurz@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_SYSCFG_H
+#define _STM32_SYSCFG_H
+
+struct stm32_syscfg_regs {
+	u32 memrmp;
+	u32 pmc;
+	u32 exticr1;
+	u32 exticr2;
+	u32 exticr3;
+	u32 exticr4;
+	u32 cmpcr;
+};
+
+/*
+ * SYSCFG registers base
+ */
+#define STM32_SYSCFG		((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
+
+/* SYSCFG memory remap register */
+#define SYSCFG_MEMRMP_MEM_BOOT	BIT(0)
+#define SYSCFG_MEMRMP_SWP_FMC	BIT(10)
+
+/* SYSCFG peripheral mode configuration register */
+#define SYSCFG_PMC_ADCXDC2	BIT(16)
+#define SYSCFG_PMC_MII_RMII_SEL	BIT(23)
+
+/* Compensation cell control register */
+#define SYSCFG_CMPCR_CMP_PD	BIT(0)
+#define SYSCFG_CMPCR_READY	BIT(8)
+
+#endif
@@ -261,6 +261,11 @@
 	case FMC_CLOCK_CFG:
 		setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
 		break;
+	case STMMAC_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
+		break;
 	default:
 		break;
 	}
@@ -15,6 +15,7 @@
 #include <dm/platform_data/serial_stm32x7.h>
 #include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_defs.h>
+#include <asm/arch/syscfg.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -276,6 +277,55 @@
 	.platdata = &serial_platdata,
 };
  
+#ifdef CONFIG_ETH_DESIGNWARE
+const struct stm32_gpio_ctl gpio_ctl_eth = {
+	.mode = STM32_GPIO_MODE_AF,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_100M,
+	.pupd = STM32_GPIO_PUPD_NO,
+	.af = STM32_GPIO_AF11
+};
+
+static const struct stm32_gpio_dsc eth_gpio[] = {
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_1},	/* ETH_RMII_REF_CLK */
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_2},	/* ETH_MDIO */
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_7},	/* ETH_RMII_CRS_DV */
+
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_1},	/* ETH_MDC */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_4},	/* ETH_RMII_RXD0 */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_5},	/* ETH_RMII_RXD1 */
+
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_11},	/* ETH_RMII_TX_EN */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_13},	/* ETH_RMII_TXD0 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_14},	/* ETH_RMII_TXD1 */
+};
+
+static int stmmac_setup(void)
+{
+	int res = 0;
+	int i;
+
+	clock_setup(SYSCFG_CLOCK_CFG);
+
+	/* Set >RMII mode */
+	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+
+	clock_setup(GPIO_A_CLOCK_CFG);
+	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_G_CLOCK_CFG);
+
+	for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
+		res = stm32_gpio_config(&eth_gpio[i], &gpio_ctl_eth);
+		if (res)
+			return res;
+	}
+
+	clock_setup(STMMAC_CLOCK_CFG);
+
+	return 0;
+}
+#endif
+
 u32 get_board_rev(void)
 {
 	return 0;
@@ -289,6 +339,12 @@
 	clock_setup(USART1_CLOCK_CFG);
 	if (res)
 		return res;
+
+#ifdef CONFIG_ETH_DESIGNWARE
+	res = stmmac_setup();
+	if (res)
+		return res;
+#endif
  
 	return 0;
 }
@@ -14,8 +14,21 @@
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIMER=y
-CONFIG_OF_LIBFDT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
@@ -763,6 +763,7 @@
 	{ .compatible = "allwinner,sun7i-a20-gmac" },
 	{ .compatible = "altr,socfpga-stmmac" },
 	{ .compatible = "amlogic,meson6-dwmac" },
+	{ .compatible = "st,stm32-dwmac" },
 	{ }
 };
  
@@ -40,6 +40,11 @@
 #define CONFIG_STM32_FLASH
 #define CONFIG_STM32X7_SERIAL
  
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL	(8)
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+
 #define CONFIG_STM32_HSE_HZ		25000000
 #define CONFIG_SYS_CLK_FREQ		200000000 /* 200 MHz */
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
@@ -54,8 +59,8 @@
 					+ sizeof(CONFIG_SYS_PROMPT) + 16)
  
 #define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_MALLOC_LEN		(16 * 1024)
-#define CONFIG_STACKSIZE		(64 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_STACKSIZE		(256 * 1024)
  
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTARGS							\
...	...	@@ -36,6 +36,7 @@
36	36	SYSCFG_CLOCK_CFG,
37	37	TIMER2_CLOCK_CFG,
38	38	FMC_CLOCK_CFG,
	39	+ STMMAC_CLOCK_CFG,
39	40	};
40	41
41	42	#endif /* __ASM_ARM_ARCH_PERIPH_H */
	1	+/*
	2	+ * (C) Copyright 2016
	3	+ * Michael Kurz, michi.kurz@gmail.com.
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#ifndef _STM32_SYSCFG_H
	9	+#define _STM32_SYSCFG_H
	10	+
	11	+struct stm32_syscfg_regs {
	12	+ u32 memrmp;
	13	+ u32 pmc;
	14	+ u32 exticr1;
	15	+ u32 exticr2;
	16	+ u32 exticr3;
	17	+ u32 exticr4;
	18	+ u32 cmpcr;
	19	+};
	20	+
	21	+/*
	22	+ * SYSCFG registers base
	23	+ */
	24	+#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
	25	+
	26	+/* SYSCFG memory remap register */
	27	+#define SYSCFG_MEMRMP_MEM_BOOT BIT(0)
	28	+#define SYSCFG_MEMRMP_SWP_FMC BIT(10)
	29	+
	30	+/* SYSCFG peripheral mode configuration register */
	31	+#define SYSCFG_PMC_ADCXDC2 BIT(16)
	32	+#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
	33	+
	34	+/* Compensation cell control register */
	35	+#define SYSCFG_CMPCR_CMP_PD BIT(0)
	36	+#define SYSCFG_CMPCR_READY BIT(8)
	37	+
	38	+#endif
...	...	@@ -261,6 +261,11 @@
261	261	case FMC_CLOCK_CFG:
262	262	setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
263	263	break;
	264	+ case STMMAC_CLOCK_CFG:
	265	+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
	266	+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
	267	+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
	268	+ break;
264	269	default:
265	270	break;
266	271	}
...	...	@@ -15,6 +15,7 @@
15	15	#include <dm/platform_data/serial_stm32x7.h>
16	16	#include <asm/arch/stm32_periph.h>
17	17	#include <asm/arch/stm32_defs.h>
	18	+#include <asm/arch/syscfg.h>
18	19
19	20	DECLARE_GLOBAL_DATA_PTR;
20	21
...	...	@@ -276,6 +277,55 @@
276	277	.platdata = &serial_platdata,
277	278	};
278	279
	280	+#ifdef CONFIG_ETH_DESIGNWARE
	281	+const struct stm32_gpio_ctl gpio_ctl_eth = {
	282	+ .mode = STM32_GPIO_MODE_AF,
	283	+ .otype = STM32_GPIO_OTYPE_PP,
	284	+ .speed = STM32_GPIO_SPEED_100M,
	285	+ .pupd = STM32_GPIO_PUPD_NO,
	286	+ .af = STM32_GPIO_AF11
	287	+};
	288	+
	289	+static const struct stm32_gpio_dsc eth_gpio[] = {
	290	+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */
	291	+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */
	292	+ {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */
	293	+
	294	+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */
	295	+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */
	296	+ {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */
	297	+
	298	+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */
	299	+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */
	300	+ {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */
	301	+};
	302	+
	303	+static int stmmac_setup(void)
	304	+{
	305	+ int res = 0;
	306	+ int i;
	307	+
	308	+ clock_setup(SYSCFG_CLOCK_CFG);
	309	+
	310	+ /* Set >RMII mode */
	311	+ STM32_SYSCFG->pmc \|= SYSCFG_PMC_MII_RMII_SEL;
	312	+
	313	+ clock_setup(GPIO_A_CLOCK_CFG);
	314	+ clock_setup(GPIO_C_CLOCK_CFG);
	315	+ clock_setup(GPIO_G_CLOCK_CFG);
	316	+
	317	+ for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
	318	+ res = stm32_gpio_config(&eth_gpio[i], &gpio_ctl_eth);
	319	+ if (res)
	320	+ return res;
	321	+ }
	322	+
	323	+ clock_setup(STMMAC_CLOCK_CFG);
	324	+
	325	+ return 0;
	326	+}
	327	+#endif
	328	+
279	329	u32 get_board_rev(void)
280	330	{
281	331	return 0;
...	...	@@ -289,6 +339,12 @@
289	339	clock_setup(USART1_CLOCK_CFG);
290	340	if (res)
291	341	return res;
	342	+
	343	+#ifdef CONFIG_ETH_DESIGNWARE
	344	+ res = stmmac_setup();
	345	+ if (res)
	346	+ return res;
	347	+#endif
292	348
293	349	return 0;
294	350	}
...	...	@@ -14,8 +14,21 @@
14	14	CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
15	15	CONFIG_AUTOBOOT_STOP_STR=" "
16	16	# CONFIG_CMD_IMLS is not set
	17	+# CONFIG_CMD_FPGA is not set
17	18	# CONFIG_CMD_SETEXPR is not set
	19	+CONFIG_CMD_DHCP=y
	20	+CONFIG_CMD_MII=y
	21	+CONFIG_CMD_PING=y
	22	+CONFIG_CMD_SNTP=y
	23	+CONFIG_CMD_DNS=y
	24	+CONFIG_CMD_LINK_LOCAL=y
18	25	CONFIG_CMD_TIMER=y
19		-CONFIG_OF_LIBFDT=y
	26	+CONFIG_OF_CONTROL=y
	27	+CONFIG_NET_RANDOM_ETHADDR=y
	28	+CONFIG_NETCONSOLE=y
	29	+CONFIG_DM_ETH=y
	30	+CONFIG_ETH_DESIGNWARE=y
	31	+# CONFIG_SPL_SERIAL_PRESENT is not set
	32	+CONFIG_OF_LIBFDT_OVERLAY=y
20	33	# CONFIG_EFI_LOADER is not set
...	...	@@ -763,6 +763,7 @@
763	763	{ .compatible = "allwinner,sun7i-a20-gmac" },
764	764	{ .compatible = "altr,socfpga-stmmac" },
765	765	{ .compatible = "amlogic,meson6-dwmac" },
	766	+ { .compatible = "st,stm32-dwmac" },
766	767	{ }
767	768	};
768	769
...	...	@@ -40,6 +40,11 @@
40	40	#define CONFIG_STM32_FLASH
41	41	#define CONFIG_STM32X7_SERIAL
42	42
	43	+#define CONFIG_DESIGNWARE_ETH
	44	+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
	45	+#define CONFIG_DW_ALTDESCRIPTOR
	46	+#define CONFIG_MII
	47	+
43	48	#define CONFIG_STM32_HSE_HZ 25000000
44	49	#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
45	50	#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
...	...	@@ -54,8 +59,8 @@
54	59	+ sizeof(CONFIG_SYS_PROMPT) + 16)
55	60
56	61	#define CONFIG_SYS_MAXARGS 16
57		-#define CONFIG_SYS_MALLOC_LEN (16 * 1024)
58		-#define CONFIG_STACKSIZE (64 << 10)
	62	+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
	63	+#define CONFIG_STACKSIZE (256 * 1024)
59	64
60	65	#define CONFIG_BAUDRATE 115200
61	66	#define CONFIG_BOOTARGS \