Eric Lee / smarc-uboot

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Commit b2323ea6f9ae478680baa964bdd97d8567507e91

Authored by wdenk
1 parent fddae7b811

Auto-size RAM on canmb board. 

Cleanup.

Showing 5 changed files with 206 additions and 68 deletions Side-by-side Diff

... ... @@ -6,6 +6,8 @@
6 6 Make PCI target address spaces on PMC405 and CPCI405 boards
7 7 configurable via environment variables
8 8  
  9 +* Auto-size RAM on canmb board.
  10 +
9 11 * Add support for canmb board
10 12  
11 13 * Patch by Stefan Roese, 13 Apr 2005:
... ... @@ -2,8 +2,8 @@
2 2 * (C) Copyright 2005
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * (C) Copyright 2003
6   - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
  5 + * (C) Copyright 2004
  6 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
9 9 * project.
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
... ... @@ -28,64 +28,209 @@
28 28 #include <mpc5xxx.h>
29 29 #include <pci.h>
30 30  
31   -/*****************************************************************************
32   - * initialize SDRAM/DDRAM controller.
33   - * TBD: get data from I2C EEPROM
34   - *****************************************************************************/
35   -long int initdram (int board_type)
36   -{
37   - ulong dramsize = 0;
38   -#ifndef CFG_RAMBOOT
39   -#if 0
40   - ulong t;
41   - ulong tap_del;
  31 +#if defined(CONFIG_MPC5200_DDR)
  32 +#include "mt46v16m16-75.h"
  33 +#else
  34 +#include "mt48lc16m32s2-75.h"
42 35 #endif
43 36  
44   - #define MODE_EN 0x80000000
45   - #define SOFT_PRE 2
46   - #define SOFT_REF 4
  37 +#ifndef CFG_RAMBOOT
  38 +static void sdram_start (int hi_addr)
  39 +{
  40 + long hi_addr_bit = hi_addr ? 0x01000000 : 0;
47 41  
48   - /* configure SDRAM start/end */
49   - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
50   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x8000000;
51   -
52   - /* setup config registers */
53   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
54   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
55   -
56 42 /* unlock mode register */
57   - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
  43 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  44 + __asm__ volatile ("sync");
  45 +
58 46 /* precharge all banks */
59   - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
60   -#ifdef CFG_DRAM_DDR
61   - /* set extended mode register */
62   - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
  47 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  48 + __asm__ volatile ("sync");
  49 +
  50 +#if SDRAM_DDR
  51 + /* set mode register: extended mode */
  52 + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  53 + __asm__ volatile ("sync");
  54 +
  55 + /* set mode register: reset DLL */
  56 + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  57 + __asm__ volatile ("sync");
63 58 #endif
64   - /* set mode register */
65   - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
  59 +
66 60 /* precharge all banks */
67   - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
  61 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  62 + __asm__ volatile ("sync");
  63 +
68 64 /* auto refresh */
69   - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
  65 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  66 + __asm__ volatile ("sync");
  67 +
70 68 /* set mode register */
71   - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
  69 + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  70 + __asm__ volatile ("sync");
  71 +
72 72 /* normal operation */
73   - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
74   - /* write default TAP delay */
75   - *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
  73 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  74 + __asm__ volatile ("sync");
  75 +}
  76 +#endif
76 77  
  78 +/*
  79 + * ATTENTION: Although partially referenced initdram does NOT make real use
  80 + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  81 + * is something else than 0x00000000.
  82 + */
  83 +
  84 +#if defined(CONFIG_MPC5200)
  85 +long int initdram (int board_type)
  86 +{
  87 + ulong dramsize = 0;
  88 + ulong dramsize2 = 0;
  89 +#ifndef CFG_RAMBOOT
  90 + ulong test1, test2;
  91 +
  92 + /* setup SDRAM chip selects */
  93 + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  94 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  95 + __asm__ volatile ("sync");
  96 +
  97 + /* setup config registers */
  98 + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  99 + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  100 + __asm__ volatile ("sync");
  101 +
  102 +#if SDRAM_DDR
  103 + /* set tap delay */
  104 + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
  105 + __asm__ volatile ("sync");
  106 +#endif
  107 +
  108 + /* find RAM size using SDRAM CS0 only */
  109 + sdram_start(0);
  110 + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  111 + sdram_start(1);
  112 + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  113 + if (test1 > test2) {
  114 + sdram_start(0);
  115 + dramsize = test1;
  116 + } else {
  117 + dramsize = test2;
  118 + }
  119 +
  120 + /* memory smaller than 1MB is impossible */
  121 + if (dramsize < (1 << 20)) {
  122 + dramsize = 0;
  123 + }
  124 +
  125 + /* set SDRAM CS0 size according to the amount of RAM found */
  126 + if (dramsize > 0) {
  127 + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
  128 + } else {
  129 + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
  130 + }
  131 +
  132 + /* let SDRAM CS1 start right after CS0 */
  133 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
  134 +
  135 + /* find RAM size using SDRAM CS1 only */
  136 + sdram_start(0);
  137 + test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
  138 + sdram_start(1);
  139 + test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
  140 + if (test1 > test2) {
  141 + sdram_start(0);
  142 + dramsize2 = test1;
  143 + } else {
  144 + dramsize2 = test2;
  145 + }
  146 +
  147 + /* memory smaller than 1MB is impossible */
  148 + if (dramsize2 < (1 << 20)) {
  149 + dramsize2 = 0;
  150 + }
  151 +
  152 + /* set SDRAM CS1 size according to the amount of RAM found */
  153 + if (dramsize2 > 0) {
  154 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
  155 + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
  156 + } else {
  157 + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
  158 + }
  159 +
  160 +#else /* CFG_RAMBOOT */
  161 +
  162 + /* retrieve size of memory connected to SDRAM CS0 */
  163 + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
  164 + if (dramsize >= 0x13) {
  165 + dramsize = (1 << (dramsize - 0x13)) << 20;
  166 + } else {
  167 + dramsize = 0;
  168 + }
  169 +
  170 + /* retrieve size of memory connected to SDRAM CS1 */
  171 + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
  172 + if (dramsize2 >= 0x13) {
  173 + dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  174 + } else {
  175 + dramsize2 = 0;
  176 + }
  177 +
77 178 #endif /* CFG_RAMBOOT */
78 179  
79   - dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20) +
80   - ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
  180 + return dramsize + dramsize2;
  181 +}
81 182  
82   - /* return total ram size */
  183 +#elif defined(CONFIG_MGT5100)
  184 +
  185 +long int initdram (int board_type)
  186 +{
  187 + ulong dramsize = 0;
  188 +#ifndef CFG_RAMBOOT
  189 + ulong test1, test2;
  190 +
  191 + /* setup and enable SDRAM chip selects */
  192 + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
  193 + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
  194 + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
  195 + __asm__ volatile ("sync");
  196 +
  197 + /* setup config registers */
  198 + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  199 + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  200 +
  201 + /* address select register */
  202 + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
  203 + __asm__ volatile ("sync");
  204 +
  205 + /* find RAM size */
  206 + sdram_start(0);
  207 + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  208 + sdram_start(1);
  209 + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
  210 + if (test1 > test2) {
  211 + sdram_start(0);
  212 + dramsize = test1;
  213 + } else {
  214 + dramsize = test2;
  215 + }
  216 +
  217 + /* set SDRAM end address according to size */
  218 + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
  219 +
  220 +#else /* CFG_RAMBOOT */
  221 +
  222 + /* Retrieve amount of SDRAM available */
  223 + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
  224 +
  225 +#endif /* CFG_RAMBOOT */
  226 +
83 227 return dramsize;
84 228 }
85 229  
86   -/*****************************************************************************
87   - * print board identification
88   - *****************************************************************************/
  230 +#else
  231 +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
  232 +#endif
  233 +
89 234 int checkboard (void)
90 235 {
91 236 puts ("Board: CANMB\n");
doc/README.ocotea-PIBS-to-U-Boot
Diff comments   View file @ b2323ea
... ... @@ -77,14 +77,14 @@
77 77  
78 78 IBM PowerPC 440 GX Rev. C
79 79 Board: IBM 440GX Evaluation Board
80   - VCO: 1066 MHz
81   - CPU: 533 MHz
82   - PLB: 152 MHz
83   - OPB: 76 MHz
84   - EPB: 76 MHz
  80 + VCO: 1066 MHz
  81 + CPU: 533 MHz
  82 + PLB: 152 MHz
  83 + OPB: 76 MHz
  84 + EPB: 76 MHz
85 85 I2C: ready
86 86 DRAM: 256 MB
87   -FLASH: 5 MB
  87 +FLASH: 5 MB
88 88 PCI: Bus Dev VenId DevId Class Int
89 89 In: serial
90 90 Out: serial
drivers/netconsole.c
Diff comments   View file @ b2323ea
... ... @@ -153,11 +153,12 @@
153 153 nc_port = 6666; /* default port */
154 154  
155 155 if (getenv ("ncip")) {
  156 + char *p;
  157 +
156 158 nc_ip = getenv_IPaddr ("ncip");
157 159 if (!nc_ip)
158 160 return -1; /* ncip is 0.0.0.0 */
159   - char *p = strchr (getenv ("ncip"), ':');
160   - if (p)
  161 + if ((p = strchr (getenv ("ncip"), ':')) != NULL)
161 162 nc_port = simple_strtoul (p + 1, NULL, 10);
162 163 } else
163 164 nc_ip = ~0; /* ncip is not set */
164 165  
... ... @@ -188,13 +189,13 @@
188 189  
189 190 void nc_puts (const char *s)
190 191 {
  192 + int len;
  193 +
191 194 if (output_recursion)
192 195 return;
193 196 output_recursion = 1;
194 197  
195   - int len = strlen (s);
196   -
197   - if (len > 512)
  198 + if ((len = strlen (s)) > 512)
198 199 len = 512;
199 200  
200 201 nc_send_packet (s, len);
... ... @@ -204,6 +205,8 @@
204 205  
205 206 int nc_getc (void)
206 207 {
  208 + uchar c;
  209 +
207 210 input_recursion = 1;
208 211  
209 212 net_timeout = 0; /* no timeout */
... ... @@ -212,8 +215,8 @@
212 215  
213 216 input_recursion = 0;
214 217  
215   - uchar c = input_buffer[input_offset];
216   - input_offset++;
  218 + c = input_buffer[input_offset++];
  219 +
217 220 if (input_offset >= sizeof input_buffer)
218 221 input_offset -= sizeof input_buffer;
219 222 input_size--;
include/configs/canmb.h
Diff comments   View file @ b2323ea
... ... @@ -129,18 +129,6 @@
129 129 #define CFG_FLASH_EMPTY_INFO
130 130  
131 131 /*
132   - * DRAM configuration
133   - */
134   -#define CFG_DRAM_DDR 0
135   -#define CFG_DRAM_EMODE 0
136   -#define CFG_DRAM_MODE 0x00CD
137   -#define CFG_DRAM_CONTROL 0x514F0000
138   -#define CFG_DRAM_CONFIG1 0xD2333A00
139   -#define CFG_DRAM_CONFIG2 0x8AD70004
140   -#define CFG_DRAM_TAP_DEL 0x08
141   -#define CFG_DRAM_RAM_SIZE 0x19
142   -
143   -/*
144 132 * Environment settings
145 133 */
146 134 #define CFG_ENV_IS_IN_FLASH 1