Eric Lee / smarc-uboot

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Commit b34b40e4918ced6792ea5f4b588bf394570e75cc

Authored by Robin Gong
1 parent 4168bfe694
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sx 

Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
bit to avoid system reboot during normal kernel boot.
For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
before mux ready, otherwise also cause reboot. But that dependes on hardware
design, only need on mx6sxsabresd board.

Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43)

Showing 2 changed files with 19 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ b34b40e
... ... @@ -228,6 +228,10 @@
228 228 {
229 229 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
230 230 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  231 +#ifdef CONFIG_MX6SX
  232 + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  233 + writew(enable, &wdog3->wmcr);
  234 +#endif
231 235  
232 236 /* Write to the PDE (Power Down Enable) bit */
233 237 writew(enable, &wdog1->wmcr);
board/freescale/mx6sxsabresd/mx6sxsabresd.c
Diff comments   View file @ b34b40e
... ... @@ -72,6 +72,8 @@
72 72 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
73 73 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm)
74 74  
  75 +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  76 + PAD_CTL_DSE_40ohm)
75 77  
76 78 #ifdef CONFIG_SYS_I2C_MXC
77 79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
... ... @@ -175,6 +177,10 @@
175 177 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 178 };
177 179  
  180 +static iomux_v3_cfg_t const wdog_b_pad = {
  181 + MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  182 +};
  183 +
178 184 #ifdef CONFIG_FEC_MXC
179 185 static iomux_v3_cfg_t const fec1_pads[] = {
180 186 MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
... ... @@ -864,6 +870,15 @@
864 870 {
865 871 /* Address of boot parameters */
866 872 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  873 +
  874 + /*
  875 + * Because kernel set WDOG_B mux before pad with the commone pinctrl
  876 + * framwork now and wdog reset will be triggered once set WDOG_B mux
  877 + * with default pad setting, we set pad setting here to workaround this.
  878 + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
  879 + * as GPIO mux firstly here to workaround it.
  880 + */
  881 + imx_iomux_v3_setup_pad(wdog_b_pad);
867 882  
868 883 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
869 884 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads));