Eric Lee / smarc-uboot | Embedian Git Server

Commit b357503f1cdedade6d31991fa6aabb4174f92989

Authored by Ye.Li 2014-09-29 23:26:28 +0800

Committed by Stefano Babic 2014-09-30 18:21:14 +0800

Exists in v2017.01-smarct4x and in 37 other branches

imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board

This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.

The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.

Signed-off-by: Ye.Li <B37916@freescale.com>

Showing 6 changed files with 157 additions and 2 deletions Inline Diff

board/freescale/mx6qarm2/MAINTAINERS
board/freescale/mx6qarm2/imximage_mx6dl.cfg
board/freescale/mx6qarm2/mx6qarm2.c
configs/mx6dlarm2_defconfig
configs/mx6qarm2_defconfig
include/configs/mx6qarm2.h

board/freescale/mx6qarm2/MAINTAINERS

Diff comments View file @ b357503

 MX6QARM2 BOARD
 M:	Jason Liu <r64343@freescale.com>
+M:	Ye Li <b37916@freescale.com>
 S:	Maintained
 F:	board/freescale/mx6qarm2/
 F:	include/configs/mx6qarm2.h
 F:	configs/mx6qarm2_defconfig
+F:	configs/mx6dlarm2_defconfig

board/freescale/mx6qarm2/imximage_mx6dl.cfg

Diff comments View file @ b357503

File was created	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	3	* Jason Liu <r64343@freescale.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*
	7	* Refer doc/README.imximage for more details about how-to configure
	8	* and create imximage boot image
	9	*
	10	* The syntax is taken as close as possible with the kwbimage
	11	*/
	12
	13	/* image version */
	14	IMAGE_VERSION 2
	15
	16	/*
	17	* Boot Device : one of
	18	* spi, sd (the board has no nand neither onenand)
	19	*/
	20	BOOT_FROM sd
	21
	22	/*
	23	* Device Configuration Data (DCD)
	24	*
	25	* Each entry must have the format:
	26	* Addr-type Address Value
	27	*
	28	* where:
	29	* Addr-type register length (1,2 or 4 bytes)
	30	* Address absolute address of the register
	31	* value value to be stored in the register
	32	*/
	33	DATA 4 0x020e0798 0x000c0000
	34	DATA 4 0x020e0758 0x00000000
	35	DATA 4 0x020e0588 0x00000030
	36	DATA 4 0x020e0594 0x00000030
	37	DATA 4 0x020e056c 0x00000030
	38	DATA 4 0x020e0578 0x00000030
	39	DATA 4 0x020e074c 0x00000030
	40	DATA 4 0x020e057c 0x00000030
	41	DATA 4 0x020e0590 0x00003000
	42	DATA 4 0x020e0598 0x00003000
	43	DATA 4 0x020e058c 0x00000000
	44	DATA 4 0x020e059c 0x00003030
	45	DATA 4 0x020e05a0 0x00003030
	46	DATA 4 0x020e078c 0x00000030
	47	DATA 4 0x020e0750 0x00020000
	48	DATA 4 0x020e05a8 0x00000030
	49	DATA 4 0x020e05b0 0x00000030
	50	DATA 4 0x020e0524 0x00000030
	51	DATA 4 0x020e051c 0x00000030
	52	DATA 4 0x020e0518 0x00000030
	53	DATA 4 0x020e050c 0x00000030
	54	DATA 4 0x020e05b8 0x00000030
	55	DATA 4 0x020e05c0 0x00000030
	56	DATA 4 0x020e0774 0x00020000
	57	DATA 4 0x020e0784 0x00000030
	58	DATA 4 0x020e0788 0x00000030
	59	DATA 4 0x020e0794 0x00000030
	60	DATA 4 0x020e079c 0x00000030
	61	DATA 4 0x020e07a0 0x00000030
	62	DATA 4 0x020e07a4 0x00000030
	63	DATA 4 0x020e07a8 0x00000030
	64	DATA 4 0x020e0748 0x00000030
	65	DATA 4 0x020e05ac 0x00000030
	66	DATA 4 0x020e05b4 0x00000030
	67	DATA 4 0x020e0528 0x00000030
	68	DATA 4 0x020e0520 0x00000030
	69	DATA 4 0x020e0514 0x00000030
	70	DATA 4 0x020e0510 0x00000030
	71	DATA 4 0x020e05bc 0x00000030
	72	DATA 4 0x020e05c4 0x00000030
	73
	74	DATA 4 0x021b0800 0xa1390003
	75	DATA 4 0x021b4800 0xa1390003
	76	DATA 4 0x021b080c 0x001F001F
	77	DATA 4 0x021b0810 0x001F001F
	78	DATA 4 0x021b480c 0x00370037
	79	DATA 4 0x021b4810 0x00370037
	80	DATA 4 0x021b083c 0x422f0220
	81	DATA 4 0x021b0840 0x021f0219
	82	DATA 4 0x021b483C 0x422f0220
	83	DATA 4 0x021b4840 0x022d022f
	84	DATA 4 0x021b0848 0x47494b49
	85	DATA 4 0x021b4848 0x48484c47
	86	DATA 4 0x021b0850 0x39382b2f
	87	DATA 4 0x021b4850 0x2f35312c
	88	DATA 4 0x021b081c 0x33333333
	89	DATA 4 0x021b0820 0x33333333
	90	DATA 4 0x021b0824 0x33333333
	91	DATA 4 0x021b0828 0x33333333
	92	DATA 4 0x021b481c 0x33333333
	93	DATA 4 0x021b4820 0x33333333
	94	DATA 4 0x021b4824 0x33333333
	95	DATA 4 0x021b4828 0x33333333
	96	DATA 4 0x021b08b8 0x00000800
	97	DATA 4 0x021b48b8 0x00000800
	98	DATA 4 0x021b0004 0x0002002d
	99	DATA 4 0x021b0008 0x00333030
	100
	101	DATA 4 0x021b000c 0x40445323
	102	DATA 4 0x021b0010 0xb66e8c63
	103
	104	DATA 4 0x021b0014 0x01ff00db
	105	DATA 4 0x021b0018 0x00081740
	106	DATA 4 0x021b001c 0x00008000
	107	DATA 4 0x021b002c 0x000026d2
	108	DATA 4 0x021b0030 0x00440e21
	109	#ifdef CONFIG_DDR_32BIT
	110	DATA 4 0x021b0040 0x00000017
	111	DATA 4 0x021b0000 0xc3190000
	112	#else
	113	DATA 4 0x021b0040 0x00000027
	114	DATA 4 0x021b0000 0xc31a0000
	115	#endif
	116	DATA 4 0x021b001c 0x04008032
	117	DATA 4 0x021b001c 0x0400803a
	118	DATA 4 0x021b001c 0x00008033
	119	DATA 4 0x021b001c 0x0000803b
	120	DATA 4 0x021b001c 0x00428031
	121	DATA 4 0x021b001c 0x00428039
	122	DATA 4 0x021b001c 0x07208030
	123	DATA 4 0x021b001c 0x07208038
	124	DATA 4 0x021b001c 0x04008040
	125	DATA 4 0x021b001c 0x04008048
	126	DATA 4 0x021b0020 0x00005800
	127	DATA 4 0x021b0818 0x00000007
	128	DATA 4 0x021b4818 0x00000007
	129	DATA 4 0x021b0004 0x0002556d
	130	DATA 4 0x021b4004 0x00011006
	131	DATA 4 0x021b001c 0x00000000
	132
	133	DATA 4 0x020c4068 0x00C03F3F
	134	DATA 4 0x020c406c 0x0030FC03
	135	DATA 4 0x020c4070 0x0FFFC000
	136	DATA 4 0x020c4074 0x3FF00000
	137	DATA 4 0x020c4078 0x00FFF300
	138	DATA 4 0x020c407c 0x0F0000C3
	139	DATA 4 0x020c4080 0x000003FF
	140
	141	DATA 4 0x020e0010 0xF00000CF
	142	DATA 4 0x020e0018 0x007F007F
	143	DATA 4 0x020e001c 0x007F007F
	144

board/freescale/mx6qarm2/mx6qarm2.c

Diff comments View file @ b357503

 /*
  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 	return 0;
 }
 iomux_v3_cfg_t const uart4_pads[] = {
 	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_CS0__GPIO6_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 static void setup_iomux_enet(void)
 {
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 }
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
 };
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 		gpio_direction_input(IMX_GPIO_NR(6, 11));
 		ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
 	} else /* Don't have the CD GPIO pin on board */
 		ret = 1;
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	s32 status = 0;
 	u32 index = 0;
 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 		switch (index) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) then supported by the board (%d)\n",
 				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 			return status;
 		}
 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 	}
 	return status;
 }
 #endif
 #define MII_MMD_ACCESS_CTRL_REG		0xd
 #define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
 #define MII_DBG_PORT_REG		0x1d
 #define MII_DBG_PORT2_REG		0x1e
 int fecmxc_mii_postcall(int phy)
 {
 	unsigned short val;
 	/*
 	 * Due to the i.MX6Q Armadillo2 board HW design,there is
 	 * no 125Mhz clock input from SOC. In order to use RGMII,
 	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
 	 */
 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
 	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
 	val &= 0xffe3;
 	val |= 0x18;
 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
 	/* For the RGMII phy, we need enable tx clock delay */
 	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
 	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
 	val |= 0x0100;
 	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
 	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
 	return 0;
 }
 int board_eth_init(bd_t *bis)
 {
 	struct eth_device *dev;
 	int ret = cpu_eth_init(bis);
 	if (ret)
 		return ret;
 	dev = eth_get_dev_by_name("FEC");
 	if (!dev) {
 		printf("FEC MXC: Unable to get FEC device entry\n");
 		return -EINVAL;
 	}
 	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
 	if (ret) {
 		printf("FEC MXC: Unable to register FEC mii postcall\n");
 		return ret;
 	}
 	return 0;
 }
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
 	setup_iomux_enet();
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 	return 0;
 }
 int checkboard(void)
 {
+#ifdef CONFIG_MX6DL
+	puts("Board: MX6DL-Armadillo2\n");
+#else
 	puts("Board: MX6Q-Armadillo2\n");
+#endif
 	return 0;
 }

configs/mx6dlarm2_defconfig

Diff comments View file @ b357503

File was created	1	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL"
	2	CONFIG_ARM=y
	3	CONFIG_TARGET_MX6QARM2=y
	4

configs/mx6qarm2_defconfig

Diff comments View file @ b357503

1	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg"	1	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q"
2	CONFIG_ARM=y	2	CONFIG_ARM=y
3	CONFIG_TARGET_MX6QARM2=y	3	CONFIG_TARGET_MX6QARM2=y
4		4

include/configs/mx6qarm2.h

Diff comments View file @ b357503

 /*
  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  *
  * Configuration settings for the Freescale i.MX6Q Armadillo2 board.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 #include "mx6_common.h"
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #include <asm/arch/imx-regs.h>
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_SYS_GENERIC_BOARD
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART4_BASE
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define	CONFIG_FEC_MXC
 #define	CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define	CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_FEC_MXC_PHYADDR		0
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
 /* Command definition */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_IMLS
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_LOADADDR			0x12000000
 #define CONFIG_SYS_TEXT_BASE		0x17800000
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc3\0" \
 	"fdt_file=imx6q-arm2.dtb\0" \
 	"fdt_addr=0x18000000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=1\0" \
 	"mmcpart=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
 			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs; " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
 			"bootz; " \
 		"fi;\0"
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev};" \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
 			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
 		"fi; " \
 	"else run netboot; fi"
 #define CONFIG_ARP_TIMEOUT	200UL
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x10010000
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_CMDLINE_EDITING
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#ifdef CONFIG_DDR_32BIT
+#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
+#else
 #define PHYS_SDRAM_SIZE			(2u * 1024 * 1024 * 1024)
+#endif
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
 #define CONFIG_ENV_SIZE			(8 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #endif				/* __CONFIG_H */