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Commit b357503f1cdedade6d31991fa6aabb4174f92989

Authored by Ye.Li
Committed by Stefano Babic
1 parent febae49a2b
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board 

This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.

The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.

Signed-off-by: Ye.Li <B37916@freescale.com>

Showing 6 changed files with 157 additions and 2 deletions Side-by-side Diff

board/freescale/mx6qarm2/MAINTAINERS
Diff comments   View file @ b357503
1 1 MX6QARM2 BOARD
2 2 M: Jason Liu <r64343@freescale.com>
  3 +M: Ye Li <b37916@freescale.com>
3 4 S: Maintained
4 5 F: board/freescale/mx6qarm2/
5 6 F: include/configs/mx6qarm2.h
6 7 F: configs/mx6qarm2_defconfig
  8 +F: configs/mx6dlarm2_defconfig
board/freescale/mx6qarm2/imximage_mx6dl.cfg
Diff comments   View file @ b357503
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer doc/README.imximage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +/* image version */
  14 +IMAGE_VERSION 2
  15 +
  16 +/*
  17 + * Boot Device : one of
  18 + * spi, sd (the board has no nand neither onenand)
  19 + */
  20 +BOOT_FROM sd
  21 +
  22 +/*
  23 + * Device Configuration Data (DCD)
  24 + *
  25 + * Each entry must have the format:
  26 + * Addr-type Address Value
  27 + *
  28 + * where:
  29 + * Addr-type register length (1,2 or 4 bytes)
  30 + * Address absolute address of the register
  31 + * value value to be stored in the register
  32 + */
  33 +DATA 4 0x020e0798 0x000c0000
  34 +DATA 4 0x020e0758 0x00000000
  35 +DATA 4 0x020e0588 0x00000030
  36 +DATA 4 0x020e0594 0x00000030
  37 +DATA 4 0x020e056c 0x00000030
  38 +DATA 4 0x020e0578 0x00000030
  39 +DATA 4 0x020e074c 0x00000030
  40 +DATA 4 0x020e057c 0x00000030
  41 +DATA 4 0x020e0590 0x00003000
  42 +DATA 4 0x020e0598 0x00003000
  43 +DATA 4 0x020e058c 0x00000000
  44 +DATA 4 0x020e059c 0x00003030
  45 +DATA 4 0x020e05a0 0x00003030
  46 +DATA 4 0x020e078c 0x00000030
  47 +DATA 4 0x020e0750 0x00020000
  48 +DATA 4 0x020e05a8 0x00000030
  49 +DATA 4 0x020e05b0 0x00000030
  50 +DATA 4 0x020e0524 0x00000030
  51 +DATA 4 0x020e051c 0x00000030
  52 +DATA 4 0x020e0518 0x00000030
  53 +DATA 4 0x020e050c 0x00000030
  54 +DATA 4 0x020e05b8 0x00000030
  55 +DATA 4 0x020e05c0 0x00000030
  56 +DATA 4 0x020e0774 0x00020000
  57 +DATA 4 0x020e0784 0x00000030
  58 +DATA 4 0x020e0788 0x00000030
  59 +DATA 4 0x020e0794 0x00000030
  60 +DATA 4 0x020e079c 0x00000030
  61 +DATA 4 0x020e07a0 0x00000030
  62 +DATA 4 0x020e07a4 0x00000030
  63 +DATA 4 0x020e07a8 0x00000030
  64 +DATA 4 0x020e0748 0x00000030
  65 +DATA 4 0x020e05ac 0x00000030
  66 +DATA 4 0x020e05b4 0x00000030
  67 +DATA 4 0x020e0528 0x00000030
  68 +DATA 4 0x020e0520 0x00000030
  69 +DATA 4 0x020e0514 0x00000030
  70 +DATA 4 0x020e0510 0x00000030
  71 +DATA 4 0x020e05bc 0x00000030
  72 +DATA 4 0x020e05c4 0x00000030
  73 +
  74 +DATA 4 0x021b0800 0xa1390003
  75 +DATA 4 0x021b4800 0xa1390003
  76 +DATA 4 0x021b080c 0x001F001F
  77 +DATA 4 0x021b0810 0x001F001F
  78 +DATA 4 0x021b480c 0x00370037
  79 +DATA 4 0x021b4810 0x00370037
  80 +DATA 4 0x021b083c 0x422f0220
  81 +DATA 4 0x021b0840 0x021f0219
  82 +DATA 4 0x021b483C 0x422f0220
  83 +DATA 4 0x021b4840 0x022d022f
  84 +DATA 4 0x021b0848 0x47494b49
  85 +DATA 4 0x021b4848 0x48484c47
  86 +DATA 4 0x021b0850 0x39382b2f
  87 +DATA 4 0x021b4850 0x2f35312c
  88 +DATA 4 0x021b081c 0x33333333
  89 +DATA 4 0x021b0820 0x33333333
  90 +DATA 4 0x021b0824 0x33333333
  91 +DATA 4 0x021b0828 0x33333333
  92 +DATA 4 0x021b481c 0x33333333
  93 +DATA 4 0x021b4820 0x33333333
  94 +DATA 4 0x021b4824 0x33333333
  95 +DATA 4 0x021b4828 0x33333333
  96 +DATA 4 0x021b08b8 0x00000800
  97 +DATA 4 0x021b48b8 0x00000800
  98 +DATA 4 0x021b0004 0x0002002d
  99 +DATA 4 0x021b0008 0x00333030
  100 +
  101 +DATA 4 0x021b000c 0x40445323
  102 +DATA 4 0x021b0010 0xb66e8c63
  103 +
  104 +DATA 4 0x021b0014 0x01ff00db
  105 +DATA 4 0x021b0018 0x00081740
  106 +DATA 4 0x021b001c 0x00008000
  107 +DATA 4 0x021b002c 0x000026d2
  108 +DATA 4 0x021b0030 0x00440e21
  109 +#ifdef CONFIG_DDR_32BIT
  110 +DATA 4 0x021b0040 0x00000017
  111 +DATA 4 0x021b0000 0xc3190000
  112 +#else
  113 +DATA 4 0x021b0040 0x00000027
  114 +DATA 4 0x021b0000 0xc31a0000
  115 +#endif
  116 +DATA 4 0x021b001c 0x04008032
  117 +DATA 4 0x021b001c 0x0400803a
  118 +DATA 4 0x021b001c 0x00008033
  119 +DATA 4 0x021b001c 0x0000803b
  120 +DATA 4 0x021b001c 0x00428031
  121 +DATA 4 0x021b001c 0x00428039
  122 +DATA 4 0x021b001c 0x07208030
  123 +DATA 4 0x021b001c 0x07208038
  124 +DATA 4 0x021b001c 0x04008040
  125 +DATA 4 0x021b001c 0x04008048
  126 +DATA 4 0x021b0020 0x00005800
  127 +DATA 4 0x021b0818 0x00000007
  128 +DATA 4 0x021b4818 0x00000007
  129 +DATA 4 0x021b0004 0x0002556d
  130 +DATA 4 0x021b4004 0x00011006
  131 +DATA 4 0x021b001c 0x00000000
  132 +
  133 +DATA 4 0x020c4068 0x00C03F3F
  134 +DATA 4 0x020c406c 0x0030FC03
  135 +DATA 4 0x020c4070 0x0FFFC000
  136 +DATA 4 0x020c4074 0x3FF00000
  137 +DATA 4 0x020c4078 0x00FFF300
  138 +DATA 4 0x020c407c 0x0F0000C3
  139 +DATA 4 0x020c4080 0x000003FF
  140 +
  141 +DATA 4 0x020e0010 0xF00000CF
  142 +DATA 4 0x020e0018 0x007F007F
  143 +DATA 4 0x020e001c 0x007F007F
board/freescale/mx6qarm2/mx6qarm2.c
Diff comments   View file @ b357503
... ... @@ -224,7 +224,11 @@
224 224  
225 225 int checkboard(void)
226 226 {
  227 +#ifdef CONFIG_MX6DL
  228 + puts("Board: MX6DL-Armadillo2\n");
  229 +#else
227 230 puts("Board: MX6Q-Armadillo2\n");
  231 +#endif
228 232  
229 233 return 0;
230 234 }
configs/mx6dlarm2_defconfig
Diff comments   View file @ b357503
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL"
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_MX6QARM2=y
configs/mx6qarm2_defconfig
Diff comments   View file @ b357503
1   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg"
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q"
2 2 CONFIG_ARM=y
3 3 CONFIG_TARGET_MX6QARM2=y
include/configs/mx6qarm2.h
Diff comments   View file @ b357503
... ... @@ -10,7 +10,6 @@
10 10 #define __CONFIG_H
11 11  
12 12 #define CONFIG_MX6
13   -#define CONFIG_MX6Q
14 13  
15 14 #include "mx6_common.h"
16 15  
17 16  
... ... @@ -169,7 +168,11 @@
169 168 /* Physical Memory Map */
170 169 #define CONFIG_NR_DRAM_BANKS 1
171 170 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  171 +#ifdef CONFIG_DDR_32BIT
  172 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
  173 +#else
172 174 #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
  175 +#endif
173 176  
174 177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
175 178 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR