Eric Lee / smarc-uboot

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Commit b37b7b2063e02718970ca1882a4522ccbe1106e9

Authored by Bin Meng
1 parent 7bb6028768
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: Switch to use DM sysreset driver 

This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Showing 31 changed files with 41 additions and 66 deletions Side-by-side Diff

... ... @@ -118,6 +118,8 @@
118 118 imply DM_SPI_FLASH
119 119 imply DM_USB
120 120 imply DM_VIDEO
  121 + imply SYSRESET
  122 + imply SYSRESET_X86
121 123 imply CMD_FPGA_LOADMK
122 124 imply CMD_GETTIME
123 125 imply CMD_IO
arch/x86/cpu/baytrail/valleyview.c
Diff comments   View file @ b37b7b2
... ... @@ -55,10 +55,4 @@
55 55  
56 56 return 0;
57 57 }
58   -
59   -void reset_cpu(ulong addr)
60   -{
61   - /* cold reset */
62   - x86_full_reset();
63   -}
arch/x86/cpu/braswell/braswell.c
Diff comments   View file @ b37b7b2
... ... @@ -27,10 +27,4 @@
27 27  
28 28 return 0;
29 29 }
30   -
31   -void reset_cpu(ulong addr)
32   -{
33   - /* cold reset */
34   - x86_full_reset();
35   -}
... ... @@ -75,35 +75,9 @@
75 75 }
76 76 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
77 77  
78   -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
79   -{
80   - printf("resetting ...\n");
81   -
82   - /* wait 50 ms */
83   - udelay(50000);
84   - disable_interrupts();
85   - reset_cpu(0);
86   -
87   - /*NOTREACHED*/
88   - return 0;
89   -}
90   -
91 78 void flush_cache(unsigned long dummy1, unsigned long dummy2)
92 79 {
93 80 asm("wbinvd\n");
94   -}
95   -
96   -__weak void reset_cpu(ulong addr)
97   -{
98   - /* Do a hard reset through the chipset's reset control register */
99   - outb(SYS_RST | RST_CPU, IO_PORT_RESET);
100   - for (;;)
101   - cpu_hlt();
102   -}
103   -
104   -void x86_full_reset(void)
105   -{
106   - outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
107 81 }
108 82  
109 83 /* Define these functions to allow ehch-hcd to function */
arch/x86/cpu/ivybridge/early_me.c
Diff comments   View file @ b37b7b2
... ... @@ -8,6 +8,7 @@
8 8 #include <common.h>
9 9 #include <dm.h>
10 10 #include <errno.h>
  11 +#include <sysreset.h>
11 12 #include <asm/pci.h>
12 13 #include <asm/cpu.h>
13 14 #include <asm/processor.h>
14 15  
15 16  
... ... @@ -138,17 +139,17 @@
138 139 case ME_HFS_ACK_RESET:
139 140 /* Non-power cycle reset */
140 141 set_global_reset(dev, 0);
141   - reset_cpu(0);
  142 + sysreset_walk_halt(SYSRESET_COLD);
142 143 break;
143 144 case ME_HFS_ACK_PWR_CYCLE:
144 145 /* Power cycle reset */
145 146 set_global_reset(dev, 0);
146   - x86_full_reset();
  147 + sysreset_walk_halt(SYSRESET_COLD);
147 148 break;
148 149 case ME_HFS_ACK_GBL_RESET:
149 150 /* Global reset */
150 151 set_global_reset(dev, 1);
151   - x86_full_reset();
  152 + sysreset_walk_halt(SYSRESET_COLD);
152 153 break;
153 154 case ME_HFS_ACK_S3:
154 155 case ME_HFS_ACK_S4:
arch/x86/cpu/ivybridge/sdram.c
Diff comments   View file @ b37b7b2
... ... @@ -18,6 +18,7 @@
18 18 #include <spi.h>
19 19 #include <spi_flash.h>
20 20 #include <syscon.h>
  21 +#include <sysreset.h>
21 22 #include <asm/cpu.h>
22 23 #include <asm/processor.h>
23 24 #include <asm/gpio.h>
... ... @@ -497,7 +498,7 @@
497 498 /* If MRC data is not found we cannot continue S3 resume. */
498 499 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
499 500 debug("Giving up in sdram_initialize: No MRC data\n");
500   - reset_cpu(0);
  501 + sysreset_walk_halt(SYSRESET_COLD);
501 502 }
502 503  
503 504 /* Pass console handler in pei_data */
arch/x86/cpu/qemu/qemu.c
Diff comments   View file @ b37b7b2
... ... @@ -156,12 +156,6 @@
156 156 }
157 157 #endif
158 158  
159   -void reset_cpu(ulong addr)
160   -{
161   - /* cold reset */
162   - x86_full_reset();
163   -}
164   -
165 159 int arch_early_init_r(void)
166 160 {
167 161 qemu_chipset_init();
arch/x86/cpu/quark/quark.c
Diff comments   View file @ b37b7b2
... ... @@ -270,12 +270,6 @@
270 270 return default_print_cpuinfo();
271 271 }
272 272  
273   -void reset_cpu(ulong addr)
274   -{
275   - /* cold reset */
276   - x86_full_reset();
277   -}
278   -
279 273 static void quark_pcie_init(void)
280 274 {
281 275 u32 val;
arch/x86/cpu/tangier/tangier.c
Diff comments   View file @ b37b7b2
... ... @@ -4,7 +4,6 @@
4 4 */
5 5  
6 6 #include <common.h>
7   -#include <asm/scu.h>
8 7 #include <asm/u-boot-x86.h>
9 8  
10 9 /*
... ... @@ -23,10 +22,5 @@
23 22 int print_cpuinfo(void)
24 23 {
25 24 return default_print_cpuinfo();
26   -}
27   -
28   -void reset_cpu(ulong addr)
29   -{
30   - scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
31 25 }
arch/x86/dts/bayleybay.dts
Diff comments   View file @ b37b7b2
... ... @@ -12,6 +12,7 @@
12 12 /include/ "skeleton.dtsi"
13 13 /include/ "keyboard.dtsi"
14 14 /include/ "serial.dtsi"
  15 +/include/ "reset.dtsi"
15 16 /include/ "rtc.dtsi"
16 17 /include/ "tsc_timer.dtsi"
17 18 /include/ "coreboot_fb.dtsi"
arch/x86/dts/baytrail_som-db5800-som-6867.dts
Diff comments   View file @ b37b7b2
... ... @@ -12,6 +12,7 @@
12 12  
13 13 /include/ "skeleton.dtsi"
14 14 /include/ "serial.dtsi"
  15 +/include/ "reset.dtsi"
15 16 /include/ "rtc.dtsi"
16 17 /include/ "tsc_timer.dtsi"
17 18  
arch/x86/dts/broadwell_som-6896.dts
Diff comments   View file @ b37b7b2
... ... @@ -2,6 +2,7 @@
2 2  
3 3 /include/ "skeleton.dtsi"
4 4 /include/ "serial.dtsi"
  5 +/include/ "reset.dtsi"
5 6 /include/ "rtc.dtsi"
6 7 /include/ "tsc_timer.dtsi"
7 8 /include/ "coreboot_fb.dtsi"
arch/x86/dts/cherryhill.dts
Diff comments   View file @ b37b7b2
... ... @@ -10,6 +10,7 @@
10 10  
11 11 /include/ "skeleton.dtsi"
12 12 /include/ "serial.dtsi"
  13 +/include/ "reset.dtsi"
13 14 /include/ "rtc.dtsi"
14 15 /include/ "tsc_timer.dtsi"
15 16  
arch/x86/dts/chromebook_link.dts
Diff comments   View file @ b37b7b2
... ... @@ -5,6 +5,7 @@
5 5 /include/ "skeleton.dtsi"
6 6 /include/ "keyboard.dtsi"
7 7 /include/ "serial.dtsi"
  8 +/include/ "reset.dtsi"
8 9 /include/ "rtc.dtsi"
9 10 /include/ "tsc_timer.dtsi"
10 11 /include/ "coreboot_fb.dtsi"
arch/x86/dts/chromebook_samus.dts
Diff comments   View file @ b37b7b2
... ... @@ -5,6 +5,7 @@
5 5 /include/ "skeleton.dtsi"
6 6 /include/ "keyboard.dtsi"
7 7 /include/ "serial.dtsi"
  8 +/include/ "reset.dtsi"
8 9 /include/ "rtc.dtsi"
9 10 /include/ "tsc_timer.dtsi"
10 11 /include/ "coreboot_fb.dtsi"
arch/x86/dts/chromebox_panther.dts
Diff comments   View file @ b37b7b2
... ... @@ -2,6 +2,7 @@
2 2  
3 3 /include/ "skeleton.dtsi"
4 4 /include/ "serial.dtsi"
  5 +/include/ "reset.dtsi"
5 6 /include/ "rtc.dtsi"
6 7 /include/ "tsc_timer.dtsi"
7 8 /include/ "coreboot_fb.dtsi"
arch/x86/dts/conga-qeval20-qa3-e3845.dts
Diff comments   View file @ b37b7b2
... ... @@ -12,6 +12,7 @@
12 12  
13 13 /include/ "skeleton.dtsi"
14 14 /include/ "serial.dtsi"
  15 +/include/ "reset.dtsi"
15 16 /include/ "rtc.dtsi"
16 17 /include/ "tsc_timer.dtsi"
17 18  
arch/x86/dts/cougarcanyon2.dts
Diff comments   View file @ b37b7b2
... ... @@ -10,6 +10,7 @@
10 10 /include/ "skeleton.dtsi"
11 11 /include/ "serial.dtsi"
12 12 /include/ "keyboard.dtsi"
  13 +/include/ "reset.dtsi"
13 14 /include/ "rtc.dtsi"
14 15 /include/ "tsc_timer.dtsi"
15 16  
arch/x86/dts/crownbay.dts
Diff comments   View file @ b37b7b2
... ... @@ -10,6 +10,7 @@
10 10 /include/ "skeleton.dtsi"
11 11 /include/ "serial.dtsi"
12 12 /include/ "keyboard.dtsi"
  13 +/include/ "reset.dtsi"
13 14 /include/ "rtc.dtsi"
14 15 /include/ "tsc_timer.dtsi"
15 16  
arch/x86/dts/dfi-bt700.dtsi
Diff comments   View file @ b37b7b2
... ... @@ -9,6 +9,7 @@
9 9 #include <dt-bindings/interrupt-router/intel-irq.h>
10 10  
11 11 #include "skeleton.dtsi"
  12 +#include "reset.dtsi"
12 13 #include "rtc.dtsi"
13 14 #include "tsc_timer.dtsi"
14 15  
arch/x86/dts/edison.dts
Diff comments   View file @ b37b7b2
... ... @@ -85,5 +85,10 @@
85 85 compatible = "intel,scu-ipc";
86 86 reg = <0xff009000 0x1000>;
87 87 };
  88 +
  89 + reset {
  90 + compatible = "intel,reset-tangier";
  91 + u-boot,dm-pre-reloc;
  92 + };
88 93 };
arch/x86/dts/efi-x86_app.dts
Diff comments   View file @ b37b7b2
... ... @@ -23,5 +23,10 @@
23 23 serial: serial {
24 24 compatible = "efi,uart";
25 25 };
  26 +
  27 + reset {
  28 + compatible = "efi,reset";
  29 + u-boot,dm-pre-reloc;
  30 + };
26 31 };
arch/x86/dts/efi-x86_payload.dts
Diff comments   View file @ b37b7b2
... ... @@ -10,6 +10,7 @@
10 10 /include/ "skeleton.dtsi"
11 11 /include/ "serial.dtsi"
12 12 /include/ "keyboard.dtsi"
  13 +/include/ "reset.dtsi"
13 14 /include/ "rtc.dtsi"
14 15 /include/ "tsc_timer.dtsi"
15 16  
arch/x86/dts/galileo.dts
Diff comments   View file @ b37b7b2
... ... @@ -9,6 +9,7 @@
9 9 #include <dt-bindings/interrupt-router/intel-irq.h>
10 10  
11 11 /include/ "skeleton.dtsi"
  12 +/include/ "reset.dtsi"
12 13 /include/ "rtc.dtsi"
13 14 /include/ "tsc_timer.dtsi"
14 15  
arch/x86/dts/minnowmax.dts
Diff comments   View file @ b37b7b2
... ... @@ -11,6 +11,7 @@
11 11  
12 12 /include/ "skeleton.dtsi"
13 13 /include/ "serial.dtsi"
  14 +/include/ "reset.dtsi"
14 15 /include/ "rtc.dtsi"
15 16 /include/ "tsc_timer.dtsi"
16 17 /include/ "coreboot_fb.dtsi"
arch/x86/dts/qemu-x86_i440fx.dts
Diff comments   View file @ b37b7b2
... ... @@ -10,6 +10,7 @@
10 10 /include/ "skeleton.dtsi"
11 11 /include/ "serial.dtsi"
12 12 /include/ "keyboard.dtsi"
  13 +/include/ "reset.dtsi"
13 14 /include/ "rtc.dtsi"
14 15 /include/ "tsc_timer.dtsi"
15 16  
arch/x86/dts/qemu-x86_q35.dts
Diff comments   View file @ b37b7b2
... ... @@ -20,6 +20,7 @@
20 20 /include/ "skeleton.dtsi"
21 21 /include/ "serial.dtsi"
22 22 /include/ "keyboard.dtsi"
  23 +/include/ "reset.dtsi"
23 24 /include/ "rtc.dtsi"
24 25 /include/ "tsc_timer.dtsi"
25 26  
arch/x86/dts/reset.dtsi
Diff comments   View file @ b37b7b2
  1 +/ {
  2 + reset {
  3 + compatible = "x86,reset";
  4 + u-boot,dm-pre-reloc;
  5 + };
  6 +};
arch/x86/include/asm/processor.h
Diff comments   View file @ b37b7b2
... ... @@ -43,11 +43,6 @@
43 43 FULL_RST = 1 << 3, /* full power cycle */
44 44 };
45 45  
46   -/**
47   - * x86_full_reset() - reset everything: perform a full power cycle
48   - */
49   -void x86_full_reset(void);
50   -
51 46 static inline __attribute__((always_inline)) void cpu_hlt(void)
52 47 {
53 48 asm("hlt");
arch/x86/include/asm/u-boot-x86.h
Diff comments   View file @ b37b7b2
... ... @@ -40,7 +40,6 @@
40 40 void x86_enable_caches(void);
41 41 void x86_disable_caches(void);
42 42 int x86_init_cache(void);
43   -void reset_cpu(ulong addr);
44 43 ulong board_get_usable_ram_top(ulong total_size);
45 44 int default_print_cpuinfo(void);
46 45  
configs/chromebook_link64_defconfig
Diff comments   View file @ b37b7b2
... ... @@ -4,6 +4,7 @@
4 4 CONFIG_SPL_LIBGENERIC_SUPPORT=y
5 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
6 6 CONFIG_SPL_SERIAL_SUPPORT=y
  7 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
7 8 CONFIG_DEBUG_UART_BOARD_INIT=y
8 9 CONFIG_DEBUG_UART_BASE=0x3f8
9 10 CONFIG_DEBUG_UART_CLOCK=1843200