net: gmac_rockchip: Add rk3328 gmac support

The GMAC2IO in the RK3328 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3328-specific logic necessary to reuse this driver. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

net: gmac_rockchip: Add rk3328 gmac support
The GMAC2IO in the RK3328 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3328-specific logic necessary to reuse this driver. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu · Philipp Tomsich
1 parent 7cd4ebab2b
Showing 1 changed file with 85 additions and 0 deletions Side-by-side Diff
drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/grf_rv1108.h>
@@ -94,6 +95,39 @@
 	return 0;
 }
  
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3328_grf_regs *grf;
+	int clk;
+	enum {
+		RK3328_GMAC_CLK_SEL_SHIFT = 11,
+		RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
+		RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
+		RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
+		RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3328_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3328_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3328_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3368_grf *grf;
@@ -207,6 +241,50 @@
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
  
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3328_grf_regs *grf;
+	enum {
+		RK3328_RMII_MODE_SHIFT = 9,
+		RK3328_RMII_MODE_MASK  = BIT(9),
+
+		RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+		RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+		RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+		RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+		RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+		RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+		RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+	};
+	enum {
+		RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+		RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+		RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+		RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1],
+		     RK3328_RMII_MODE_MASK |
+		     RK3328_GMAC_PHY_INTF_SEL_MASK |
+		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
+		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+	rk_clrsetreg(&grf->mac_con[0],
+		     RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+		     pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3368_grf *grf;
@@ -375,6 +453,11 @@
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
  
+const struct rk_gmac_ops rk3328_gmac_ops = {
+	.fix_mac_speed = rk3328_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3368_gmac_ops = {
 	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -393,6 +476,8 @@
 static const struct udevice_id rockchip_gmac_ids[] = {
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3328-gmac",
+	  .data = (ulong)&rk3328_gmac_ops },
 	{ .compatible = "rockchip,rk3368-gmac",
 	  .data = (ulong)&rk3368_gmac_ops },
 	{ .compatible = "rockchip,rk3399-gmac",
...	...	@@ -16,6 +16,7 @@
16	16	#include <asm/arch/clock.h>
17	17	#include <asm/arch/hardware.h>
18	18	#include <asm/arch/grf_rk3288.h>
	19	+#include <asm/arch/grf_rk3328.h>
19	20	#include <asm/arch/grf_rk3368.h>
20	21	#include <asm/arch/grf_rk3399.h>
21	22	#include <asm/arch/grf_rv1108.h>
...	...	@@ -94,6 +95,39 @@
94	95	return 0;
95	96	}
96	97
	98	+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
	99	+{
	100	+ struct rk3328_grf_regs *grf;
	101	+ int clk;
	102	+ enum {
	103	+ RK3328_GMAC_CLK_SEL_SHIFT = 11,
	104	+ RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
	105	+ RK3328_GMAC_CLK_SEL_125M = 0 << 11,
	106	+ RK3328_GMAC_CLK_SEL_25M = 3 << 11,
	107	+ RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
	108	+ };
	109	+
	110	+ switch (priv->phydev->speed) {
	111	+ case 10:
	112	+ clk = RK3328_GMAC_CLK_SEL_2_5M;
	113	+ break;
	114	+ case 100:
	115	+ clk = RK3328_GMAC_CLK_SEL_25M;
	116	+ break;
	117	+ case 1000:
	118	+ clk = RK3328_GMAC_CLK_SEL_125M;
	119	+ break;
	120	+ default:
	121	+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
	122	+ return -EINVAL;
	123	+ }
	124	+
	125	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	126	+ rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
	127	+
	128	+ return 0;
	129	+}
	130	+
97	131	static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
98	132	{
99	133	struct rk3368_grf *grf;
...	...	@@ -207,6 +241,50 @@
207	241	pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
208	242	}
209	243
	244	+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	245	+{
	246	+ struct rk3328_grf_regs *grf;
	247	+ enum {
	248	+ RK3328_RMII_MODE_SHIFT = 9,
	249	+ RK3328_RMII_MODE_MASK = BIT(9),
	250	+
	251	+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
	252	+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
	253	+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
	254	+
	255	+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
	256	+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
	257	+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
	258	+
	259	+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
	260	+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
	261	+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
	262	+ };
	263	+ enum {
	264	+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
	265	+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
	266	+
	267	+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
	268	+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
	269	+ };
	270	+
	271	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	272	+ rk_clrsetreg(&grf->mac_con[1],
	273	+ RK3328_RMII_MODE_MASK \|
	274	+ RK3328_GMAC_PHY_INTF_SEL_MASK \|
	275	+ RK3328_RXCLK_DLY_ENA_GMAC_MASK \|
	276	+ RK3328_TXCLK_DLY_ENA_GMAC_MASK,
	277	+ RK3328_GMAC_PHY_INTF_SEL_RGMII \|
	278	+ RK3328_RXCLK_DLY_ENA_GMAC_MASK \|
	279	+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
	280	+
	281	+ rk_clrsetreg(&grf->mac_con[0],
	282	+ RK3328_CLK_RX_DL_CFG_GMAC_MASK \|
	283	+ RK3328_CLK_TX_DL_CFG_GMAC_MASK,
	284	+ pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT \|
	285	+ pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
	286	+}
	287	+
210	288	static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
211	289	{
212	290	struct rk3368_grf *grf;
...	...	@@ -375,6 +453,11 @@
375	453	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
376	454	};
377	455
	456	+const struct rk_gmac_ops rk3328_gmac_ops = {
	457	+ .fix_mac_speed = rk3328_gmac_fix_mac_speed,
	458	+ .set_to_rgmii = rk3328_gmac_set_to_rgmii,
	459	+};
	460	+
378	461	const struct rk_gmac_ops rk3368_gmac_ops = {
379	462	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
380	463	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
...	...	@@ -393,6 +476,8 @@
393	476	static const struct udevice_id rockchip_gmac_ids[] = {
394	477	{ .compatible = "rockchip,rk3288-gmac",
395	478	.data = (ulong)&rk3288_gmac_ops },
	479	+ { .compatible = "rockchip,rk3328-gmac",
	480	+ .data = (ulong)&rk3328_gmac_ops },
396	481	{ .compatible = "rockchip,rk3368-gmac",
397	482	.data = (ulong)&rk3368_gmac_ops },
398	483	{ .compatible = "rockchip,rk3399-gmac",