Commit b3dd629e78870ba2dc9f8032978721c0fa02a856
1 parent
e05825324a
Exists in
master
and in
54 other branches
Prepare 2009.03-rc2
Update CHANEGLOG, fix minor coding style issue. Signed-off-by: Wolfgang Denk <wd@denx.de>
Showing 2 changed files with 755 additions and 2 deletions Side-by-side Diff
CHANGELOG
1 | +commit 394d30dd1ee23b80fd5e59e17ebe0feca927ab31 | |
2 | +Author: Jerry Van Baren <gvb.uboot@gmail.com> | |
3 | +Date: Fri Mar 13 11:40:10 2009 -0400 | |
4 | + | |
5 | + mpc83xx: Add bank configuration to FSL spd_sdram.c | |
6 | + | |
7 | + The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 | |
8 | + bank SDRAMs. | |
9 | + | |
10 | + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> | |
11 | + Acked-by: Dave Liu <daveliu@freescale.com> | |
12 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
13 | + | |
14 | +commit b581626c1e2474a3dadf69d4f0e0582eccbc4235 | |
15 | +Author: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> | |
16 | +Date: Fri Mar 13 08:58:14 2009 +0100 | |
17 | + | |
18 | + mpc83xx: correctly set encryption and I2C bus 0 clock | |
19 | + | |
20 | + This patch makes sure the correct mask is applied when setting | |
21 | + the encryption and I2C bus 0 clock in SCCR. | |
22 | + Failing to do so may lead to ENCCM being 0 in which case I2C bus 0 | |
23 | + won't function. | |
24 | + | |
25 | + Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> | |
26 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
27 | + | |
28 | +commit e6a6a704151c2d7e4a7b485545b48a6020ccca17 | |
29 | +Author: Dirk Behme <dirk.behme@googlemail.com> | |
30 | +Date: Thu Mar 12 19:30:50 2009 +0100 | |
31 | + | |
32 | + OMAP3: Add support for OMAP3 die ID | |
33 | + | |
34 | + Read and store OMAP3 die ID in U-Boot environment. | |
35 | + | |
36 | + Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> | |
37 | + | |
38 | +commit f949bd8d089ec3059c460ac829c0d919e1d7af0e | |
39 | +Author: Jon Smirl <jonsmirl@gmail.com> | |
40 | +Date: Wed Mar 11 15:08:56 2009 -0400 | |
41 | + | |
42 | + MPC5200 FEC MII speed register | |
43 | + | |
44 | + Set a non-zero speed in the MII register so that MII commands will work. | |
45 | + | |
46 | + Signed-off-by: Jon Smirl <jonsmirl@gmail.com> | |
47 | + | |
48 | +commit 94a353611b93ac4cb4434a5f7e98aa0902da919e | |
49 | +Author: Yusuke.Goda <goda.yusuke@renesas.com> | |
50 | +Date: Fri Mar 13 16:08:18 2009 +0900 | |
51 | + | |
52 | + sh: ap325rxa: Change the wait cycle in the area 5 | |
53 | + | |
54 | + Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> | |
55 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
56 | + | |
57 | +commit 2db0e1278b9f11263e0a13326b57d4f99781f7ac | |
58 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
59 | +Date: Wed Feb 25 16:04:26 2009 +0900 | |
60 | + | |
61 | + sh: Fix cannot work rtl8139 on r2dplus | |
62 | + | |
63 | + The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory | |
64 | + registration. | |
65 | + | |
66 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
67 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
68 | + | |
69 | +commit 64f3c0b8ba99d6651db59273e497ab5e857c8d4f | |
70 | +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
71 | +Date: Fri Feb 27 18:35:41 2009 +0900 | |
72 | + | |
73 | + sh: Add netdev header fixing of warning/build | |
74 | + | |
75 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
76 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
77 | + | |
78 | +commit ada9318252f51c2626e9837c623f9812b0308dea | |
79 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
80 | +Date: Tue Mar 3 15:11:17 2009 +0900 | |
81 | + | |
82 | + sh: Add support 32-Bit Extended Address Mode to sh7785lcr | |
83 | + | |
84 | + We can built 'make sh7785lcr_32bit_config'. And add new command "pmb" | |
85 | + for this mode. This command changes PMB for using 512MB system memory. | |
86 | + | |
87 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
88 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
89 | + | |
90 | +commit 06b18163b57e6b0349b0c299222d50e7b1e41e50 | |
91 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
92 | +Date: Wed Feb 25 14:26:42 2009 +0900 | |
93 | + | |
94 | + sh: Add some register value configurable to PCI of SH7780 | |
95 | + | |
96 | + Some register value was hardcoded for System memory size 128MB and | |
97 | + memory offset 0x08000000. This patch fixed the problem. | |
98 | + | |
99 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
100 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
101 | + | |
102 | +commit 06e2735eb85cbea7cecb3c308d6d078b3651b22c | |
103 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
104 | +Date: Wed Feb 25 14:26:52 2009 +0900 | |
105 | + | |
106 | + sh: Add system memory registration to PCI for SH4 | |
107 | + | |
108 | + It is necessary for some pci device driver. | |
109 | + | |
110 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
111 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
112 | + | |
113 | +commit b3061b40db691245a7bb9a55354b4edacbf3902d | |
114 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
115 | +Date: Wed Feb 25 14:26:55 2009 +0900 | |
116 | + | |
117 | + sh: Add value for PCI system memory registration of sh7785lcr | |
118 | + | |
119 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
120 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
121 | + | |
122 | +commit 6d84ae3956a6cd7aebd86f661130752594e60124 | |
123 | +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
124 | +Date: Tue Mar 3 15:11:08 2009 +0900 | |
125 | + | |
126 | + sh: Add macros for SH-4A 32-Bit Address Extended Mode | |
127 | + | |
128 | + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
129 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
130 | + | |
131 | +commit 3e3eec39de8fe0ae62e6e4d4e3fa4442ee9ed6b1 | |
132 | +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
133 | +Date: Tue Feb 3 13:35:05 2009 +0900 | |
134 | + | |
135 | + sh: use write{8,16,32} in ms7720se lowlevel_init | |
136 | + | |
137 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
138 | + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
139 | + | |
140 | +commit 0452352df118bc9dd684a056aaaa5fb4aed1178a | |
141 | +Author: Paul Gortmaker <paul.gortmaker@windriver.com> | |
142 | +Date: Mon Mar 9 18:07:53 2009 -0500 | |
143 | + | |
144 | + tsec: report when there is no vendor specific PHY support | |
145 | + | |
146 | + Commit af1c2b84 added a generic phy support, with an ID of zero | |
147 | + and a 32 bit mask; meaning that it will match on any PHY ID. | |
148 | + | |
149 | + The problem is that there is a test that checked if a matching | |
150 | + PHY was found, and if not, it printed the non-matching ID. | |
151 | + But since there will always be a match (on the generic PHY, | |
152 | + worst case), this test will never trip. | |
153 | + | |
154 | + In the case of a misconfigured PHY address, or of a PHY that | |
155 | + isn't explicitly supported outside of the generic support, | |
156 | + you will never see the ID of 0xffffffff, or the ID of the | |
157 | + real (but unsupported) chip. It will silently fall through | |
158 | + onto the generic support. | |
159 | + | |
160 | + This change makes that test useful again, and ensures that | |
161 | + the selection of generic PHY support doesn't happen without | |
162 | + some sort of notice. It also makes it explicitly clear that | |
163 | + the generic PHY must be last in the PHY table. | |
164 | + | |
165 | + Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> | |
166 | + Acked-by: Andy Fleming <afleming@freescale.com> | |
167 | + | |
168 | +commit c279dfc10186ceba78d3862036f158750e86599a | |
169 | +Author: Wolfgang Denk <wd@denx.de> | |
170 | +Date: Mon Mar 9 10:53:05 2009 +0100 | |
171 | + | |
172 | + SIMPC8313 board: fix out of tree building. | |
173 | + | |
174 | + Fix typo in makefile which broke out of tree builds. | |
175 | + | |
176 | + Also use expolicit "rm" instead of "ln -sf" which is known to be | |
177 | + unreliable. | |
178 | + | |
179 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
180 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
181 | + | |
182 | +commit 49b5aff491bd574935ecaf8545152066a25eff3d | |
183 | +Author: ksi@koi8.net <ksi@koi8.net> | |
184 | +Date: Mon Feb 23 10:53:13 2009 -0800 | |
185 | + | |
186 | + Add eTSEC 1/2 IO override control (corrected) | |
187 | + | |
188 | + This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) | |
189 | + | |
190 | + Signed-off-by: Sergey Kubushyn <ksi@koi8.net> | |
191 | + | |
192 | +commit 48c2b7bb432da84fcce05b4db6efad0be73a93dc | |
193 | +Author: Andy Fleming <afleming@freescale.com> | |
194 | +Date: Fri Mar 6 19:05:52 2009 -0600 | |
195 | + | |
196 | + fsl: Remove unnecessary debug printfs | |
197 | + | |
198 | + These were left in accidentally, and are not really useful unless the | |
199 | + code is as broken as it was when it was being developed. | |
200 | + | |
201 | + Signed-off-by: Andy Fleming <afleming@freescale.com> | |
202 | + | |
203 | +commit 0ee84b88b78bce425190d8cd7adf4c30cba0c2f0 | |
204 | +Author: Ed Swarthout <Ed.Swarthout@freescale.com> | |
205 | +Date: Tue Feb 24 02:37:59 2009 -0600 | |
206 | + | |
207 | + Fix mpc85xx ddr-gen3 ddr_sdram_cfg. | |
208 | + | |
209 | + Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other | |
210 | + sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. | |
211 | + | |
212 | + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> | |
213 | + | |
214 | +commit a922fdb87af25c25c032424908dcf60fbf3250ea | |
215 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
216 | +Date: Tue Feb 24 06:13:10 2009 +0100 | |
217 | + | |
218 | + PXA: timer use do_div and simplify it | |
219 | + | |
220 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
221 | + | |
222 | +commit 4b00d1aa82b6af9b4e628a5729a12086e44558b3 | |
223 | +Author: Wolfgang Denk <wd@denx.de> | |
224 | +Date: Mon Mar 9 10:51:39 2009 +0100 | |
225 | + | |
226 | + SIMPC8313 board: fix out of tree building. | |
227 | + | |
228 | + Fix typo in makefile which broke out of tree builds. | |
229 | + | |
230 | + Also use expolicit "rm" instead of "ln -sf" which is known to be | |
231 | + unreliable. | |
232 | + | |
233 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
234 | + | |
235 | +commit f70fd13e2fe4cf58e251271c27f9c06e141d7f9a | |
236 | +Author: Heiko Schocher <hs@denx.de> | |
237 | +Date: Tue Feb 24 11:30:51 2009 +0100 | |
238 | + | |
239 | + 8360, kmeter1: added bootcount feature. | |
240 | + | |
241 | + add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU. | |
242 | + | |
243 | + The bootcounter uses 8 bytes from the muram, | |
244 | + because no other memory was found on this | |
245 | + CPU for the bootcount feature. So we must | |
246 | + correct the muram size in DTS before booting | |
247 | + Linux. | |
248 | + | |
249 | + This feature is actual only implemented for | |
250 | + MPC8360, because not all 83xx CPU have qe, | |
251 | + and therefore no muram, which this feature | |
252 | + uses. | |
253 | + | |
254 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
255 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
256 | + | |
257 | +commit 1e7ed2565031e01abc18c713030a0a9829c07684 | |
258 | +Author: Heiko Schocher <hs@denx.de> | |
259 | +Date: Tue Feb 24 11:30:48 2009 +0100 | |
260 | + | |
261 | + 83xx, kmeter: QE_ENET10 errata for Silicon Revision 2.1 | |
262 | + | |
263 | + old code implemented the QE_ENET10 errata only for Silicon | |
264 | + Revision 2.0. New code reads now the Silicon Revision | |
265 | + register and sets dependend on the Silicon Revision the | |
266 | + values as advised in the QE_ENET10 errata. | |
267 | + | |
268 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
269 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
270 | + | |
271 | +commit 605f78e34a3f0103693b891f2573edd352e7d495 | |
272 | +Author: Heiko Schocher <hs@denx.de> | |
273 | +Date: Tue Feb 24 11:30:44 2009 +0100 | |
274 | + | |
275 | + 83xx, kmeter1: updates for 2009.03 | |
276 | + | |
277 | + - HRCW update | |
278 | + HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL | |
279 | + HRCWH_LALE_EARLY added | |
280 | + - DDR-SDRAM settings modified. This solves sporadically | |
281 | + problems with this memory. | |
282 | + - CS1 now 128 MB window size | |
283 | + - CS3 now 512 MB window size | |
284 | + - PRAM activated | |
285 | + - MTDPARTS_DEFAULT defined | |
286 | + - CONFIG_HOSTNAME added | |
287 | + - MONITOR_LEN now 384 KB | |
288 | + | |
289 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
290 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
291 | + | |
292 | +commit 118cbe3c35c898f8d020b29d6dc180307cacf147 | |
293 | +Author: Heiko Schocher <hs@denx.de> | |
294 | +Date: Tue Feb 24 11:30:40 2009 +0100 | |
295 | + | |
296 | + 83xx, kmeter1: autodetect size of DDR II RAM | |
297 | + | |
298 | + it is possible that some board variants have different DDR II | |
299 | + RAM sizes. So we autodetect the size of the assembled RAM. | |
300 | + | |
301 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
302 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
303 | + | |
304 | +commit c1bce4fff750d734b1fa7467eb08f93902c97ca6 | |
305 | +Author: Heiko Schocher <hs@denx.de> | |
306 | +Date: Tue Feb 24 11:30:37 2009 +0100 | |
307 | + | |
308 | + 83xx, i2c: add mux support for fsl_i2c | |
309 | + | |
310 | + This patch adds I2C mux support for the fsl_i2c driver. This | |
311 | + allows you to add "new" i2c busses, which are reached over | |
312 | + i2c muxes. For more infos, please look in the README and | |
313 | + search for CONFIG_I2C_MUX. | |
314 | + | |
315 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
316 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
317 | + | |
318 | +commit 19f0e93041dbfe22f8d39b98e4f7f9ea87b77803 | |
319 | +Author: Heiko Schocher <hs@denx.de> | |
320 | +Date: Tue Feb 24 11:30:34 2009 +0100 | |
321 | + | |
322 | + 83xx, kmeter1: add I2C, dtt, eeprom support | |
323 | + | |
324 | + This patch adds I2C support for the Keymile kmeter1 board. | |
325 | + It uses the First I2C Controller from the CPU, for | |
326 | + accessing 4 temperature sensors, an eeprom with IVM data | |
327 | + and the booteeprom over a pca9547 mux. | |
328 | + | |
329 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
330 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
331 | + | |
332 | +commit db1d72afd77287bc8577210f3f71ab249dcf146f | |
333 | +Author: Heiko Schocher <hs@denx.de> | |
334 | +Date: Tue Feb 24 11:30:30 2009 +0100 | |
335 | + | |
336 | + i2c, dtt: move dtt_init () to board_init_r () | |
337 | + | |
338 | + In case where a board not uses CONFIG_POST, it is not | |
339 | + necessary to init the DTTs when running from flash. | |
340 | + | |
341 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
342 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
343 | + | |
344 | +commit 5b0055547f0246908b79cc300170d87380b69e18 | |
345 | +Author: Dave Liu <daveliu@freescale.com> | |
346 | +Date: Wed Feb 25 12:31:32 2009 +0800 | |
347 | + | |
348 | + 83xx: Fix some bugs in spd sdram code | |
349 | + | |
350 | + 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for | |
351 | + tRTP according to DDR2 JEDEC spec. | |
352 | + 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. | |
353 | + 3. add the support of DDR2-533,667,800 DIMMs | |
354 | + 4. cpo | |
355 | + 5. make the AL to min to gain better performance. | |
356 | + | |
357 | + The Micron MT9HTF6472CHY-667D1 DIMMs test passed on | |
358 | + MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. | |
359 | + | |
360 | + items 1, 2 and 5: | |
361 | + Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | |
362 | + | |
363 | + Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | |
364 | + Signed-off-by: Dave Liu <daveliu@freescale.com> | |
365 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
366 | + | |
367 | +commit b7be63abec45858c044f0fbd6aeef524c4663f9b | |
368 | +Author: Valeriy Glushkov <gvv@lstec.com> | |
369 | +Date: Wed Feb 4 18:27:49 2009 +0200 | |
370 | + | |
371 | + MPC8349ITX: several config issues fixed | |
372 | + | |
373 | + The previous version rebooted forever with DDR bigger than 256MB. | |
374 | + Access the DS1339 RTC chip is on I2C1 bus. | |
375 | + Allow DHCP. | |
376 | + | |
377 | + Signed-off-by: Valeriy Glushkov <gvv@lstec.com> | |
378 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
379 | + | |
380 | +commit 7e2ec1de1d2d723b59d7dd2fb85ff71b952d63af | |
381 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
382 | +Date: Thu Feb 19 18:20:39 2009 +0300 | |
383 | + | |
384 | + mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal | |
385 | + | |
386 | + The SerDes initialization should be finished before negating the reset | |
387 | + signal according to the reference manual. This isn't an issue on real | |
388 | + hardware, but we'd better stick to the specifications anyway. | |
389 | + | |
390 | + Suggested-by: Liu Dave <DaveLiu@freescale.com> | |
391 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
392 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
393 | + | |
394 | +commit 9c2d63ec0e9520948b6d598ea32e9aa4e0de847f | |
395 | +Author: Heiko Schocher <hs@denx.de> | |
396 | +Date: Wed Feb 25 12:28:32 2009 +0100 | |
397 | + | |
398 | + i2c, dtt: move dtt_init () to board_init_r () | |
399 | + | |
400 | + it is not necessary to init the DTTs so early, | |
401 | + so move this init to board_init_r (). | |
402 | + | |
403 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
404 | + | |
405 | +commit 00cc5595a7caac8066b408774383a956c2e26797 | |
406 | +Author: Anatolij Gustschin <agust@denx.de> | |
407 | +Date: Wed Feb 25 20:28:13 2009 +0100 | |
408 | + | |
409 | + lcd: Fix compilation warning in common/lcd.c | |
410 | + | |
411 | + Fix following warning while compilation for mcc200 board: | |
412 | + | |
413 | + lcd.c: In function 'lcd_display_bitmap': | |
414 | + lcd.c:625: warning: unused variable 'cmap' | |
415 | + | |
416 | + Signed-off-by: Anatolij Gustschin <agust@denx.de> | |
417 | + | |
418 | +commit f5a77a09c93fe7f04c0c56f64ea436f7d318d674 | |
419 | +Author: Graeme Russ <graeme.russ@gmail.com> | |
420 | +Date: Tue Feb 24 21:11:24 2009 +1100 | |
421 | + | |
422 | + Moved SC520 Files (fix commit 407976185e0dda2c90e89027121a1071b9c77bfb) | |
423 | + | |
424 | + Fixes commit 407976185e0dda2c90e89027121a1071b9c77bfb | |
425 | + | |
426 | + Signed-off-by: Graeme Russ <graeme.russ at gmail.com> | |
427 | + | |
428 | +commit 75ba6d693b8f6247aa4b81323a2ee2fa28222215 | |
429 | +Author: Mike Frysinger <vapier@gentoo.org> | |
430 | +Date: Mon Feb 23 10:29:47 2009 -0500 | |
431 | + | |
432 | + smc911x: split out useful defines/functions into local header | |
433 | + | |
434 | + The smc911x driver has a lot of useful defines/functions which can be used | |
435 | + by pieces of code (such as example eeprom programmers). Rather than | |
436 | + forcing each place to duplicate these defines/functions, split them out | |
437 | + of the smdc911x driver into a local header. | |
438 | + | |
439 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
440 | + Acked-by: Ben Warren <biggerbadderben@gmail.com> | |
441 | + CC: Sascha Hauer <s.hauer@pengutronix.de> | |
442 | + CC: Guennadi Liakhovetski <lg@denx.de> | |
443 | + CC: Magnus Lilja <lilja.magnus@gmail.com> | |
444 | + CC: Ben Warren <biggerbadderben@gmail.com> | |
445 | + | |
446 | +commit a2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1 | |
447 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
448 | +Date: Tue Feb 24 10:44:02 2009 +0100 | |
449 | + | |
450 | + ARM: add an "eet" variant of the imx31_phycore board | |
451 | + | |
452 | + The "eet" variant of the imx31_phycore board has an OLED display, using a | |
453 | + s6e63d6 display controller on the first SPI interface, using GPIO57 as a | |
454 | + chip-select for it. With this configuration you can display 256 colour BMP | |
455 | + images in 16-bit RGB (RGB565) LCD mode. | |
456 | + | |
457 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
458 | + Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
459 | + | |
460 | +commit 0c99f6ab31c5635874ba7a2e8d37791bfbf02f8f | |
461 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
462 | +Date: Fri Feb 6 10:37:57 2009 +0100 | |
463 | + | |
464 | + video: add an i.MX31 framebuffer driver | |
465 | + | |
466 | + Add a driver for the Synchronous Display Controller and the Display | |
467 | + Interface on i.MX31, using IPU for DMA channel setup. So far only | |
468 | + displaying of bitmaps is supported, no text output. | |
469 | + | |
470 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
471 | + Acked-by: Anatolij Gustschin <agust@denx.de> | |
472 | + | |
473 | +commit b245e65ee3c4cce3ccf008a21f4528239655876c | |
474 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
475 | +Date: Fri Feb 6 10:37:53 2009 +0100 | |
476 | + | |
477 | + LCD: support 8bpp BMPs on 16bpp displays | |
478 | + | |
479 | + This patch also simplifies some ifdefs in lcd.c, introduces a generic | |
480 | + vidinfo_t, which new drivers are encouraged to use and old drivers to switch | |
481 | + over to. | |
482 | + | |
483 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
484 | + Acked-by: Anatolij Gustschin <agust@denx.de> | |
485 | + | |
486 | +commit a303dfb0e9a93e516ea9427b5c09543d5f74ade1 | |
487 | +Author: Mark Jackson <mpfj@mimc.co.uk> | |
488 | +Date: Fri Feb 6 10:37:49 2009 +0100 | |
489 | + | |
490 | + Add 16bpp BMP support | |
491 | + | |
492 | + This patch adds 16bpp BMP support to the common lcd code. | |
493 | + | |
494 | + Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code. | |
495 | + | |
496 | + At the moment it's only been tested on the MIMC200 AVR32 board, but extending | |
497 | + this to other platforms should be a simple task !! | |
498 | + | |
499 | + Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> | |
500 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
501 | + Acked-by: Anatolij Gustschin <agust@denx.de> | |
502 | + | |
503 | +commit 689551c5ff1b394b88412f3df22144e79468d3a9 | |
504 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
505 | +Date: Fri Feb 6 10:37:41 2009 +0100 | |
506 | + | |
507 | + A driver for the S6E63D6 SPI display controller from Samsung | |
508 | + | |
509 | + This is a driver for the S6E63D6 SPI OLED display controller from Samsung. | |
510 | + It only provides access to controller's registers so the client can freely | |
511 | + configure it. | |
512 | + | |
513 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
514 | + Acked-by: Anatolij Gustschin <agust@denx.de> | |
515 | + | |
516 | +commit fc7a93c84f3f134484811a0d9ad751fbc1a7da6d | |
517 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
518 | +Date: Fri Feb 13 09:26:40 2009 +0100 | |
519 | + | |
520 | + i.MX31: support GPIO as a chip-select in the mxc_spi driver | |
521 | + | |
522 | + Some SPI devices have special requirements on chip-select handling. | |
523 | + With this patch we can use a GPIO as a chip-select and strictly follow | |
524 | + the SPI_XFER_BEGIN and SPI_XFER_END flags. | |
525 | + | |
526 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
527 | + Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
528 | + | |
529 | +commit b30de3cccf8867566cd314e7c7033904afa5dc9d | |
530 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
531 | +Date: Sat Feb 7 01:18:07 2009 +0100 | |
532 | + | |
533 | + i.MX31: add a simple gpio driver | |
534 | + | |
535 | + This is a minimal driver, so far only managing output. It will | |
536 | + be used by the mxc_spi.c driver. | |
537 | + | |
538 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
539 | + Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
540 | + | |
541 | +commit f9b6a1575d9f1ca192e4cb60e547aa66f08baa3f | |
542 | +Author: Guennadi Liakhovetski <lg@denx.de> | |
543 | +Date: Sat Feb 7 00:09:12 2009 +0100 | |
544 | + | |
545 | + i.MX31: fix SPI driver for shorter than 32 bit | |
546 | + | |
547 | + Fix setting the SPI Control register, 8 and 16-bit transfers | |
548 | + and a wrong pointer in the free routine in the mxc_spi driver. | |
549 | + | |
550 | + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> | |
551 | + Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
552 | + | |
553 | +commit 7e91558032a0c1932dd7f4f562f9c7cc55efc496 | |
554 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
555 | +Date: Thu Feb 19 18:20:52 2009 +0300 | |
556 | + | |
557 | + mpc83xx: MPC837XERDB: Add PCIe support | |
558 | + | |
559 | + On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe | |
560 | + slots. Let's support them. | |
561 | + | |
562 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
563 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
564 | + | |
565 | +commit 50a4d08e8f31debbd4ea12caf1265f3643c38d5b | |
566 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
567 | +Date: Thu Feb 19 18:20:50 2009 +0300 | |
568 | + | |
569 | + mpc83xx: PCI: Fix hard-coded first_busno value | |
570 | + | |
571 | + We should use pci_last_busno() in pci_init_bus(), otherwise we'll | |
572 | + erroneously re-use PCI0's first_busno for PCI1 hoses. | |
573 | + | |
574 | + NOTE: The patch is untested. All MPC83xx FSL boards I have have | |
575 | + PCI1 in miniPCI form, for which I don't have any cards handy. | |
576 | + | |
577 | + But looking in cpu/mpc85xx/pci.c: | |
578 | + ... | |
579 | + #ifdef CONFIG_MPC85XX_PCI2 | |
580 | + hose = &pci_hose[1]; | |
581 | + | |
582 | + hose->first_busno = pci_hose[0].last_busno + 1; | |
583 | + | |
584 | + And considering that we do the same for MPC83xx PCI-E support, | |
585 | + I think this patch is correct. | |
586 | + | |
587 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
588 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
589 | + | |
590 | +commit a5878d427128c1a9226045ebe05fbadaa02eb9dd | |
591 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
592 | +Date: Thu Feb 19 18:20:46 2009 +0300 | |
593 | + | |
594 | + mpc83xx: PCI: Fix bus-range fdt fixups for PCI1 controllers | |
595 | + | |
596 | + This patch fixes copy-paste issue: pci_hose[0]'s first and last | |
597 | + busnos were used to fixup pci1's nodes. | |
598 | + | |
599 | + We don't see this bug triggering only because Linux reenumerate | |
600 | + buses anyway. | |
601 | + | |
602 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
603 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
604 | + | |
605 | +commit b24a99f6666ac278ec9f9c1334518af828833d19 | |
606 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
607 | +Date: Thu Feb 19 18:20:44 2009 +0300 | |
608 | + | |
609 | + mpc83xx: PCIe: Fix CONFIG_PCI_SCAN_SHOW reporting bogus values | |
610 | + | |
611 | + This patch fixes an issue in config space read accessors: we should | |
612 | + fill-in the value even if we fail (e.g. skipping devices), otherwise | |
613 | + CONFIG_PCI_SCAN_SHOW reports bogus values during boot up. | |
614 | + | |
615 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
616 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
617 | + | |
618 | +commit e2d72ba543c7b6924b5b5d393dcd80b2b9c3a022 | |
619 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
620 | +Date: Thu Feb 19 18:20:42 2009 +0300 | |
621 | + | |
622 | + mpc83xx: PCIe: Don't start bus enumeration at 0 | |
623 | + | |
624 | + Currently we assign first_busno = 0 for the first PCIe hose, but this | |
625 | + scheme won't work if we have ordinary PCI hose already registered (its | |
626 | + first_busno value is 0 too). | |
627 | + | |
628 | + The old code worked fine only because we have PCI disabled on | |
629 | + MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92e3b13f2b3 | |
630 | + "mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards"). | |
631 | + But on MPC837XERDB boards we have PCI and PCIe, so the bug actually | |
632 | + triggers. | |
633 | + | |
634 | + So, to fix the issue, we should use pci_last_busno() + 1 for the | |
635 | + first_busno (i.e. last available busno). | |
636 | + | |
637 | + Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com> | |
638 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
639 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
640 | + | |
641 | +commit cc2a8c7751ddbae3116660064f446888538b93e9 | |
642 | +Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
643 | +Date: Thu Feb 19 18:20:41 2009 +0300 | |
644 | + | |
645 | + PCI: Add pci_last_busno() helper | |
646 | + | |
647 | + This is just a handy routine that reports last PCI busno: we walk | |
648 | + down all the hoses and return last hose's last_busno. | |
649 | + | |
650 | + Will be used by PCI/PCIe initialization code. | |
651 | + | |
652 | + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> | |
653 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
654 | + | |
655 | +commit bd76729bcbfd64b5d016a9b936f058931fc06eaf | |
656 | +Author: Becky Bruce <beckyb@kernel.crashing.org> | |
657 | +Date: Mon Feb 23 13:56:51 2009 -0600 | |
658 | + | |
659 | + MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default | |
660 | + | |
661 | + Currently, we get 256MB as the default, but since all the 86xx | |
662 | + board configs define a 2G BAT mapping for RAM, raise default | |
663 | + to 2G. | |
664 | + | |
665 | + Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> | |
666 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
667 | + | |
668 | +commit 2331e18b9df0ab98ebf3ab44c0efea1311949aaa | |
669 | +Author: Becky Bruce <beckyb@kernel.crashing.org> | |
670 | +Date: Thu Feb 12 10:43:32 2009 -0600 | |
671 | + | |
672 | + mpc8641hpcn: Indicate 36-bit addr map in boot messages | |
673 | + | |
674 | + If 36-bit addressing is enabled, print a message on the console | |
675 | + when we boot. | |
676 | + | |
677 | + Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> | |
678 | + | |
679 | +commit 2f70c49e5b9813635ad73666aa30f304c7fdeda9 | |
680 | +Author: Heiko Schocher <hs@denx.de> | |
681 | +Date: Tue Feb 10 09:38:52 2009 +0100 | |
682 | + | |
683 | + netloop: speed up NetLoop | |
684 | + | |
685 | + NetLoop polls every cycle with getenv some environment variables. | |
686 | + This is horribly slow, especially when the environment is big. | |
687 | + | |
688 | + This patch reads only the environment variables in NetLoop, | |
689 | + when they were changed. | |
690 | + | |
691 | + Also moved the init part of the NetLoop function in a seperate | |
692 | + function. | |
693 | + | |
694 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
695 | + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> | |
696 | + | |
697 | +commit ad2d16393e9f684e4a9255f42e8bfdd819b67a87 | |
698 | +Author: Mike Frysinger <vapier@gentoo.org> | |
699 | +Date: Mon Dec 22 02:56:07 2008 -0500 | |
700 | + | |
701 | + smc911x_eeprom: new example app for managing newer SMC parts | |
702 | + | |
703 | + A forward port of the last version to work with the newer smc911x driver. | |
704 | + I only have a board with a LAN9218 part on it, so that is the only one | |
705 | + I've tested. But there isn't anything in this that would make it terribly | |
706 | + chip specific afaik. | |
707 | + | |
708 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
709 | + CC: Sascha Hauer <s.hauer@pengutronix.de> | |
710 | + CC: Guennadi Liakhovetski <lg@denx.de> | |
711 | + CC: Magnus Lilja <lilja.magnus@gmail.com> | |
712 | + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> | |
713 | + | |
714 | +commit 736323a490b664ec0edc3ddb2c1c4a6824db45c6 | |
715 | +Author: Pieter Henning <phenning@vastech.co.za> | |
716 | +Date: Sun Feb 22 23:17:15 2009 -0800 | |
717 | + | |
718 | + Added Vitesse VSC8211 definitions to TSEC driver | |
719 | + | |
720 | + Added the struct containing PHY settings for the Vitesse VSC8211 phy to | |
721 | + the phy_info list in tsec.c | |
722 | + | |
723 | + Signed-off-by: Pieter Henning <phenning@vastech.co.za> | |
724 | + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> | |
725 | + | |
726 | +commit 32688e572ff96715b41420e9a7f280db6c399b65 | |
727 | +Author: Wolfgang Denk <wd@denx.de> | |
728 | +Date: Mon Feb 23 00:22:21 2009 +0100 | |
729 | + | |
730 | + Update CHANGELOG; Prepare 2009.03-rc1 | |
731 | + | |
732 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
733 | + | |
1 | 734 | commit 80b827c2b78329c6503b271e43d9eb693d644710 |
2 | 735 | Author: Wolfgang Denk <wd@denx.de> |
3 | 736 | Date: Sun Feb 22 23:45:40 2009 +0100 |
... | ... | @@ -774,6 +1507,27 @@ |
774 | 1507 | overlapping with environment. |
775 | 1508 | |
776 | 1509 | Signed-off-by: Wolfgang Denk <wd@denx.de> |
1510 | + | |
1511 | +commit 2b68b23373f96199a0cafbfd7a9f79ed62381ebb | |
1512 | +Author: Heiko Schocher <hs@denx.de> | |
1513 | +Date: Wed Feb 11 19:26:15 2009 +0100 | |
1514 | + | |
1515 | + 83xx: add missing TIMING_CFG1_CASLAT_* defines | |
1516 | + | |
1517 | + Signed-off-by: Heiko Schocher <hs@denx.de> | |
1518 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
1519 | + | |
1520 | +commit c9e34fe2e86f7b6cc8260f4b24cbdc7dd81e04c5 | |
1521 | +Author: Valeriy Glushkov <gvv@lstec.com> | |
1522 | +Date: Thu Feb 5 14:35:21 2009 +0200 | |
1523 | + | |
1524 | + mpc8349itx: allow SATA boot from the onboard SIL1334 | |
1525 | + | |
1526 | + This patch allows using of SATA devices connected | |
1527 | + to the onboard PCI SIL1334 SATA controller. | |
1528 | + | |
1529 | + Signed-off-by: Valeriy Glushkov <gvv@lstec.com> | |
1530 | + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> | |
777 | 1531 | |
778 | 1532 | commit e1ac387f4645499746856adc1aeaa9787da2eca6 |
779 | 1533 | Author: Andy Fleming <afleming@freescale.com> |