Tegra114: Initialize System Counter (TSC) with osc frequency

T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>

Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tom Warren
1 parent d0edce4fa3
Showing 7 changed files with 72 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/tegra-common/clock.c
arch/arm/cpu/tegra114-common/clock.c
arch/arm/cpu/tegra20-common/clock.c
arch/arm/cpu/tegra30-common/clock.c
arch/arm/include/asm/arch-tegra/clock.h
arch/arm/include/asm/arch-tegra114/sysctr.h
arch/arm/include/asm/arch-tegra114/tegra.h
@@ -557,5 +557,8 @@
 	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
 	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
 	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+	/* Do any special system timer/TSC setup */
+	arch_timer_init();
 }
@@ -19,6 +19,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
@@ -652,5 +653,26 @@
 	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
 	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
 	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only T114 has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
 }
@@ -559,4 +559,8 @@
 		break;
 	}
 }
+
+void arch_timer_init(void)
+{
+}
@@ -616,4 +616,8 @@
 		break;
 	}
 }
+
+void arch_timer_init(void)
+{
+}
@@ -317,5 +317,8 @@
 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
 		(id) < PERIPHC_COUNT)
  
+/* SoC-specific TSC init */
+void arch_timer_init(void);
+
 #endif  /* _TEGRA_CLOCK_H_ */
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_SYSCTR_H_
+#define _TEGRA114_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA114_SYSCTR_H_ */
@@ -18,6 +18,7 @@
 #define _TEGRA114_H_
  
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
  
 #include <asm/arch-tegra/tegra.h>
...	...	@@ -557,5 +557,8 @@
557	557	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
558	558	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
559	559	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
	560	+
	561	+ /* Do any special system timer/TSC setup */
	562	+ arch_timer_init();
560	563	}
...	...	@@ -19,6 +19,7 @@
19	19	#include <common.h>
20	20	#include <asm/io.h>
21	21	#include <asm/arch/clock.h>
	22	+#include <asm/arch/sysctr.h>
22	23	#include <asm/arch/tegra.h>
23	24	#include <asm/arch-tegra/clk_rst.h>
24	25	#include <asm/arch-tegra/timer.h>
...	...	@@ -652,5 +653,26 @@
652	653	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
653	654	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
654	655	udelay(2);
	656	+}
	657	+
	658	+void arch_timer_init(void)
	659	+{
	660	+ struct sysctr_ctlr sysctr = (struct sysctr_ctlr )NV_PA_TSC_BASE;
	661	+ u32 freq, val;
	662	+
	663	+ freq = clock_get_rate(CLOCK_ID_OSC);
	664	+ debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
	665	+
	666	+ /* ARM CNTFRQ */
	667	+ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
	668	+
	669	+ /* Only T114 has the System Counter regs */
	670	+ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
	671	+ writel(freq, &sysctr->cntfid0);
	672	+
	673	+ val = readl(&sysctr->cntcr);
	674	+ val \|= TSC_CNTCR_ENABLE \| TSC_CNTCR_HDBG;
	675	+ writel(val, &sysctr->cntcr);
	676	+ debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
655	677	}
...	...	@@ -559,4 +559,8 @@
559	559	break;
560	560	}
561	561	}
	562	+
	563	+void arch_timer_init(void)
	564	+{
	565	+}
...	...	@@ -616,4 +616,8 @@
616	616	break;
617	617	}
618	618	}
	619	+
	620	+void arch_timer_init(void)
	621	+{
	622	+}
...	...	@@ -317,5 +317,8 @@
317	317	#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
318	318	(id) < PERIPHC_COUNT)
319	319
	320	+/* SoC-specific TSC init */
	321	+void arch_timer_init(void);
	322	+
320	323	#endif /* _TEGRA_CLOCK_H_ */
	1	+/*
	2	+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify it
	5	+ * under the terms and conditions of the GNU General Public License,
	6	+ * version 2, as published by the Free Software Foundation.
	7	+ *
	8	+ * This program is distributed in the hope it will be useful, but WITHOUT
	9	+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	+ * more details.
	12	+ *
	13	+ * You should have received a copy of the GNU General Public License
	14	+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	+ */
	16	+
	17	+#ifndef _TEGRA114_SYSCTR_H_
	18	+#define _TEGRA114_SYSCTR_H_
	19	+
	20	+struct sysctr_ctlr {
	21	+ u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
	22	+ u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
	23	+ u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
	24	+ u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
	25	+ u32 reserved1[4]; /* 0x10 - 0x1C */
	26	+ u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
	27	+ u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
	28	+ u32 reserved2[1002]; /* 0x28 - 0xFCC */
	29	+ u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
	30	+};
	31	+
	32	+#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
	33	+#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
	34	+
	35	+#endif /* _TEGRA114_SYSCTR_H_ */
...	...	@@ -18,6 +18,7 @@
18	18	#define _TEGRA114_H_
19	19
20	20	#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
	21	+#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
21	22
22	23	#include <asm/arch-tegra/tegra.h>
23	24