ARM: Introduce erratum workaround for 454179

454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>

ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon · Tom Rini
1 parent c616a0df29
Showing 4 changed files with 22 additions and 0 deletions Side-by-side Diff
README
arch/arm/cpu/armv7/cp15.c
arch/arm/cpu/armv7/start.S
arch/arm/include/asm/armv7.h
@@ -693,6 +693,7 @@
 		NOTE: The following can be machine specific errata. These
 		do have ability to provide rudimentary version and machine
 		specific checks, but expect no product checks.
+		CONFIG_ARM_ERRATA_454179
 		CONFIG_ARM_ERRATA_798870
  
 - Tegra SoC options:
@@ -21,4 +21,10 @@
 {
 	asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
 }
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+				 u32 cpu_variant, u32 cpu_rev)
+{
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}
@@ -189,6 +189,19 @@
 skip_errata_798870:
 #endif
  
+#ifdef CONFIG_ARM_ERRATA_454179
+	cmp	r2, #0x21		@ Only on < r2p1
+	bge	skip_errata_454179
+
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
  
@@ -140,6 +140,8 @@
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 				 u32 cpu_rev_comb, u32 cpu_variant,
 				 u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev);
 #endif /* ! __ASSEMBLY__ */
  
 #endif
...	...	@@ -693,6 +693,7 @@
693	693	NOTE: The following can be machine specific errata. These
694	694	do have ability to provide rudimentary version and machine
695	695	specific checks, but expect no product checks.
	696	+ CONFIG_ARM_ERRATA_454179
696	697	CONFIG_ARM_ERRATA_798870
697	698
698	699	- Tegra SoC options:
...	...	@@ -21,4 +21,10 @@
21	21	{
22	22	asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
23	23	}
	24	+
	25	+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
	26	+ u32 cpu_variant, u32 cpu_rev)
	27	+{
	28	+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
	29	+}
...	...	@@ -189,6 +189,19 @@
189	189	skip_errata_798870:
190	190	#endif
191	191
	192	+#ifdef CONFIG_ARM_ERRATA_454179
	193	+ cmp r2, #0x21 @ Only on < r2p1
	194	+ bge skip_errata_454179
	195	+
	196	+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
	197	+ orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
	198	+ push {r1-r5} @ Save the cpu info registers
	199	+ bl v7_arch_cp15_set_acr
	200	+ pop {r1-r5} @ Restore the cpu info - fall through
	201	+
	202	+skip_errata_454179:
	203	+#endif
	204	+
192	205	mov pc, r5 @ back to my caller
193	206	ENDPROC(cpu_init_cp15)
194	207
...	...	@@ -140,6 +140,8 @@
140	140	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
141	141	u32 cpu_rev_comb, u32 cpu_variant,
142	142	u32 cpu_rev);
	143	+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
	144	+ u32 cpu_variant, u32 cpu_rev);
143	145	#endif /* ! __ASSEMBLY__ */
144	146
145	147	#endif