x86: Add a clock driver for Intel devices

So far we have avoided adding a clock driver for Intel devices. But the Designware I2C driver needs a different clock (133MHz) on Intel devices than on others (166MHz). Add a simple driver that provides this information. This driver can be expanded later as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: Add a clock driver for Intel devices
So far we have avoided adding a clock driver for Intel devices. But the Designware I2C driver needs a different clock (133MHz) on Intel devices than on others (166MHz). Add a simple driver that provides this information. This driver can be expanded later as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass · Bin Meng
1 parent fdec36f248
Showing 5 changed files with 73 additions and 0 deletions Side-by-side Diff
drivers/clk/Kconfig
drivers/clk/Makefile
drivers/clk/intel/Makefile
drivers/clk/intel/clk_intel.c
include/dt-bindings/clock/intel-clock.h
@@ -73,6 +73,16 @@
 	  Enable this option if you want to (re-)use the Linux kernel's Common
 	  Clock Framework [CCF] composite code in U-Boot's clock driver.
  
+config CLK_INTEL
+	bool "Enable clock driver for Intel x86"
+	depends on CLK && X86
+	help
+	  This provides very basic support for clocks on Intel SoCs. The driver
+	  is barely used at present but could be expanded as needs arise.
+	  Much clock configuration in U-Boot is either set up by the FSP, or
+	  set up by U-Boot itself but only statically. Thus the driver does not
+	  support changing clock rates, only querying them.
+
 config CLK_STM32F
 	bool "Enable clock driver support for STM32F family"
 	depends on CLK && (STM32F7 || STM32F4)
@@ -25,6 +25,7 @@
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2010 Google LLC
+#
+
+obj-y += clk_intel.o
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk-uclass.h>
+#include <dt-bindings/clock/intel-clock.h>
+
+static ulong intel_clk_get_rate(struct clk *clk)
+{
+	ulong rate;
+
+	switch (clk->id) {
+	case CLK_I2C:
+		/* Hard-coded to 133MHz on current platforms */
+		return 133333333;
+	default:
+		return -ENODEV;
+	}
+
+	return rate;
+}
+
+static struct clk_ops intel_clk_ops = {
+	.get_rate	= intel_clk_get_rate,
+};
+
+static const struct udevice_id intel_clk_ids[] = {
+	{ .compatible = "intel,apl-clk" },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_intel) = {
+	.name		= "clk_intel",
+	.id		= UCLASS_CLK,
+	.of_match	= intel_clk_ids,
+	.ops		= &intel_clk_ops,
+};
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Intel clocks.
+ *
+ * The constants defined in this header are used in the device tree
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _DT_BINDINGS_CLK_INTEL_H
+#define _DT_BINDINGS_CLK_INTEL_H
+
+#define CLK_I2C		1
+
+#endif
...	...	@@ -73,6 +73,16 @@
73	73	Enable this option if you want to (re-)use the Linux kernel's Common
74	74	Clock Framework [CCF] composite code in U-Boot's clock driver.
75	75
	76	+config CLK_INTEL
	77	+ bool "Enable clock driver for Intel x86"
	78	+ depends on CLK && X86
	79	+ help
	80	+ This provides very basic support for clocks on Intel SoCs. The driver
	81	+ is barely used at present but could be expanded as needs arise.
	82	+ Much clock configuration in U-Boot is either set up by the FSP, or
	83	+ set up by U-Boot itself but only statically. Thus the driver does not
	84	+ support changing clock rates, only querying them.
	85	+
76	86	config CLK_STM32F
77	87	bool "Enable clock driver support for STM32F family"
78	88	depends on CLK && (STM32F7 \|\| STM32F4)
...	...	@@ -25,6 +25,7 @@
25	25	obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
26	26	obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
27	27	obj-$(CONFIG_CLK_EXYNOS) += exynos/
	28	+obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
28	29	obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
29	30	obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
30	31	obj-$(CONFIG_CLK_OWL) += owl/
	1	+# SPDX-License-Identifier: GPL-2.0+
	2	+#
	3	+# Copyright 2010 Google LLC
	4	+#
	5	+
	6	+obj-y += clk_intel.o
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * Copyright 2019 Google LLC
	4	+ * Written by Simon Glass <sjg@chromium.org>
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <dm.h>
	9	+#include <clk-uclass.h>
	10	+#include <dt-bindings/clock/intel-clock.h>
	11	+
	12	+static ulong intel_clk_get_rate(struct clk *clk)
	13	+{
	14	+ ulong rate;
	15	+
	16	+ switch (clk->id) {
	17	+ case CLK_I2C:
	18	+ /* Hard-coded to 133MHz on current platforms */
	19	+ return 133333333;
	20	+ default:
	21	+ return -ENODEV;
	22	+ }
	23	+
	24	+ return rate;
	25	+}
	26	+
	27	+static struct clk_ops intel_clk_ops = {
	28	+ .get_rate = intel_clk_get_rate,
	29	+};
	30	+
	31	+static const struct udevice_id intel_clk_ids[] = {
	32	+ { .compatible = "intel,apl-clk" },
	33	+ { }
	34	+};
	35	+
	36	+U_BOOT_DRIVER(clk_intel) = {
	37	+ .name = "clk_intel",
	38	+ .id = UCLASS_CLK,
	39	+ .of_match = intel_clk_ids,
	40	+ .ops = &intel_clk_ops,
	41	+};
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * This header provides constants for Intel clocks.
	4	+ *
	5	+ * The constants defined in this header are used in the device tree
	6	+ *
	7	+ * Copyright 2019 Google LLC
	8	+ */
	9	+
	10	+#ifndef _DT_BINDINGS_CLK_INTEL_H
	11	+#define _DT_BINDINGS_CLK_INTEL_H
	12	+
	13	+#define CLK_I2C 1
	14	+
	15	+#endif