sh: Fix compile warning

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

sh: Fix compile warning
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu
1 parent 4a065abf92
Showing 9 changed files with 133 additions and 100 deletions Side-by-side Diff
board/ms7722se/lowlevel_init.S
board/r7780mp/lowlevel_init.S
board/sh7785lcr/selfcheck.c
drivers/pci/pci_sh7751.c
drivers/pci/pci_sh7780.c
include/asm-sh/cache.h
include/asm-sh/io.h
include/asm-sh/pci.h
lib_sh/bootm.c
@@ -43,48 +43,61 @@
  
 lowlevel_init:
  
-	mov.l	CCR_A, r1	! Address of Cache Control Register
-	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	/* Address of Cache Control Register */
+	mov.l	CCR_A, r1
+	/*Instruction Cache Invalidate */
+	mov.l	CCR_D, r0
 	mov.l	r0, @r1
  
-	mov.l	MMUCR_A, r1	! Address of MMU Control Register
-	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	/* Address of MMU Control Register */
+	mov.l	MMUCR_A, r1
+	/* TI == TLB Invalidate bit */
+	mov.l	MMUCR_D, r0
 	mov.l	r0, @r1
  
-	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	!
+	/* Address of Power Control Register 0 */
+	mov.l	MSTPCR0_A, r1
+	mov.l	MSTPCR0_D, r0
 	mov.l	r0, @r1
  
-	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	!
+	/* Address of Power Control Register 2 */
+	mov.l	MSTPCR2_A, r1
+	mov.l	MSTPCR2_D, r0
 	mov.l	r0, @r1
  
-	mov.l	SBSCR_A, r1	!
-	mov.w	SBSCR_D, r0	!
+	mov.l	SBSCR_A, r1
+	mov.w	SBSCR_D, r0
 	mov.w	r0, @r1
  
-	mov.l	PSCR_A, r1	!
-	mov.w	PSCR_D, r0	!
+	mov.l	PSCR_A, r1
+	mov.w	PSCR_D, r0
 	mov.w	r0, @r1
  
-!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+!	mov.l	RWTCSR_A, r1
+	/* 0xA507 -> timer_STOP/WDT_CLK=max */
+!	mov.w	RWTCSR_D_1, r0
 !	mov.w	r0, @r1
  
-	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
-	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	/* 0xA4520000 (Watchdog Count Register) */
+	mov.l	RWTCNT_A, r1
+	/*0x5A00 -> Clear */
+	mov.w	RWTCNT_D, r0
 	mov.w	r0, @r1
  
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+	mov.l	RWTCSR_A, r1
+	/* 0xA504 -> timer_STOP/CLK=500ms */
+	mov.w	RWTCSR_D_2, r0
 	mov.w	r0, @r1
  
-	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	/* 0xA4150000 Frequency control register */
+	mov.l	FRQCR_A, r1
 	mov.l	FRQCR_D, r0	!
 	mov.l	r0, @r1
  
-	mov.l	CCR_A, r1		! Address of Cache Control Register
-	mov.l	CCR_D_2, r0	! ??
+	mov.l	CCR_A, r1
+	mov.l	CCR_D_2, r0
 	mov.l	r0, @r1
  
 bsc_init:
@@ -290,6 +303,7 @@
 RWTCSR_D_1:	.word	0xA507
 RWTCSR_D_2:	.word	0xA507
 RWTCNT_D:	.word	0x5A00
+	.align	2
  
 SR_MASK_D:	.long	0xEFFFFF0F
@@ -325,8 +325,9 @@
 RWTCSR_D_1:				.word	0xA507
 RWTCSR_D_2:				.word	0xA507
 RWTCNT_D:				.word	0x5A00
+	.align	2
  
-BBG_PMMR_A:			.long	0xFF800010
+BBG_PMMR_A:				.long	0xFF800010
 BBG_PMSR1_A:			.long	0xFF800014
 BBG_PMSR2_A:			.long	0xFF800018
 BBG_PMSR3_A:			.long	0xFF80001C
@@ -84,7 +84,7 @@
 	if (data == 0x816910ec)
 		printf("Ethernet OK\n");
 	else
-		printf("Ethernet NG, data = %08x\n", data);
+		printf("Ethernet NG, data = %08x\n", (unsigned int)data);
 }
  
 static void test_sata(void)
@@ -96,7 +96,7 @@
 	if (data == 0x35121095)
 		printf("SATA OK\n");
 	else
-		printf("SATA NG, data = %08x\n", data);
+		printf("SATA NG, data = %08x\n", (unsigned int)data);
 }
  
 static void test_pci(void)
@@ -23,18 +23,19 @@
  */
  
 #include <common.h>
+#include <pci.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <pci.h>
+#include <asm/pci.h>
  
 /* Register addresses and such */
 #define SH7751_BCR1	(vu_long *)0xFF800000
-#define SH7751_BCR2	(vu_short*)0xFF800004
+#define SH7751_BCR2	(vu_short *)0xFF800004
 #define SH7751_WCR1	(vu_long *)0xFF800008
 #define SH7751_WCR2	(vu_long *)0xFF80000C
 #define SH7751_WCR3	(vu_long *)0xFF800010
 #define SH7751_MCR	(vu_long *)0xFF800014
-#define SH7751_BCR3	(vu_short*)0xFF800050
+#define SH7751_BCR3	(vu_short *)0xFF800050
 #define SH7751_PCICONF0 (vu_long *)0xFE200000
 #define SH7751_PCICONF1 (vu_long *)0xFE200004
 #define SH7751_PCICONF2 (vu_long *)0xFE200008
  
@@ -87,12 +88,12 @@
 #define SH7751_PCIPAR   (vu_long *)0xFE2001C0
 #define SH7751_PCIPDR   (vu_long *)0xFE200220
  
-#define p4_in(addr)     *(addr)
-#define p4_out(data,addr) *(addr) = (data)
+#define p4_in(addr)	(*addr)
+#define p4_out(data, addr) (*addr) = (data)
  
 /* Double word */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32 * value)
+			      pci_dev_t dev, int offset, u32 *value)
 {
 	u32 par_data = 0x80000000 | dev;
  
@@ -103,7 +104,7 @@
 }
  
 int pci_sh4_write_config_dword(struct pci_controller *hose,
-			       pci_dev_t dev, int offset, u32 * value)
+			       pci_dev_t dev, int offset, u32 value)
 {
 	u32 par_data = 0x80000000 | dev;
  
  
  
@@ -126,15 +127,18 @@
 	/* Double-check some BSC config settings */
 	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
 	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
-		printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+		printf("SH7751_BCR1 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR1));
 		return 2;
 	}
 	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 3;
 	}
 	if (p4_in(SH7751_BCR2) & 0x01) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 4;
 	}
  
@@ -25,9 +25,10 @@
  
 #include <common.h>
  
+#include <pci.h>
 #include <asm/processor.h>
+#include <asm/pci.h>
 #include <asm/io.h>
-#include <pci.h>
  
 #define SH7780_VENDOR_ID	0x1912
 #define SH7780_DEVICE_ID	0x0002
@@ -41,10 +42,10 @@
 #define SH7780_PCICR_PRST	0x00000002
 #define SH7780_PCICR_CFIN	0x00000001
  
-#define p4_in(addr)			*((vu_long *)addr)
-#define p4_out(data,addr)	*(vu_long *)(addr) = (data)
-#define p4_inw(addr)		*((vu_short *)addr)
-#define p4_outw(data,addr)	*(vu_short *)(addr) = (data)
+#define p4_in(addr)			(*(vu_long *)addr)
+#define p4_out(data, addr)	(*(vu_long *)addr) = (data)
+#define p4_inw(addr)		(*(vu_short *)addr)
+#define p4_outw(data, addr)	(*(vu_short *)addr) = (data)
  
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 				    pci_dev_t dev, int offset, u32 *value)
  
@@ -72,9 +73,9 @@
 	p4_out(0x01, SH7780_PCIECR);
  
 	if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
-	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
 		printf("PCI: Unknown PCI host bridge.\n");
-		return;
+		return -1;
 	}
 	printf("PCI: SH7780 PCI host bridge found.\n");
  
@@ -3,29 +3,31 @@
  
 #if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
  
+int cache_control(unsigned int cmd);
+
 #define L1_CACHE_BYTES 32
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
  
-void dcache_wback_range (u32 start, u32 end)
+void dcache_wback_range(u32 start, u32 end)
 {
 	u32 v;
  
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbwb     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbwb     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
  
-void dcache_invalid_range (u32 start, u32 end)
+void dcache_invalid_range(u32 start, u32 end)
 {
 	u32 v;
  
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbi     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbi     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
 #endif /* CONFIG_SH4 || CONFIG_SH4A */
@@ -34,9 +34,9 @@
 #define __arch_getw(a)			(*(volatile unsigned short *)(a))
 #define __arch_getl(a)			(*(volatile unsigned int *)(a))
  
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
  
 extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
 extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
@@ -46,9 +46,9 @@
 extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
 extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  
-#define __raw_writeb(v,a)		__arch_putb(v,a)
-#define __raw_writew(v,a)		__arch_putw(v,a)
-#define __raw_writel(v,a)		__arch_putl(v,a)
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
  
 #define __raw_readb(a)			__arch_getb(a)
 #define __raw_readw(a)			__arch_getw(a)
  
@@ -59,13 +59,13 @@
  * properly.  Spell it out to the compiler in some cases.
  * These are only valid for small values of "off" (< 1<<12)
  */
-#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
-#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
-#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
  
-#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
-#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
-#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
  
 /*
  * Now, pick up the machine-defined IO definitions
  
  
  
  
  
@@ -91,36 +91,43 @@
  *
  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  */
-#define outb(v,p)               __raw_writeb(v, p)
-#define outw(v,p)               __raw_writew(cpu_to_le16(v),p)
-#define outl(v,p)               __raw_writel(cpu_to_le32(v),p)
+#define outb(v, p)               __raw_writeb(v, p)
+#define outw(v, p)               __raw_writew(cpu_to_le16(v), p)
+#define outl(v, p)               __raw_writel(cpu_to_le32(v), p)
  
 #define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
 #define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
 #define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
  
-#define outsb(p,d,l)			__raw_writesb(p,d,l)
-#define outsw(p,d,l)			__raw_writesw(p,d,l)
-#define outsl(p,d,l)			__raw_writesl(p,d,l)
+#define outsb(p, d, l)			__raw_writesb(p, d, l)
+#define outsw(p, d, l)			__raw_writesw(p, d, l)
+#define outsl(p, d, l)			__raw_writesl(p, d, l)
  
-#define insb(p,d,l)			__raw_readsb(p,d,l)
-#define insw(p,d,l)			__raw_readsw(p,d,l)
-#define insl(p,d,l)			__raw_readsl(p,d,l)
+#define insb(p, d, l)			__raw_readsb(p, d, l)
+#define insw(p, d, l)			__raw_readsw(p, d, l)
+#define insl(p, d, l)			__raw_readsl(p, d, l)
  
-#define outb_p(val,port)		outb((val),(port))
-#define outw_p(val,port)		outw((val),(port))
-#define outl_p(val,port)		outl((val),(port))
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
 #define inb_p(port)			inb((port))
 #define inw_p(port)			inw((port))
 #define inl_p(port)			inl((port))
  
-#define outsb_p(port,from,len)		outsb(port,from,len)
-#define outsw_p(port,from,len)		outsw(port,from,len)
-#define outsl_p(port,from,len)		outsl(port,from,len)
-#define insb_p(port,to,len)		insb(port,to,len)
-#define insw_p(port,to,len)		insw(port,to,len)
-#define insl_p(port,to,len)		insl(port,to,len)
+#define outsb_p(port, from, len)		outsb(port, from, len)
+#define outsw_p(port, from, len)		outsw(port, from, len)
+#define outsl_p(port, from, len)		outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
  
+/* for U-Boot PCI */
+#define out_8(port, val)	outb(val, port)
+#define out_le16(port, val)	outw(val, port)
+#define out_le32(port, val)	outl(val, port)
+#define in_8(port)			inb(port)
+#define in_le16(port)		inw(port)
+#define in_le32(port)		inl(port)
 /*
  * ioremap and friends.
  *
@@ -128,7 +135,7 @@
  * linux/Documentation/IO-mapping.txt.  If you want a
  * physical address, use __ioremap instead.
  */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
 extern void __iounmap(void *addr);
  
 /*
  
  
@@ -139,20 +146,20 @@
  *  iomem_to_phys(off)
  */
 #ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)				\
+#define __arch_ioremap(off, sz, nocache)				\
  ({								\
 	unsigned long _off = (off), _size = (sz);		\
 	void *_ret = (void *)0;					\
 	if (iomem_valid_addr(_off, _size))			\
-		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
 	_ret;							\
  })
  
 #define __arch_iounmap __iounmap
 #endif
  
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define ioremap(off, sz)			__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)		__arch_ioremap((off), (sz), 1)
 #define iounmap(_addr)			__arch_iounmap(_addr)
  
 /*
  
  
  
@@ -180,19 +187,21 @@
 #ifdef __mem_pci
  
 #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+#define readw(c)\
+	({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c)\
+	({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
  
-#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
-#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
  
-#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+#define memset_io(c, v, l)		_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
  
-#define eth_io_copy_and_sum(s,c,l,b) \
-				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+#define eth_io_copy_and_sum(s, c, l, b) \
+				eth_copy_and_sum((s), __mem_pci(c), (l), (b))
  
 static inline int
 check_signature(unsigned long io_addr, const unsigned char *signature,
  
@@ -216,11 +225,11 @@
 #define readb(addr)	__raw_readb(addr)
 #define readw(addr)	__raw_readw(addr)
 #define readl(addr)	__raw_readl(addr)
-#define writeb(v,addr)	__raw_writeb(v, addr)
-#define writew(v,addr)	__raw_writew(v, addr)
-#define writel(v,addr)	__raw_writel(v, addr)
+#define writeb(v, addr)	__raw_writeb(v, addr)
+#define writew(v, addr)	__raw_writew(v, addr)
+#define writel(v, addr)	__raw_writel(v, addr)
  
-#define check_signature(io,sig,len)	(0)
+#define check_signature(io, sig, len)	(0)
  
 #endif	/* __mem_pci */
  
@@ -36,6 +36,7 @@
 #error "Not support PCI."
 #endif
  
+int pci_sh4_init(struct pci_controller *hose);
 /* PCI dword read for sh4 */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 		pci_dev_t dev, int offset, u32 *value);
@@ -48,11 +48,12 @@
 	/* Linux kernel load address */
 	void (*kernel) (void) = (void (*)(void))images->ep;
 	/* empty_zero_page */
-	unsigned char *param = (unsigned char *)image_get_ep(images);
+	unsigned char *param
+		= (unsigned char *)image_get_load(images->legacy_hdr_os);
 	/* Linux kernel command line */
-	unsigned char *cmdline = param + 0x100;
+	char *cmdline = (char *)param + 0x100;
 	/* PAGE_SIZE */
-	unsigned long size = images->ep - image_get_ep(images);
+	unsigned long size = images->ep - (unsigned long)param;
 	char *bootargs = getenv("bootargs");
  
 	/* Setup parameters */
...	...	@@ -43,48 +43,61 @@
43	43
44	44	lowlevel_init:
45	45
46		- mov.l CCR_A, r1 ! Address of Cache Control Register
47		- mov.l CCR_D, r0 ! Instruction Cache Invalidate
	46	+ /* Address of Cache Control Register */
	47	+ mov.l CCR_A, r1
	48	+ /Instruction Cache Invalidate /
	49	+ mov.l CCR_D, r0
48	50	mov.l r0, @r1
49	51
50		- mov.l MMUCR_A, r1 ! Address of MMU Control Register
51		- mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
	52	+ /* Address of MMU Control Register */
	53	+ mov.l MMUCR_A, r1
	54	+ /* TI == TLB Invalidate bit */
	55	+ mov.l MMUCR_D, r0
52	56	mov.l r0, @r1
53	57
54		- mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
55		- mov.l MSTPCR0_D, r0 !
	58	+ /* Address of Power Control Register 0 */
	59	+ mov.l MSTPCR0_A, r1
	60	+ mov.l MSTPCR0_D, r0
56	61	mov.l r0, @r1
57	62
58		- mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
59		- mov.l MSTPCR2_D, r0 !
	63	+ /* Address of Power Control Register 2 */
	64	+ mov.l MSTPCR2_A, r1
	65	+ mov.l MSTPCR2_D, r0
60	66	mov.l r0, @r1
61	67
62		- mov.l SBSCR_A, r1 !
63		- mov.w SBSCR_D, r0 !
	68	+ mov.l SBSCR_A, r1
	69	+ mov.w SBSCR_D, r0
64	70	mov.w r0, @r1
65	71
66		- mov.l PSCR_A, r1 !
67		- mov.w PSCR_D, r0 !
	72	+ mov.l PSCR_A, r1
	73	+ mov.w PSCR_D, r0
68	74	mov.w r0, @r1
69	75
70		-! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
71		-! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
	76	+ /* 0xA4520004 (Watchdog Control / Status Register) */
	77	+! mov.l RWTCSR_A, r1
	78	+ /* 0xA507 -> timer_STOP/WDT_CLK=max */
	79	+! mov.w RWTCSR_D_1, r0
72	80	! mov.w r0, @r1
73	81
74		- mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
75		- mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
	82	+ /* 0xA4520000 (Watchdog Count Register) */
	83	+ mov.l RWTCNT_A, r1
	84	+ /0x5A00 -> Clear /
	85	+ mov.w RWTCNT_D, r0
76	86	mov.w r0, @r1
77	87
78		- mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
79		- mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
	88	+ /* 0xA4520004 (Watchdog Control / Status Register) */
	89	+ mov.l RWTCSR_A, r1
	90	+ /* 0xA504 -> timer_STOP/CLK=500ms */
	91	+ mov.w RWTCSR_D_2, r0
80	92	mov.w r0, @r1
81	93
82		- mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
	94	+ /* 0xA4150000 Frequency control register */
	95	+ mov.l FRQCR_A, r1
83	96	mov.l FRQCR_D, r0 !
84	97	mov.l r0, @r1
85	98
86		- mov.l CCR_A, r1 ! Address of Cache Control Register
87		- mov.l CCR_D_2, r0 ! ??
	99	+ mov.l CCR_A, r1
	100	+ mov.l CCR_D_2, r0
88	101	mov.l r0, @r1
89	102
90	103	bsc_init:
...	...	@@ -290,6 +303,7 @@
290	303	RWTCSR_D_1: .word 0xA507
291	304	RWTCSR_D_2: .word 0xA507
292	305	RWTCNT_D: .word 0x5A00
	306	+ .align 2
293	307
294	308	SR_MASK_D: .long 0xEFFFFF0F
...	...	@@ -325,8 +325,9 @@
325	325	RWTCSR_D_1: .word 0xA507
326	326	RWTCSR_D_2: .word 0xA507
327	327	RWTCNT_D: .word 0x5A00
	328	+ .align 2
328	329
329		-BBG_PMMR_A: .long 0xFF800010
	330	+BBG_PMMR_A: .long 0xFF800010
330	331	BBG_PMSR1_A: .long 0xFF800014
331	332	BBG_PMSR2_A: .long 0xFF800018
332	333	BBG_PMSR3_A: .long 0xFF80001C
...	...	@@ -84,7 +84,7 @@
84	84	if (data == 0x816910ec)
85	85	printf("Ethernet OK\n");
86	86	else
87		- printf("Ethernet NG, data = %08x\n", data);
	87	+ printf("Ethernet NG, data = %08x\n", (unsigned int)data);
88	88	}
89	89
90	90	static void test_sata(void)
...	...	@@ -96,7 +96,7 @@
96	96	if (data == 0x35121095)
97	97	printf("SATA OK\n");
98	98	else
99		- printf("SATA NG, data = %08x\n", data);
	99	+ printf("SATA NG, data = %08x\n", (unsigned int)data);
100	100	}
101	101
102	102	static void test_pci(void)
...	...	@@ -23,18 +23,19 @@
23	23	*/
24	24
25	25	#include <common.h>
	26	+#include <pci.h>
26	27	#include <asm/processor.h>
27	28	#include <asm/io.h>
28		-#include <pci.h>
	29	+#include <asm/pci.h>
29	30
30	31	/* Register addresses and such */
31	32	#define SH7751_BCR1 (vu_long *)0xFF800000
32		-#define SH7751_BCR2 (vu_short*)0xFF800004
	33	+#define SH7751_BCR2 (vu_short *)0xFF800004
33	34	#define SH7751_WCR1 (vu_long *)0xFF800008
34	35	#define SH7751_WCR2 (vu_long *)0xFF80000C
35	36	#define SH7751_WCR3 (vu_long *)0xFF800010
36	37	#define SH7751_MCR (vu_long *)0xFF800014
37		-#define SH7751_BCR3 (vu_short*)0xFF800050
	38	+#define SH7751_BCR3 (vu_short *)0xFF800050
38	39	#define SH7751_PCICONF0 (vu_long *)0xFE200000
39	40	#define SH7751_PCICONF1 (vu_long *)0xFE200004
40	41	#define SH7751_PCICONF2 (vu_long *)0xFE200008
41	42
...	...	@@ -87,12 +88,12 @@
87	88	#define SH7751_PCIPAR (vu_long *)0xFE2001C0
88	89	#define SH7751_PCIPDR (vu_long *)0xFE200220
89	90
90		-#define p4_in(addr) *(addr)
91		-#define p4_out(data,addr) *(addr) = (data)
	91	+#define p4_in(addr) (*addr)
	92	+#define p4_out(data, addr) (*addr) = (data)
92	93
93	94	/* Double word */
94	95	int pci_sh4_read_config_dword(struct pci_controller *hose,
95		- pci_dev_t dev, int offset, u32 * value)
	96	+ pci_dev_t dev, int offset, u32 *value)
96	97	{
97	98	u32 par_data = 0x80000000 \| dev;
98	99
...	...	@@ -103,7 +104,7 @@
103	104	}
104	105
105	106	int pci_sh4_write_config_dword(struct pci_controller *hose,
106		- pci_dev_t dev, int offset, u32 * value)
	107	+ pci_dev_t dev, int offset, u32 value)
107	108	{
108	109	u32 par_data = 0x80000000 \| dev;
109	110
110	111
111	112
...	...	@@ -126,15 +127,18 @@
126	127	/* Double-check some BSC config settings */
127	128	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
128	129	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
129		- printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
	130	+ printf("SH7751_BCR1 value is wrong(0x%08X)\n",
	131	+ (unsigned int)p4_in(SH7751_BCR1));
130	132	return 2;
131	133	}
132	134	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
133		- printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
	135	+ printf("SH7751_BCR2 value is wrong(0x%08X)\n",
	136	+ (unsigned int)p4_in(SH7751_BCR2));
134	137	return 3;
135	138	}
136	139	if (p4_in(SH7751_BCR2) & 0x01) {
137		- printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
	140	+ printf("SH7751_BCR2 value is wrong(0x%08X)\n",
	141	+ (unsigned int)p4_in(SH7751_BCR2));
138	142	return 4;
139	143	}
140	144
...	...	@@ -25,9 +25,10 @@
25	25
26	26	#include <common.h>
27	27
	28	+#include <pci.h>
28	29	#include <asm/processor.h>
	30	+#include <asm/pci.h>
29	31	#include <asm/io.h>
30		-#include <pci.h>
31	32
32	33	#define SH7780_VENDOR_ID 0x1912
33	34	#define SH7780_DEVICE_ID 0x0002
...	...	@@ -41,10 +42,10 @@
41	42	#define SH7780_PCICR_PRST 0x00000002
42	43	#define SH7780_PCICR_CFIN 0x00000001
43	44
44		-#define p4_in(addr) ((vu_long )addr)
45		-#define p4_out(data,addr) (vu_long )(addr) = (data)
46		-#define p4_inw(addr) ((vu_short )addr)
47		-#define p4_outw(data,addr) (vu_short )(addr) = (data)
	45	+#define p4_in(addr) ((vu_long )addr)
	46	+#define p4_out(data, addr) ((vu_long )addr) = (data)
	47	+#define p4_inw(addr) ((vu_short )addr)
	48	+#define p4_outw(data, addr) ((vu_short )addr) = (data)
48	49
49	50	int pci_sh4_read_config_dword(struct pci_controller *hose,
50	51	pci_dev_t dev, int offset, u32 *value)
51	52
...	...	@@ -72,9 +73,9 @@
72	73	p4_out(0x01, SH7780_PCIECR);
73	74
74	75	if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
75		- && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
	76	+ && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
76	77	printf("PCI: Unknown PCI host bridge.\n");
77		- return;
	78	+ return -1;
78	79	}
79	80	printf("PCI: SH7780 PCI host bridge found.\n");
80	81
...	...	@@ -3,29 +3,31 @@
3	3
4	4	#if defined(CONFIG_SH4) \|\| defined(CONFIG_SH4A)
5	5
	6	+int cache_control(unsigned int cmd);
	7	+
6	8	#define L1_CACHE_BYTES 32
7	9	struct __large_struct { unsigned long buf[100]; };
8	10	#define __m(x) ((struct __large_struct )(x))
9	11
10		-void dcache_wback_range (u32 start, u32 end)
	12	+void dcache_wback_range(u32 start, u32 end)
11	13	{
12	14	u32 v;
13	15
14	16	start &= ~(L1_CACHE_BYTES - 1);
15	17	for (v = start; v < end; v += L1_CACHE_BYTES) {
16		- asm volatile ("ocbwb %0": /* no output */
17		- :"m" (__m (v)));
	18	+ asm volatile ("ocbwb %0" : /* no output */
	19	+ : "m" (__m(v)));
18	20	}
19	21	}
20	22
21		-void dcache_invalid_range (u32 start, u32 end)
	23	+void dcache_invalid_range(u32 start, u32 end)
22	24	{
23	25	u32 v;
24	26
25	27	start &= ~(L1_CACHE_BYTES - 1);
26	28	for (v = start; v < end; v += L1_CACHE_BYTES) {
27		- asm volatile ("ocbi %0": /* no output */
28		- :"m" (__m (v)));
	29	+ asm volatile ("ocbi %0" : /* no output */
	30	+ : "m" (__m(v)));
29	31	}
30	32	}
31	33	#endif /* CONFIG_SH4 \|\| CONFIG_SH4A */
...	...	@@ -34,9 +34,9 @@
34	34	#define __arch_getw(a) ((volatile unsigned short )(a))
35	35	#define __arch_getl(a) ((volatile unsigned int )(a))
36	36
37		-#define __arch_putb(v,a) ((volatile unsigned char )(a) = (v))
38		-#define __arch_putw(v,a) ((volatile unsigned short )(a) = (v))
39		-#define __arch_putl(v,a) ((volatile unsigned int )(a) = (v))
	37	+#define __arch_putb(v, a) ((volatile unsigned char )(a) = (v))
	38	+#define __arch_putw(v, a) ((volatile unsigned short )(a) = (v))
	39	+#define __arch_putl(v, a) ((volatile unsigned int )(a) = (v))
40	40
41	41	extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
42	42	extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
...	...	@@ -46,9 +46,9 @@
46	46	extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
47	47	extern void __raw_readsl(unsigned int addr, void *data, int longlen);
48	48
49		-#define __raw_writeb(v,a) __arch_putb(v,a)
50		-#define __raw_writew(v,a) __arch_putw(v,a)
51		-#define __raw_writel(v,a) __arch_putl(v,a)
	49	+#define __raw_writeb(v, a) __arch_putb(v, a)
	50	+#define __raw_writew(v, a) __arch_putw(v, a)
	51	+#define __raw_writel(v, a) __arch_putl(v, a)
52	52
53	53	#define __raw_readb(a) __arch_getb(a)
54	54	#define __raw_readw(a) __arch_getw(a)
55	55
...	...	@@ -59,13 +59,13 @@
59	59	* properly. Spell it out to the compiler in some cases.
60	60	* These are only valid for small values of "off" (< 1<<12)
61	61	*/
62		-#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
63		-#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
64		-#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
	62	+#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
	63	+#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
	64	+#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
65	65
66		-#define __raw_base_readb(base,off) __arch_base_getb(base,off)
67		-#define __raw_base_readw(base,off) __arch_base_getw(base,off)
68		-#define __raw_base_readl(base,off) __arch_base_getl(base,off)
	66	+#define __raw_base_readb(base, off) __arch_base_getb(base, off)
	67	+#define __raw_base_readw(base, off) __arch_base_getw(base, off)
	68	+#define __raw_base_readl(base, off) __arch_base_getl(base, off)
69	69
70	70	/*
71	71	* Now, pick up the machine-defined IO definitions
72	72
73	73
74	74
75	75
76	76
...	...	@@ -91,36 +91,43 @@
91	91	*
92	92	* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
93	93	*/
94		-#define outb(v,p) __raw_writeb(v, p)
95		-#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
96		-#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
	94	+#define outb(v, p) __raw_writeb(v, p)
	95	+#define outw(v, p) __raw_writew(cpu_to_le16(v), p)
	96	+#define outl(v, p) __raw_writel(cpu_to_le32(v), p)
97	97
98	98	#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
99	99	#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
100	100	#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
101	101
102		-#define outsb(p,d,l) __raw_writesb(p,d,l)
103		-#define outsw(p,d,l) __raw_writesw(p,d,l)
104		-#define outsl(p,d,l) __raw_writesl(p,d,l)
	102	+#define outsb(p, d, l) __raw_writesb(p, d, l)
	103	+#define outsw(p, d, l) __raw_writesw(p, d, l)
	104	+#define outsl(p, d, l) __raw_writesl(p, d, l)
105	105
106		-#define insb(p,d,l) __raw_readsb(p,d,l)
107		-#define insw(p,d,l) __raw_readsw(p,d,l)
108		-#define insl(p,d,l) __raw_readsl(p,d,l)
	106	+#define insb(p, d, l) __raw_readsb(p, d, l)
	107	+#define insw(p, d, l) __raw_readsw(p, d, l)
	108	+#define insl(p, d, l) __raw_readsl(p, d, l)
109	109
110		-#define outb_p(val,port) outb((val),(port))
111		-#define outw_p(val,port) outw((val),(port))
112		-#define outl_p(val,port) outl((val),(port))
	110	+#define outb_p(val, port) outb((val), (port))
	111	+#define outw_p(val, port) outw((val), (port))
	112	+#define outl_p(val, port) outl((val), (port))
113	113	#define inb_p(port) inb((port))
114	114	#define inw_p(port) inw((port))
115	115	#define inl_p(port) inl((port))
116	116
117		-#define outsb_p(port,from,len) outsb(port,from,len)
118		-#define outsw_p(port,from,len) outsw(port,from,len)
119		-#define outsl_p(port,from,len) outsl(port,from,len)
120		-#define insb_p(port,to,len) insb(port,to,len)
121		-#define insw_p(port,to,len) insw(port,to,len)
122		-#define insl_p(port,to,len) insl(port,to,len)
	117	+#define outsb_p(port, from, len) outsb(port, from, len)
	118	+#define outsw_p(port, from, len) outsw(port, from, len)
	119	+#define outsl_p(port, from, len) outsl(port, from, len)
	120	+#define insb_p(port, to, len) insb(port, to, len)
	121	+#define insw_p(port, to, len) insw(port, to, len)
	122	+#define insl_p(port, to, len) insl(port, to, len)
123	123
	124	+/* for U-Boot PCI */
	125	+#define out_8(port, val) outb(val, port)
	126	+#define out_le16(port, val) outw(val, port)
	127	+#define out_le32(port, val) outl(val, port)
	128	+#define in_8(port) inb(port)
	129	+#define in_le16(port) inw(port)
	130	+#define in_le32(port) inl(port)
124	131	/*
125	132	* ioremap and friends.
126	133	*
...	...	@@ -128,7 +135,7 @@
128	135	* linux/Documentation/IO-mapping.txt. If you want a
129	136	* physical address, use __ioremap instead.
130	137	*/
131		-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
	138	+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
132	139	extern void __iounmap(void *addr);
133	140
134	141	/*
135	142
136	143
...	...	@@ -139,20 +146,20 @@
139	146	* iomem_to_phys(off)
140	147	*/
141	148	#ifdef iomem_valid_addr
142		-#define __arch_ioremap(off,sz,nocache) \
	149	+#define __arch_ioremap(off, sz, nocache) \
143	150	({ \
144	151	unsigned long _off = (off), _size = (sz); \
145	152	void _ret = (void )0; \
146	153	if (iomem_valid_addr(_off, _size)) \
147		- _ret = __ioremap(iomem_to_phys(_off),_size,0); \
	154	+ _ret = __ioremap(iomem_to_phys(_off), _size, 0); \
148	155	_ret; \
149	156	})
150	157
151	158	#define __arch_iounmap __iounmap
152	159	#endif
153	160
154		-#define ioremap(off,sz) __arch_ioremap((off),(sz),0)
155		-#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1)
	161	+#define ioremap(off, sz) __arch_ioremap((off), (sz), 0)
	162	+#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1)
156	163	#define iounmap(_addr) __arch_iounmap(_addr)
157	164
158	165	/*
159	166
160	167
161	168
...	...	@@ -180,19 +187,21 @@
180	187	#ifdef __mem_pci
181	188
182	189	#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
183		-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
184		-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
	190	+#define readw(c)\
	191	+ ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
	192	+#define readl(c)\
	193	+ ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
185	194
186		-#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
187		-#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
188		-#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
	195	+#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
	196	+#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
	197	+#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
189	198
190		-#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
191		-#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
192		-#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
	199	+#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
	200	+#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
	201	+#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
193	202
194		-#define eth_io_copy_and_sum(s,c,l,b) \
195		- eth_copy_and_sum((s),__mem_pci(c),(l),(b))
	203	+#define eth_io_copy_and_sum(s, c, l, b) \
	204	+ eth_copy_and_sum((s), __mem_pci(c), (l), (b))
196	205
197	206	static inline int
198	207	check_signature(unsigned long io_addr, const unsigned char *signature,
199	208
...	...	@@ -216,11 +225,11 @@
216	225	#define readb(addr) __raw_readb(addr)
217	226	#define readw(addr) __raw_readw(addr)
218	227	#define readl(addr) __raw_readl(addr)
219		-#define writeb(v,addr) __raw_writeb(v, addr)
220		-#define writew(v,addr) __raw_writew(v, addr)
221		-#define writel(v,addr) __raw_writel(v, addr)
	228	+#define writeb(v, addr) __raw_writeb(v, addr)
	229	+#define writew(v, addr) __raw_writew(v, addr)
	230	+#define writel(v, addr) __raw_writel(v, addr)
222	231
223		-#define check_signature(io,sig,len) (0)
	232	+#define check_signature(io, sig, len) (0)
224	233
225	234	#endif /* __mem_pci */
226	235
...	...	@@ -36,6 +36,7 @@
36	36	#error "Not support PCI."
37	37	#endif
38	38
	39	+int pci_sh4_init(struct pci_controller *hose);
39	40	/* PCI dword read for sh4 */
40	41	int pci_sh4_read_config_dword(struct pci_controller *hose,
41	42	pci_dev_t dev, int offset, u32 *value);
...	...	@@ -48,11 +48,12 @@
48	48	/* Linux kernel load address */
49	49	void (kernel) (void) = (void ()(void))images->ep;
50	50	/* empty_zero_page */
51		- unsigned char param = (unsigned char )image_get_ep(images);
	51	+ unsigned char *param
	52	+ = (unsigned char *)image_get_load(images->legacy_hdr_os);
52	53	/* Linux kernel command line */
53		- unsigned char *cmdline = param + 0x100;
	54	+ char cmdline = (char )param + 0x100;
54	55	/* PAGE_SIZE */
55		- unsigned long size = images->ep - image_get_ep(images);
	56	+ unsigned long size = images->ep - (unsigned long)param;
56	57	char *bootargs = getenv("bootargs");
57	58
58	59	/* Setup parameters */