Commit b616d9b0a708eb90eb474e1b6ec6dfe4c48a1678

Authored by Scott Wood
1 parent 151c06ec61

nand: Embed mtd_info in struct nand_chip

nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].

Signed-off-by: Scott Wood <oss@buserror.net>

Showing 44 changed files with 247 additions and 239 deletions Side-by-side Diff

board/BuR/common/common.c
... ... @@ -259,7 +259,7 @@
259 259 }
260 260 #ifdef CONFIG_NAND
261 261 dtbsize = 0x20000;
262   - rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize,
  262 + rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
263 263 NULL, 0x20000, (u_char *)dtbaddr);
264 264 #else
265 265 char *dtbname = getenv("dtb");
board/atmel/at91sam9261ek/at91sam9261ek.c
... ... @@ -212,7 +212,7 @@
212 212 dram_size += gd->bd->bi_dram[i].size;
213 213 nand_size = 0;
214 214 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
215   - nand_size += nand_info[i].size;
  215 + nand_size += nand_info[i]->size;
216 216 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
217 217 dram_size >> 20,
218 218 nand_size >> 20 );
board/atmel/at91sam9263ek/at91sam9263ek.c
... ... @@ -191,7 +191,7 @@
191 191 dram_size += gd->bd->bi_dram[i].size;
192 192 nand_size = 0;
193 193 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
194   - nand_size += nand_info[i].size;
  194 + nand_size += nand_info[i]->size;
195 195 #ifndef CONFIG_SYS_NO_FLASH
196 196 flash_size = 0;
197 197 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
... ... @@ -272,7 +272,7 @@
272 272 dram_size += gd->bd->bi_dram[i].size;
273 273 nand_size = 0;
274 274 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
275   - nand_size += nand_info[i].size;
  275 + nand_size += nand_info[i]->size;
276 276 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
277 277 dram_size >> 20,
278 278 nand_size >> 20 );
board/atmel/at91sam9n12ek/at91sam9n12ek.c
... ... @@ -124,7 +124,7 @@
124 124 dram_size += gd->bd->bi_dram[i].size;
125 125 nand_size = 0;
126 126 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
127   - nand_size += nand_info[i].size;
  127 + nand_size += nand_info[i]->size;
128 128 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
129 129 dram_size >> 20,
130 130 nand_size >> 20);
board/atmel/at91sam9rlek/at91sam9rlek.c
... ... @@ -151,7 +151,7 @@
151 151 dram_size += gd->bd->bi_dram[i].size;
152 152 nand_size = 0;
153 153 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
154   - nand_size += nand_info[i].size;
  154 + nand_size += nand_info[i]->size;
155 155 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
156 156 dram_size >> 20,
157 157 nand_size >> 20 );
board/atmel/at91sam9x5ek/at91sam9x5ek.c
... ... @@ -196,7 +196,7 @@
196 196 dram_size += gd->bd->bi_dram[i].size;
197 197 nand_size = 0;
198 198 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
199   - nand_size += nand_info[i].size;
  199 + nand_size += nand_info[i]->size;
200 200 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
201 201 dram_size >> 20,
202 202 nand_size >> 20);
board/atmel/sama5d3xek/sama5d3xek.c
... ... @@ -207,7 +207,7 @@
207 207 nand_size = 0;
208 208 #ifdef CONFIG_NAND_ATMEL
209 209 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
210   - nand_size += nand_info[i].size;
  210 + nand_size += nand_info[i]->size;
211 211 #endif
212 212 lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
213 213 dram_size >> 20, nand_size >> 20);
board/atmel/sama5d4_xplained/sama5d4_xplained.c
... ... @@ -191,7 +191,7 @@
191 191 nand_size = 0;
192 192 #ifdef CONFIG_NAND_ATMEL
193 193 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
194   - nand_size += nand_info[i].size;
  194 + nand_size += nand_info[i]->size;
195 195 #endif
196 196 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
197 197 dram_size >> 20, nand_size >> 20);
board/atmel/sama5d4ek/sama5d4ek.c
... ... @@ -187,7 +187,7 @@
187 187 nand_size = 0;
188 188 #ifdef CONFIG_NAND_ATMEL
189 189 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
190   - nand_size += nand_info[i].size;
  190 + nand_size += nand_info[i]->size;
191 191 #endif
192 192 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
193 193 dram_size >> 20, nand_size >> 20);
board/ronetix/pm9261/pm9261.c
... ... @@ -194,7 +194,7 @@
194 194  
195 195 nand_size = 0;
196 196 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
197   - nand_size += nand_info[i].size;
  197 + nand_size += nand_info[i]->size;
198 198  
199 199 flash_size = 0;
200 200 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
board/ronetix/pm9263/pm9263.c
... ... @@ -293,7 +293,7 @@
293 293  
294 294 nand_size = 0;
295 295 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
296   - nand_size += nand_info[i].size;
  296 + nand_size += nand_info[i]->size;
297 297  
298 298 flash_size = 0;
299 299 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
... ... @@ -461,7 +461,7 @@
461 461 printf("\n");
462 462  
463 463 for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
464   - mtd = &nand_info[nand_dev];
  464 + mtd = nand_info[nand_dev];
465 465 if (!mtd->name || !mtd->size)
466 466 continue;
467 467  
... ... @@ -167,7 +167,7 @@
167 167 } else if (type == MTD_DEV_TYPE_NAND) {
168 168 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
169 169 if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
170   - *size = nand_info[num].size;
  170 + *size = nand_info[num]->size;
171 171 return 0;
172 172 }
173 173  
... ... @@ -244,7 +244,7 @@
244 244 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
245 245 struct mtd_info *mtd;
246 246  
247   - mtd = &nand_info[id->num];
  247 + mtd = nand_info[id->num];
248 248  
249 249 return mtd->erasesize;
250 250 #else
... ... @@ -116,7 +116,7 @@
116 116 static int set_dev(int dev)
117 117 {
118 118 if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
119   - !nand_info[dev].name) {
  119 + !nand_info[dev]->name) {
120 120 puts("No such device\n");
121 121 return -1;
122 122 }
123 123  
... ... @@ -124,12 +124,12 @@
124 124 if (nand_curr_device == dev)
125 125 return 0;
126 126  
127   - printf("Device %d: %s", dev, nand_info[dev].name);
  127 + printf("Device %d: %s", dev, nand_info[dev]->name);
128 128 puts("... is now current device\n");
129 129 nand_curr_device = dev;
130 130  
131 131 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
132   - board_nand_select_device(nand_info[dev].priv, dev);
  132 + board_nand_select_device(nand_info[dev]->priv, dev);
133 133 #endif
134 134  
135 135 return 0;
... ... @@ -189,7 +189,7 @@
189 189 {
190 190 int ret;
191 191 uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
192   - struct mtd_info *mtd = &nand_info[0];
  192 + struct mtd_info *mtd = nand_info[0];
193 193 char *cmd = argv[1];
194 194  
195 195 if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
... ... @@ -216,7 +216,7 @@
216 216  
217 217 /* We don't care about size, or maxsize. */
218 218 if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
219   - MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
  219 + MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
220 220 puts("Offset or partition name expected\n");
221 221 return 1;
222 222 }
... ... @@ -284,7 +284,7 @@
284 284  
285 285 static void nand_print_and_set_info(int idx)
286 286 {
287   - struct mtd_info *mtd = &nand_info[idx];
  287 + struct mtd_info *mtd = nand_info[idx];
288 288 struct nand_chip *chip = mtd->priv;
289 289  
290 290 printf("Device %d: ", idx);
... ... @@ -349,7 +349,7 @@
349 349 /* We grab the nand info object here fresh because this is usually
350 350 * called after arg_off_size() which can change the value of dev.
351 351 */
352   - struct mtd_info *mtd = &nand_info[dev];
  352 + struct mtd_info *mtd = nand_info[dev];
353 353 loff_t maxoffset = offset + *size;
354 354 int badblocks = 0;
355 355  
... ... @@ -399,7 +399,7 @@
399 399  
400 400 putc('\n');
401 401 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
402   - if (nand_info[i].name)
  402 + if (nand_info[i]->name)
403 403 nand_print_and_set_info(i);
404 404 }
405 405 return 0;
406 406  
... ... @@ -434,11 +434,11 @@
434 434 * for another device is to be used.
435 435 */
436 436 if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
437   - !nand_info[dev].name) {
  437 + !nand_info[dev]->name) {
438 438 puts("\nno devices available\n");
439 439 return 1;
440 440 }
441   - mtd = &nand_info[dev];
  441 + mtd = nand_info[dev];
442 442  
443 443 if (strcmp(cmd, "bad") == 0) {
444 444 printf("\nDevice %d bad blocks:\n", dev);
445 445  
... ... @@ -497,13 +497,13 @@
497 497 /* skip first two or three arguments, look for offset and size */
498 498 if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
499 499 &maxsize, MTD_DEV_TYPE_NAND,
500   - nand_info[dev].size) != 0)
  500 + nand_info[dev]->size) != 0)
501 501 return 1;
502 502  
503 503 if (set_dev(dev))
504 504 return 1;
505 505  
506   - mtd = &nand_info[dev];
  506 + mtd = nand_info[dev];
507 507  
508 508 memset(&opts, 0, sizeof(opts));
509 509 opts.offset = off;
510 510  
... ... @@ -562,13 +562,13 @@
562 562  
563 563 if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
564 564 MTD_DEV_TYPE_NAND,
565   - nand_info[dev].size))
  565 + nand_info[dev]->size))
566 566 return 1;
567 567  
568 568 if (set_dev(dev))
569 569 return 1;
570 570  
571   - mtd = &nand_info[dev];
  571 + mtd = nand_info[dev];
572 572  
573 573 if (argc > 4 && !str2long(argv[4], &pagecount)) {
574 574 printf("'%s' is not a number\n", argv[4]);
... ... @@ -585,7 +585,7 @@
585 585 if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
586 586 &size, &maxsize,
587 587 MTD_DEV_TYPE_NAND,
588   - nand_info[dev].size) != 0)
  588 + nand_info[dev]->size) != 0)
589 589 return 1;
590 590  
591 591 if (set_dev(dev))
... ... @@ -597,7 +597,7 @@
597 597 rwsize = size;
598 598 }
599 599  
600   - mtd = &nand_info[dev];
  600 + mtd = nand_info[dev];
601 601  
602 602 if (!s || !strcmp(s, ".jffs2") ||
603 603 !strcmp(s, ".e") || !strcmp(s, ".i")) {
604 604  
... ... @@ -728,13 +728,13 @@
728 728  
729 729 if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
730 730 &maxsize, MTD_DEV_TYPE_NAND,
731   - nand_info[dev].size) < 0)
  731 + nand_info[dev]->size) < 0)
732 732 return 1;
733 733  
734 734 if (set_dev(dev))
735 735 return 1;
736 736  
737   - if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
  737 + if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
738 738 puts("NAND flash successfully unlocked\n");
739 739 } else {
740 740 puts("Error unlocking NAND flash, "
... ... @@ -915,7 +915,7 @@
915 915 addr = simple_strtoul(argv[1], NULL, 16);
916 916 else
917 917 addr = CONFIG_SYS_LOAD_ADDR;
918   - return nand_load_image(cmdtp, &nand_info[dev->id->num],
  918 + return nand_load_image(cmdtp, nand_info[dev->id->num],
919 919 part->offset, addr, argv[0]);
920 920 }
921 921 }
922 922  
... ... @@ -958,14 +958,14 @@
958 958  
959 959 idx = simple_strtoul(boot_device, NULL, 16);
960 960  
961   - if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
  961 + if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) {
962 962 printf("\n** Device %d not available\n", idx);
963 963 bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
964 964 return 1;
965 965 }
966 966 bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
967 967  
968   - return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
  968 + return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
969 969 }
970 970  
971 971 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
... ... @@ -132,15 +132,15 @@
132 132 size_t blocksize, len;
133 133 u_char *char_ptr;
134 134  
135   - blocksize = nand_info[0].erasesize;
  135 + blocksize = nand_info[0]->erasesize;
136 136 len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
137 137  
138 138 while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
139   - if (nand_block_isbad(&nand_info[0], offset)) {
  139 + if (nand_block_isbad(nand_info[0], offset)) {
140 140 offset += blocksize;
141 141 } else {
142 142 char_ptr = &buf[amount_saved];
143   - if (nand_write(&nand_info[0], offset, &len, char_ptr))
  143 + if (nand_write(nand_info[0], offset, &len, char_ptr))
144 144 return 1;
145 145  
146 146 offset += blocksize;
... ... @@ -164,7 +164,7 @@
164 164 int ret = 0;
165 165  
166 166 printf("Erasing %s...\n", location->name);
167   - if (nand_erase_opts(&nand_info[0], &location->erase_opts))
  167 + if (nand_erase_opts(nand_info[0], &location->erase_opts))
168 168 return 1;
169 169  
170 170 printf("Writing to %s... ", location->name);
171 171  
172 172  
173 173  
... ... @@ -247,20 +247,20 @@
247 247 size_t blocksize, len;
248 248 u_char *char_ptr;
249 249  
250   - blocksize = nand_info[0].erasesize;
  250 + blocksize = nand_info[0]->erasesize;
251 251 if (!blocksize)
252 252 return 1;
253 253  
254 254 len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
255 255  
256 256 while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
257   - if (nand_block_isbad(&nand_info[0], offset)) {
  257 + if (nand_block_isbad(nand_info[0], offset)) {
258 258 offset += blocksize;
259 259 } else {
260 260 char_ptr = &buf[amount_loaded];
261   - if (nand_read_skip_bad(&nand_info[0], offset,
  261 + if (nand_read_skip_bad(nand_info[0], offset,
262 262 &len, NULL,
263   - nand_info[0].size, char_ptr))
  263 + nand_info[0]->size, char_ptr))
264 264 return 1;
265 265  
266 266 offset += blocksize;
... ... @@ -387,7 +387,7 @@
387 387 ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
388 388  
389 389 #if defined(CONFIG_ENV_OFFSET_OOB)
390   - ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
  390 + ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset);
391 391 /*
392 392 * If unable to read environment offset from NAND OOB then fall through
393 393 * to the normal environment reading code below
... ... @@ -62,7 +62,7 @@
62 62 return -EINVAL;
63 63 }
64 64  
65   - *mtd = &nand_info[dev->id->num];
  65 + *mtd = nand_info[dev->id->num];
66 66  
67 67 return 0;
68 68 }
common/splash_source.c
... ... @@ -45,9 +45,9 @@
45 45 #ifdef CONFIG_CMD_NAND
46 46 static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
47 47 {
48   - return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
  48 + return nand_read_skip_bad(nand_info[nand_curr_device], offset,
49 49 &read_size, NULL,
50   - nand_info[nand_curr_device].size,
  50 + nand_info[nand_curr_device]->size,
51 51 (u_char *)bmp_load_addr);
52 52 }
53 53 #else
... ... @@ -136,15 +136,8 @@
136 136 Example of new init to be added to the end of an existing driver
137 137 init:
138 138  
139   - /*
140   - * devnum is the device number to be used in nand commands
141   - * and in mtd->name. Must be less than
142   - * CONFIG_SYS_NAND_MAX_DEVICE.
143   - */
144   - mtd = &nand_info[devnum];
145   -
146 139 /* chip is struct nand_chip, and is now provided by the driver. */
147   - mtd->priv = &chip;
  140 + mtd = &chip.mtd;
148 141  
149 142 /*
150 143 * Fill in appropriate values if this driver uses these fields,
... ... @@ -165,7 +158,11 @@
165 158 if (nand_scan_tail(mtd))
166 159 error out
167 160  
168   - if (nand_register(devnum))
  161 + /*
  162 + * devnum is the device number to be used in nand commands
  163 + * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
  164 + */
  165 + if (nand_register(devnum, mtd))
169 166 error out
170 167  
171 168 In addition to providing more flexibility to the driver, it reduces
drivers/dfu/dfu_nand.c
... ... @@ -39,12 +39,12 @@
39 39  
40 40 if (nand_curr_device < 0 ||
41 41 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
42   - !nand_info[nand_curr_device].name) {
  42 + !nand_info[nand_curr_device]->name) {
43 43 printf("%s: invalid nand device\n", __func__);
44 44 return -1;
45 45 }
46 46  
47   - mtd = &nand_info[nand_curr_device];
  47 + mtd = nand_info[nand_curr_device];
48 48  
49 49 if (op == DFU_OP_READ) {
50 50 ret = nand_read_skip_bad(mtd, start, &count, &actual,
51 51  
... ... @@ -147,12 +147,12 @@
147 147  
148 148 if (nand_curr_device < 0 ||
149 149 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
150   - !nand_info[nand_curr_device].name) {
  150 + !nand_info[nand_curr_device]->name) {
151 151 printf("%s: invalid nand device\n", __func__);
152 152 return -1;
153 153 }
154 154  
155   - mtd = &nand_info[nand_curr_device];
  155 + mtd = nand_info[nand_curr_device];
156 156  
157 157 memset(&opts, 0, sizeof(opts));
158 158 opts.offset = dfu->data.nand.start + dfu->offset +
drivers/mtd/nand/am335x_spl_bch.c
... ... @@ -16,7 +16,7 @@
16 16 #include <linux/mtd/nand_ecc.h>
17 17  
18 18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
19   -struct mtd_info nand_info[1];
  19 +static struct mtd_info *mtd;
20 20 static struct nand_chip nand_chip;
21 21  
22 22 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
23 23  
... ... @@ -30,12 +30,12 @@
30 30 static int nand_command(int block, int page, uint32_t offs,
31 31 u8 cmd)
32 32 {
33   - struct nand_chip *this = nand_info[0].priv;
  33 + struct nand_chip *this = mtd->priv;
34 34 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
35 35 void (*hwctrl)(struct mtd_info *mtd, int cmd,
36 36 unsigned int ctrl) = this->cmd_ctrl;
37 37  
38   - while (!this->dev_ready(&nand_info[0]))
  38 + while (!this->dev_ready(mtd))
39 39 ;
40 40  
41 41 /* Emulate NAND_CMD_READOOB */
42 42  
... ... @@ -45,11 +45,11 @@
45 45 }
46 46  
47 47 /* Begin command latch cycle */
48   - hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  48 + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
49 49  
50 50 if (cmd == NAND_CMD_RESET) {
51   - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
52   - while (!this->dev_ready(&nand_info[0]))
  51 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  52 + while (!this->dev_ready(mtd))
53 53 ;
54 54 return 0;
55 55 }
56 56  
57 57  
58 58  
59 59  
60 60  
61 61  
62 62  
63 63  
64 64  
65 65  
... ... @@ -60,39 +60,39 @@
60 60  
61 61 /* Set ALE and clear CLE to start address cycle */
62 62 /* Column address */
63   - hwctrl(&nand_info[0], offs & 0xff,
  63 + hwctrl(mtd, offs & 0xff,
64 64 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
65   - hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  65 + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
66 66 /* Row address */
67 67 if (cmd != NAND_CMD_RNDOUT) {
68   - hwctrl(&nand_info[0], (page_addr & 0xff),
  68 + hwctrl(mtd, (page_addr & 0xff),
69 69 NAND_CTRL_ALE); /* A[19:12] */
70   - hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
  70 + hwctrl(mtd, ((page_addr >> 8) & 0xff),
71 71 NAND_CTRL_ALE); /* A[27:20] */
72 72 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
73 73 /* One more address cycle for devices > 128MiB */
74   - hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
  74 + hwctrl(mtd, (page_addr >> 16) & 0x0f,
75 75 NAND_CTRL_ALE); /* A[31:28] */
76 76 #endif
77 77 }
78 78  
79   - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  79 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
80 80  
81 81 if (cmd == NAND_CMD_READ0) {
82 82 /* Latch in address */
83   - hwctrl(&nand_info[0], NAND_CMD_READSTART,
  83 + hwctrl(mtd, NAND_CMD_READSTART,
84 84 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
85   - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  85 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
86 86  
87 87 /*
88 88 * Wait a while for the data to be ready
89 89 */
90   - while (!this->dev_ready(&nand_info[0]))
  90 + while (!this->dev_ready(mtd))
91 91 ;
92 92 } else if (cmd == NAND_CMD_RNDOUT) {
93   - hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
  93 + hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
94 94 NAND_CTRL_CHANGE);
95   - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  95 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
96 96 }
97 97  
98 98 return 0;
... ... @@ -100,7 +100,7 @@
100 100  
101 101 static int nand_is_bad_block(int block)
102 102 {
103   - struct nand_chip *this = nand_info[0].priv;
  103 + struct nand_chip *this = mtd->priv;
104 104  
105 105 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
106 106 NAND_CMD_READOOB);
... ... @@ -121,7 +121,7 @@
121 121  
122 122 static int nand_read_page(int block, int page, void *dst)
123 123 {
124   - struct nand_chip *this = nand_info[0].priv;
  124 + struct nand_chip *this = mtd->priv;
125 125 u_char ecc_calc[ECCTOTAL];
126 126 u_char ecc_code[ECCTOTAL];
127 127 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
128 128  
129 129  
... ... @@ -137,15 +137,15 @@
137 137 nand_command(block, page, 0, NAND_CMD_READ0);
138 138  
139 139 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
140   - this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
  140 + this->ecc.hwctl(mtd, NAND_ECC_READ);
141 141 nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
142 142  
143   - this->read_buf(&nand_info[0], p, eccsize);
  143 + this->read_buf(mtd, p, eccsize);
144 144  
145 145 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
146 146  
147   - this->read_buf(&nand_info[0], oob, eccbytes);
148   - this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
  147 + this->read_buf(mtd, oob, eccbytes);
  148 + this->ecc.calculate(mtd, p, &ecc_calc[i]);
149 149  
150 150 data_pos += eccsize;
151 151 oob_pos += eccbytes;
... ... @@ -164,7 +164,7 @@
164 164 * from correct_data(). We just hope that all possible errors
165 165 * are corrected by this routine.
166 166 */
167   - this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
  167 + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
168 168 }
169 169  
170 170 return 0;
171 171  
... ... @@ -223,13 +223,13 @@
223 223 /*
224 224 * Init board specific nand support
225 225 */
226   - nand_info[0].priv = &nand_chip;
  226 + mtd = &nand_chip.mtd;
227 227 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
228 228 (void __iomem *)CONFIG_SYS_NAND_BASE;
229 229 board_nand_init(&nand_chip);
230 230  
231 231 if (nand_chip.select_chip)
232   - nand_chip.select_chip(&nand_info[0], 0);
  232 + nand_chip.select_chip(mtd, 0);
233 233  
234 234 /* NAND chip may require reset after power-on */
235 235 nand_command(0, 0, 0, NAND_CMD_RESET);
... ... @@ -239,6 +239,6 @@
239 239 void nand_deselect(void)
240 240 {
241 241 if (nand_chip.select_chip)
242   - nand_chip.select_chip(&nand_info[0], -1);
  242 + nand_chip.select_chip(mtd, -1);
243 243 }
drivers/mtd/nand/arasan_nfc.c
... ... @@ -1101,7 +1101,7 @@
1101 1101 }
1102 1102  
1103 1103 nand->nand_base = arasan_nand_base;
1104   - mtd = &nand_info[0];
  1104 + mtd = &nand_chip->mtd;
1105 1105 nand_chip->priv = nand;
1106 1106 mtd->priv = nand_chip;
1107 1107  
... ... @@ -1134,7 +1134,7 @@
1134 1134 goto fail;
1135 1135 }
1136 1136  
1137   - if (nand_register(devnum)) {
  1137 + if (nand_register(devnum, mtd)) {
1138 1138 printf("Nand Register Fail\n");
1139 1139 goto fail;
1140 1140 }
drivers/mtd/nand/atmel_nand.c
... ... @@ -1238,17 +1238,17 @@
1238 1238  
1239 1239 #ifdef CONFIG_SPL_BUILD
1240 1240 /* The following code is for SPL */
1241   -static struct mtd_info mtd;
  1241 +static struct mtd_info *mtd;
1242 1242 static struct nand_chip nand_chip;
1243 1243  
1244 1244 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1245 1245 {
1246   - struct nand_chip *this = mtd.priv;
  1246 + struct nand_chip *this = mtd->priv;
1247 1247 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1248 1248 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1249 1249 unsigned int ctrl) = this->cmd_ctrl;
1250 1250  
1251   - while (!this->dev_ready(&mtd))
  1251 + while (!this->dev_ready(mtd))
1252 1252 ;
1253 1253  
1254 1254 if (cmd == NAND_CMD_READOOB) {
1255 1255  
1256 1256  
1257 1257  
1258 1258  
1259 1259  
... ... @@ -1256,24 +1256,24 @@
1256 1256 cmd = NAND_CMD_READ0;
1257 1257 }
1258 1258  
1259   - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1259 + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1260 1260  
1261 1261 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1262 1262 offs >>= 1;
1263 1263  
1264   - hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1265   - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1266   - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1267   - hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
  1264 + hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1265 + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
  1266 + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
  1267 + hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1268 1268 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1269   - hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
  1269 + hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1270 1270 #endif
1271   - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1271 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1272 1272  
1273   - hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1274   - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1273 + hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1274 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1275 1275  
1276   - while (!this->dev_ready(&mtd))
  1276 + while (!this->dev_ready(mtd))
1277 1277 ;
1278 1278  
1279 1279 return 0;
... ... @@ -1281,7 +1281,7 @@
1281 1281  
1282 1282 static int nand_is_bad_block(int block)
1283 1283 {
1284   - struct nand_chip *this = mtd.priv;
  1284 + struct nand_chip *this = mtd->priv;
1285 1285  
1286 1286 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1287 1287  
... ... @@ -1304,7 +1304,7 @@
1304 1304  
1305 1305 static int nand_read_page(int block, int page, void *dst)
1306 1306 {
1307   - struct nand_chip *this = mtd.priv;
  1307 + struct nand_chip *this = mtd->priv;
1308 1308 u_char ecc_calc[ECCTOTAL];
1309 1309 u_char ecc_code[ECCTOTAL];
1310 1310 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1311 1311  
... ... @@ -1317,11 +1317,11 @@
1317 1317  
1318 1318 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1319 1319 if (this->ecc.mode != NAND_ECC_SOFT)
1320   - this->ecc.hwctl(&mtd, NAND_ECC_READ);
1321   - this->read_buf(&mtd, p, eccsize);
1322   - this->ecc.calculate(&mtd, p, &ecc_calc[i]);
  1320 + this->ecc.hwctl(mtd, NAND_ECC_READ);
  1321 + this->read_buf(mtd, p, eccsize);
  1322 + this->ecc.calculate(mtd, p, &ecc_calc[i]);
1323 1323 }
1324   - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  1324 + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1325 1325  
1326 1326 for (i = 0; i < ECCTOTAL; i++)
1327 1327 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1328 1328  
1329 1329  
1330 1330  
1331 1331  
1332 1332  
1333 1333  
1334 1334  
... ... @@ -1330,35 +1330,35 @@
1330 1330 p = dst;
1331 1331  
1332 1332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1333   - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  1333 + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1334 1334  
1335 1335 return 0;
1336 1336 }
1337 1337  
1338 1338 int spl_nand_erase_one(int block, int page)
1339 1339 {
1340   - struct nand_chip *this = mtd.priv;
  1340 + struct nand_chip *this = mtd->priv;
1341 1341 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1342 1342 unsigned int ctrl) = this->cmd_ctrl;
1343 1343 int page_addr;
1344 1344  
1345 1345 if (nand_chip.select_chip)
1346   - nand_chip.select_chip(&mtd, 0);
  1346 + nand_chip.select_chip(mtd, 0);
1347 1347  
1348 1348 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1349   - hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1349 + hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1350 1350 /* Row address */
1351   - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1352   - hwctrl(&mtd, ((page_addr >> 8) & 0xff),
  1351 + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1352 + hwctrl(mtd, ((page_addr >> 8) & 0xff),
1353 1353 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1354 1354 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1355 1355 /* One more address cycle for devices > 128MiB */
1356   - hwctrl(&mtd, (page_addr >> 16) & 0x0f,
  1356 + hwctrl(mtd, (page_addr >> 16) & 0x0f,
1357 1357 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1358 1358 #endif
1359   - hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1359 + hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1360 1360  
1361   - while (!this->dev_ready(&mtd))
  1361 + while (!this->dev_ready(mtd))
1362 1362 ;
1363 1363  
1364 1364 nand_deselect();
1365 1365  
... ... @@ -1368,10 +1368,10 @@
1368 1368 #else
1369 1369 static int nand_read_page(int block, int page, void *dst)
1370 1370 {
1371   - struct nand_chip *this = mtd.priv;
  1371 + struct nand_chip *this = mtd->priv;
1372 1372  
1373 1373 nand_command(block, page, 0, NAND_CMD_READ0);
1374   - atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
  1374 + atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1375 1375  
1376 1376 return 0;
1377 1377 }
... ... @@ -1438,7 +1438,7 @@
1438 1438  
1439 1439 #ifdef CONFIG_ATMEL_NAND_HWECC
1440 1440 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1441   - ret = atmel_pmecc_nand_init_params(nand, &mtd);
  1441 + ret = atmel_pmecc_nand_init_params(nand, mtd);
1442 1442 #endif
1443 1443 #endif
1444 1444  
... ... @@ -1447,9 +1447,10 @@
1447 1447  
1448 1448 void nand_init(void)
1449 1449 {
1450   - mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1451   - mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1452   - mtd.priv = &nand_chip;
  1450 + mtd = &nand_chip.mtd;
  1451 + mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
  1452 + mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
  1453 + mtd->priv = &nand_chip;
1453 1454 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1454 1455 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1455 1456 board_nand_init(&nand_chip);
1456 1457  
... ... @@ -1462,13 +1463,13 @@
1462 1463 #endif
1463 1464  
1464 1465 if (nand_chip.select_chip)
1465   - nand_chip.select_chip(&mtd, 0);
  1466 + nand_chip.select_chip(mtd, 0);
1466 1467 }
1467 1468  
1468 1469 void nand_deselect(void)
1469 1470 {
1470 1471 if (nand_chip.select_chip)
1471   - nand_chip.select_chip(&mtd, -1);
  1472 + nand_chip.select_chip(mtd, -1);
1472 1473 }
1473 1474  
1474 1475 #else
1475 1476  
... ... @@ -1482,8 +1483,8 @@
1482 1483 int atmel_nand_chip_init(int devnum, ulong base_addr)
1483 1484 {
1484 1485 int ret;
1485   - struct mtd_info *mtd = &nand_info[devnum];
1486 1486 struct nand_chip *nand = &nand_chip[devnum];
  1487 + struct mtd_info *mtd = &nand->mtd;
1487 1488  
1488 1489 mtd->priv = nand;
1489 1490 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
... ... @@ -1521,7 +1522,7 @@
1521 1522  
1522 1523 ret = nand_scan_tail(mtd);
1523 1524 if (!ret)
1524   - nand_register(devnum);
  1525 + nand_register(devnum, mtd);
1525 1526  
1526 1527 return ret;
1527 1528 }
drivers/mtd/nand/denali.c
... ... @@ -1263,7 +1263,7 @@
1263 1263 goto fail;
1264 1264 }
1265 1265  
1266   - ret = nand_register(0);
  1266 + ret = nand_register(0, denali->mtd);
1267 1267  
1268 1268 fail:
1269 1269 return ret;
... ... @@ -1282,7 +1282,7 @@
1282 1282 * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
1283 1283 * still provides a "struct mtd_info nand_info" instance.
1284 1284 */
1285   - denali->mtd = &nand_info[0];
  1285 + denali->mtd = &denali->nand.mtd;
1286 1286  
1287 1287 /*
1288 1288 * In the future, these base addresses should be taken from
drivers/mtd/nand/fsl_elbc_nand.c
... ... @@ -656,7 +656,7 @@
656 656  
657 657 static int fsl_elbc_chip_init(int devnum, u8 *addr)
658 658 {
659   - struct mtd_info *mtd = &nand_info[devnum];
  659 + struct mtd_info *mtd;
660 660 struct nand_chip *nand;
661 661 struct fsl_elbc_mtd *priv;
662 662 uint32_t br = 0, or = 0;
... ... @@ -697,6 +697,7 @@
697 697 }
698 698  
699 699 nand = &priv->chip;
  700 + mtd = &nand->mtd;
700 701 mtd->priv = nand;
701 702  
702 703 elbc_ctrl->chips[priv->bank] = priv;
... ... @@ -787,7 +788,7 @@
787 788 if (ret)
788 789 return ret;
789 790  
790   - ret = nand_register(devnum);
  791 + ret = nand_register(devnum, mtd);
791 792 if (ret)
792 793 return ret;
793 794  
drivers/mtd/nand/fsl_ifc_nand.c
... ... @@ -880,7 +880,7 @@
880 880  
881 881 static int fsl_ifc_chip_init(int devnum, u8 *addr)
882 882 {
883   - struct mtd_info *mtd = &nand_info[devnum];
  883 + struct mtd_info *mtd;
884 884 struct nand_chip *nand;
885 885 struct fsl_ifc_mtd *priv;
886 886 struct nand_ecclayout *layout;
... ... @@ -925,6 +925,7 @@
925 925 }
926 926  
927 927 nand = &priv->chip;
  928 + mtd = &nand->mtd;
928 929 mtd->priv = nand;
929 930  
930 931 ifc_ctrl->chips[priv->bank] = priv;
... ... @@ -1044,7 +1045,7 @@
1044 1045 if (ret)
1045 1046 return ret;
1046 1047  
1047   - ret = nand_register(devnum);
  1048 + ret = nand_register(devnum, mtd);
1048 1049 if (ret)
1049 1050 return ret;
1050 1051 return 0;
drivers/mtd/nand/fsmc_nand.c
... ... @@ -409,7 +409,7 @@
409 409 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
410 410 * function, as it doesn't need to switch to a different ECC layout.
411 411 */
412   - mtd = &nand_info[nand_curr_device];
  412 + mtd = nand_info[nand_curr_device];
413 413 nand = mtd->priv;
414 414  
415 415 /* Setup the ecc configurations again */
... ... @@ -443,7 +443,6 @@
443 443 {
444 444 static int chip_nr;
445 445 struct mtd_info *mtd;
446   - int i;
447 446 u32 peripid2 = readl(&fsmc_regs_p->peripid2);
448 447  
449 448 fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
... ... @@ -480,7 +479,7 @@
480 479 (void __iomem *)CONFIG_SYS_NAND_BASE;
481 480 nand->badblockbits = 7;
482 481  
483   - mtd = &nand_info[chip_nr++];
  482 + mtd = &nand->mtd;
484 483 mtd->priv = nand;
485 484  
486 485 switch (fsmc_version) {
... ... @@ -514,9 +513,8 @@
514 513 if (nand_scan_tail(mtd))
515 514 return -ENXIO;
516 515  
517   - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
518   - if (nand_register(i))
519   - return -ENXIO;
  516 + if (nand_register(chip_nr++, mtd))
  517 + return -ENXIO;
520 518  
521 519 return 0;
522 520 }
drivers/mtd/nand/lpc32xx_nand_mlc.c
... ... @@ -539,13 +539,11 @@
539 539  
540 540 void board_nand_init(void)
541 541 {
542   - /* we have only one device anyway */
543   - struct mtd_info *mtd = &nand_info[0];
544   - /* chip is struct nand_chip, and is now provided by the driver. */
545   - mtd->priv = &lpc32xx_chip;
546   - /* to store return status in case we need to print it */
  542 + struct mtd_info *mtd = &lpc32xx_chip.mtd;
547 543 int ret;
548 544  
  545 + mtd->priv = &lpc32xx_chip;
  546 +
549 547 /* Set all BOARDSPECIFIC (actually core-specific) fields */
550 548  
551 549 lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
... ... @@ -597,7 +595,7 @@
597 595 }
598 596  
599 597 /* chip is good, register it */
600   - ret = nand_register(0);
  598 + ret = nand_register(0, mtd);
601 599 if (ret)
602 600 error("nand_register returned %i", ret);
603 601 }
drivers/mtd/nand/mpc5121_nfc.c
... ... @@ -549,7 +549,6 @@
549 549 int resettime = 0;
550 550 int retval = 0;
551 551 int rev;
552   - static int chip_nr = 0;
553 552  
554 553 /*
555 554 * Check SoC revision. This driver supports only NFC
... ... @@ -568,7 +567,7 @@
568 567 return -ENOMEM;
569 568 }
570 569  
571   - mtd = &nand_info[chip_nr++];
  570 + mtd = &chip->mtd;
572 571 mtd->priv = chip;
573 572 chip->priv = prv;
574 573  
drivers/mtd/nand/mxc_nand.c
... ... @@ -1164,7 +1164,7 @@
1164 1164 #endif
1165 1165  
1166 1166 /* structures must be linked */
1167   - mtd = &host->mtd;
  1167 + mtd = &this->mtd;
1168 1168 mtd->priv = this;
1169 1169 host->nand = this;
1170 1170  
drivers/mtd/nand/mxs_nand_spl.c
... ... @@ -8,7 +8,7 @@
8 8 #include <nand.h>
9 9 #include <malloc.h>
10 10  
11   -static struct mtd_info mtd;
  11 +static struct mtd_info *mtd;
12 12 static struct nand_chip nand_chip;
13 13  
14 14 static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
15 15  
... ... @@ -147,14 +147,15 @@
147 147  
148 148 /* init mxs nand driver */
149 149 board_nand_init(&nand_chip);
150   - mtd.priv = &nand_chip;
  150 + mtd = &nand_chip.mtd;
  151 + mtd->priv = &nand_chip;
151 152 /* set mtd functions */
152 153 nand_chip.cmdfunc = mxs_nand_command;
153 154 nand_chip.numchips = 1;
154 155  
155 156 /* identify flash device */
156 157 puts("NAND : ");
157   - if (mxs_flash_ident(&mtd)) {
  158 + if (mxs_flash_ident(mtd)) {
158 159 printf("Failed to identify\n");
159 160 return -1;
160 161 }
161 162  
162 163  
... ... @@ -162,12 +163,12 @@
162 163 /* allocate and initialize buffers */
163 164 nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
164 165 sizeof(*nand_chip.buffers));
165   - nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
  166 + nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
166 167 /* setup flash layout (does not scan as we override that) */
167   - mtd.size = nand_chip.chipsize;
168   - nand_chip.scan_bbt(&mtd);
  168 + mtd->size = nand_chip.chipsize;
  169 + nand_chip.scan_bbt(mtd);
169 170  
170   - printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
  171 + printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
171 172 return 0;
172 173 }
173 174  
174 175  
175 176  
176 177  
177 178  
178 179  
... ... @@ -180,20 +181,20 @@
180 181  
181 182 if (mxs_nand_init())
182 183 return -ENODEV;
183   - chip = mtd.priv;
  184 + chip = mtd->priv;
184 185 page = offs >> chip->page_shift;
185   - nand_page_per_block = mtd.erasesize / mtd.writesize;
  186 + nand_page_per_block = mtd->erasesize / mtd->writesize;
186 187  
187 188 debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
188 189  
189   - size = roundup(size, mtd.writesize);
  190 + size = roundup(size, mtd->writesize);
190 191 while (sz < size) {
191   - if (mxs_read_page_ecc(&mtd, buf, page) < 0)
  192 + if (mxs_read_page_ecc(mtd, buf, page) < 0)
192 193 return -1;
193   - sz += mtd.writesize;
194   - offs += mtd.writesize;
  194 + sz += mtd->writesize;
  195 + offs += mtd->writesize;
195 196 page++;
196   - buf += mtd.writesize;
  197 + buf += mtd->writesize;
197 198  
198 199 /*
199 200 * Check if we have crossed a block boundary, and if so
200 201  
... ... @@ -204,10 +205,10 @@
204 205 * Yes, new block. See if this block is good. If not,
205 206 * loop until we find a good block.
206 207 */
207   - while (is_badblock(&mtd, offs, 1)) {
  208 + while (is_badblock(mtd, offs, 1)) {
208 209 page = page + nand_page_per_block;
209 210 /* Check i we've reached the end of flash. */
210   - if (page >= mtd.size >> chip->page_shift)
  211 + if (page >= mtd->size >> chip->page_shift)
211 212 return -ENOMEM;
212 213 }
213 214 }
drivers/mtd/nand/nand.c
... ... @@ -19,7 +19,7 @@
19 19 int nand_curr_device = -1;
20 20  
21 21  
22   -struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
  22 +struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
23 23  
24 24 #ifndef CONFIG_SYS_NAND_SELF_INIT
25 25 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
26 26  
27 27  
28 28  
... ... @@ -30,15 +30,25 @@
30 30  
31 31 static unsigned long total_nand_size; /* in kiB */
32 32  
33   -/* Register an initialized NAND mtd device with the U-Boot NAND command. */
34   -int nand_register(int devnum)
  33 +int nand_mtd_to_devnum(struct mtd_info *mtd)
35 34 {
36   - struct mtd_info *mtd;
  35 + int i;
37 36  
  37 + for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
  38 + if (mtd && nand_info[i] == mtd)
  39 + return i;
  40 + }
  41 +
  42 + return -ENODEV;
  43 +}
  44 +
  45 +/* Register an initialized NAND mtd device with the U-Boot NAND command. */
  46 +int nand_register(int devnum, struct mtd_info *mtd)
  47 +{
38 48 if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
39 49 return -EINVAL;
40 50  
41   - mtd = &nand_info[devnum];
  51 + nand_info[devnum] = mtd;
42 52  
43 53 sprintf(dev_name[devnum], "nand%d", devnum);
44 54 mtd->name = dev_name[devnum];
45 55  
... ... @@ -62,8 +72,8 @@
62 72 #ifndef CONFIG_SYS_NAND_SELF_INIT
63 73 static void nand_init_chip(int i)
64 74 {
65   - struct mtd_info *mtd = &nand_info[i];
66 75 struct nand_chip *nand = &nand_chip[i];
  76 + struct mtd_info *mtd = &nand->mtd;
67 77 ulong base_addr = base_address[i];
68 78 int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
69 79  
... ... @@ -79,7 +89,7 @@
79 89 if (nand_scan(mtd, maxchips))
80 90 return;
81 91  
82   - nand_register(i);
  92 + nand_register(i, mtd);
83 93 }
84 94 #endif
85 95  
... ... @@ -100,7 +110,8 @@
100 110 /*
101 111 * Select the chip in the board/cpu specific driver
102 112 */
103   - board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
  113 + board_nand_select_device(nand_info[nand_curr_device]->priv,
  114 + nand_curr_device);
104 115 #endif
105 116 }
drivers/mtd/nand/nand_spl_simple.c
... ... @@ -11,7 +11,7 @@
11 11 #include <linux/mtd/nand_ecc.h>
12 12  
13 13 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
14   -static struct mtd_info mtd;
  14 +static struct mtd_info *mtd;
15 15 static struct nand_chip nand_chip;
16 16  
17 17 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
... ... @@ -26,32 +26,32 @@
26 26 static int nand_command(int block, int page, uint32_t offs,
27 27 u8 cmd)
28 28 {
29   - struct nand_chip *this = mtd.priv;
  29 + struct nand_chip *this = mtd->priv();
30 30 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
31 31  
32   - while (!this->dev_ready(&mtd))
  32 + while (!this->dev_ready(mtd))
33 33 ;
34 34  
35 35 /* Begin command latch cycle */
36   - this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  36 + this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
37 37 /* Set ALE and clear CLE to start address cycle */
38 38 /* Column address */
39   - this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
40   - this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
41   - this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
  39 + this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  40 + this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  41 + this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
42 42 NAND_CTRL_ALE); /* A[24:17] */
43 43 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
44 44 /* One more address cycle for devices > 32MiB */
45   - this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
  45 + this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
46 46 NAND_CTRL_ALE); /* A[28:25] */
47 47 #endif
48 48 /* Latch in address */
49   - this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  49 + this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
50 50  
51 51 /*
52 52 * Wait a while for the data to be ready
53 53 */
54   - while (!this->dev_ready(&mtd))
  54 + while (!this->dev_ready(mtd))
55 55 ;
56 56  
57 57 return 0;
58 58  
... ... @@ -63,12 +63,12 @@
63 63 static int nand_command(int block, int page, uint32_t offs,
64 64 u8 cmd)
65 65 {
66   - struct nand_chip *this = mtd.priv;
  66 + struct nand_chip *this = mtd->priv;
67 67 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
68 68 void (*hwctrl)(struct mtd_info *mtd, int cmd,
69 69 unsigned int ctrl) = this->cmd_ctrl;
70 70  
71   - while (!this->dev_ready(&mtd))
  71 + while (!this->dev_ready(mtd))
72 72 ;
73 73  
74 74 /* Emulate NAND_CMD_READOOB */
75 75  
76 76  
77 77  
78 78  
79 79  
... ... @@ -82,30 +82,30 @@
82 82 offs >>= 1;
83 83  
84 84 /* Begin command latch cycle */
85   - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  85 + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
86 86 /* Set ALE and clear CLE to start address cycle */
87 87 /* Column address */
88   - hwctrl(&mtd, offs & 0xff,
89   - NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
90   - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  88 + hwctrl(mtd, offs & 0xff,
  89 + NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  90 + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
91 91 /* Row address */
92   - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
93   - hwctrl(&mtd, ((page_addr >> 8) & 0xff),
94   - NAND_CTRL_ALE); /* A[27:20] */
  92 + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  93 + hwctrl(mtd, ((page_addr >> 8) & 0xff),
  94 + NAND_CTRL_ALE); /* A[27:20] */
95 95 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
96 96 /* One more address cycle for devices > 128MiB */
97   - hwctrl(&mtd, (page_addr >> 16) & 0x0f,
  97 + hwctrl(mtd, (page_addr >> 16) & 0x0f,
98 98 NAND_CTRL_ALE); /* A[31:28] */
99 99 #endif
100 100 /* Latch in address */
101   - hwctrl(&mtd, NAND_CMD_READSTART,
102   - NAND_CTRL_CLE | NAND_CTRL_CHANGE);
103   - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  101 + hwctrl(mtd, NAND_CMD_READSTART,
  102 + NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  103 + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
104 104  
105 105 /*
106 106 * Wait a while for the data to be ready
107 107 */
108   - while (!this->dev_ready(&mtd))
  108 + while (!this->dev_ready(mtd))
109 109 ;
110 110  
111 111 return 0;
... ... @@ -114,7 +114,7 @@
114 114  
115 115 static int nand_is_bad_block(int block)
116 116 {
117   - struct nand_chip *this = mtd.priv;
  117 + struct nand_chip *this = mtd->priv;
118 118 u_char bb_data[2];
119 119  
120 120 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
121 121  
... ... @@ -124,11 +124,11 @@
124 124 * Read one byte (or two if it's a 16 bit chip).
125 125 */
126 126 if (this->options & NAND_BUSWIDTH_16) {
127   - this->read_buf(&mtd, bb_data, 2);
  127 + this->read_buf(mtd, bb_data, 2);
128 128 if (bb_data[0] != 0xff || bb_data[1] != 0xff)
129 129 return 1;
130 130 } else {
131   - this->read_buf(&mtd, bb_data, 1);
  131 + this->read_buf(mtd, bb_data, 1);
132 132 if (bb_data[0] != 0xff)
133 133 return 1;
134 134 }
... ... @@ -139,7 +139,7 @@
139 139 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
140 140 static int nand_read_page(int block, int page, uchar *dst)
141 141 {
142   - struct nand_chip *this = mtd.priv;
  142 + struct nand_chip *this = mtd->priv;
143 143 u_char ecc_calc[ECCTOTAL];
144 144 u_char ecc_code[ECCTOTAL];
145 145 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
... ... @@ -150,7 +150,7 @@
150 150 uint8_t *p = dst;
151 151  
152 152 nand_command(block, page, 0, NAND_CMD_READOOB);
153   - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  153 + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
154 154 nand_command(block, page, 0, NAND_CMD_READ0);
155 155  
156 156 /* Pick the ECC bytes out of the oob data */
... ... @@ -159,10 +159,10 @@
159 159  
160 160  
161 161 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
162   - this->ecc.hwctl(&mtd, NAND_ECC_READ);
163   - this->read_buf(&mtd, p, eccsize);
164   - this->ecc.calculate(&mtd, p, &ecc_calc[i]);
165   - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  162 + this->ecc.hwctl(mtd, NAND_ECC_READ);
  163 + this->read_buf(mtd, p, eccsize);
  164 + this->ecc.calculate(mtd, p, &ecc_calc[i]);
  165 + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
166 166 }
167 167  
168 168 return 0;
... ... @@ -170,7 +170,7 @@
170 170 #else
171 171 static int nand_read_page(int block, int page, void *dst)
172 172 {
173   - struct nand_chip *this = mtd.priv;
  173 + struct nand_chip *this = mtd->priv;
174 174 u_char ecc_calc[ECCTOTAL];
175 175 u_char ecc_code[ECCTOTAL];
176 176 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
177 177  
... ... @@ -184,11 +184,11 @@
184 184  
185 185 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
186 186 if (this->ecc.mode != NAND_ECC_SOFT)
187   - this->ecc.hwctl(&mtd, NAND_ECC_READ);
188   - this->read_buf(&mtd, p, eccsize);
189   - this->ecc.calculate(&mtd, p, &ecc_calc[i]);
  187 + this->ecc.hwctl(mtd, NAND_ECC_READ);
  188 + this->read_buf(mtd, p, eccsize);
  189 + this->ecc.calculate(mtd, p, &ecc_calc[i]);
190 190 }
191   - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  191 + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
192 192  
193 193 /* Pick the ECC bytes out of the oob data */
194 194 for (i = 0; i < ECCTOTAL; i++)
... ... @@ -202,7 +202,7 @@
202 202 * from correct_data(). We just hope that all possible errors
203 203 * are corrected by this routine.
204 204 */
205   - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  205 + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
206 206 }
207 207  
208 208 return 0;
... ... @@ -249,7 +249,8 @@
249 249 /*
250 250 * Init board specific nand support
251 251 */
252   - mtd.priv = &nand_chip;
  252 + mtd = &nand_chip.mtd;
  253 + mtd->priv = &nand_chip;
253 254 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
254 255 (void __iomem *)CONFIG_SYS_NAND_BASE;
255 256 board_nand_init(&nand_chip);
256 257  
... ... @@ -262,13 +263,13 @@
262 263 #endif
263 264  
264 265 if (nand_chip.select_chip)
265   - nand_chip.select_chip(&mtd, 0);
  266 + nand_chip.select_chip(mtd, 0);
266 267 }
267 268  
268 269 /* Unselect after operation */
269 270 void nand_deselect(void)
270 271 {
271 272 if (nand_chip.select_chip)
272   - nand_chip.select_chip(&mtd, -1);
  273 + nand_chip.select_chip(mtd, -1);
273 274 }
drivers/mtd/nand/omap_gpmc.c
... ... @@ -898,12 +898,12 @@
898 898  
899 899 if (nand_curr_device < 0 ||
900 900 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
901   - !nand_info[nand_curr_device].name) {
  901 + !nand_info[nand_curr_device]->name) {
902 902 printf("nand: error: no NAND devices found\n");
903 903 return -ENODEV;
904 904 }
905 905  
906   - mtd = &nand_info[nand_curr_device];
  906 + mtd = nand_info[nand_curr_device];
907 907 nand = mtd->priv;
908 908 nand->options |= NAND_OWN_BUFFERS;
909 909 nand->options &= ~NAND_SUBPAGE_READ;
drivers/mtd/nand/pxa3xx_nand.c
... ... @@ -1477,9 +1477,9 @@
1477 1477  
1478 1478 info->variant = pxa3xx_nand_get_variant();
1479 1479 for (cs = 0; cs < pdata->num_cs; cs++) {
1480   - mtd = &nand_info[cs];
1481 1480 chip = (struct nand_chip *)
1482 1481 ((u8 *)&info[1] + sizeof(*host) * cs);
  1482 + mtd = &chip->mtd;
1483 1483 host = (struct pxa3xx_nand_host *)chip;
1484 1484 info->host[cs] = host;
1485 1485 host->mtd = mtd;
... ... @@ -1573,8 +1573,10 @@
1573 1573 continue;
1574 1574 }
1575 1575  
1576   - if (!ret)
1577   - probe_success = 1;
  1576 + if (nand_register(cs, mtd))
  1577 + continue;
  1578 +
  1579 + probe_success = 1;
1578 1580 }
1579 1581  
1580 1582 if (!probe_success)
... ... @@ -1601,7 +1603,5 @@
1601 1603 ret = pxa3xx_nand_probe(info);
1602 1604 if (ret)
1603 1605 return;
1604   -
1605   - nand_register(0);
1606 1606 }
drivers/mtd/nand/tegra_nand.c
... ... @@ -976,7 +976,7 @@
976 976  
977 977 dm_gpio_set_value(&config->wp_gpio, 1);
978 978  
979   - our_mtd = &nand_info[devnum];
  979 + our_mtd = &nand->mtd;
980 980 our_mtd->priv = nand;
981 981 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
982 982 if (ret)
... ... @@ -989,7 +989,7 @@
989 989 if (ret)
990 990 return ret;
991 991  
992   - ret = nand_register(devnum);
  992 + ret = nand_register(devnum, our_mtd);
993 993 if (ret)
994 994 return ret;
995 995  
drivers/mtd/nand/vf610_nfc.c
... ... @@ -630,7 +630,7 @@
630 630  
631 631 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
632 632 {
633   - struct mtd_info *mtd = &nand_info[devnum];
  633 + struct mtd_info *mtd;
634 634 struct nand_chip *chip;
635 635 struct vf610_nfc *nfc;
636 636 int err = 0;
... ... @@ -653,6 +653,7 @@
653 653 chip = &nfc->chip;
654 654 nfc->regs = addr;
655 655  
  656 + mtd = &chip->mtd;
656 657 mtd->priv = chip;
657 658 chip->priv = nfc;
658 659  
... ... @@ -753,7 +754,7 @@
753 754 if (err)
754 755 return err;
755 756  
756   - err = nand_register(devnum);
  757 + err = nand_register(devnum, mtd);
757 758 if (err)
758 759 return err;
759 760  
... ... @@ -360,7 +360,7 @@
360 360 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
361 361 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
362 362  
363   - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  363 + rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
364 364 &fw_length, (u_char *)addr);
365 365 if (rc == -EUCLEAN) {
366 366 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
drivers/net/phy/cortina.c
... ... @@ -139,8 +139,8 @@
139 139 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
140 140  
141 141 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
142   - ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
143   - &fw_length, (u_char *)addr);
  142 + ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
  143 + &fw_length, (u_char *)addr);
144 144 if (ret == -EUCLEAN) {
145 145 printf("NAND read of Cortina firmware at 0x%x failed %d\n",
146 146 CONFIG_CORTINA_FW_ADDR, ret);
fs/jffs2/jffs2_1pass.c
... ... @@ -195,7 +195,7 @@
195 195 }
196 196  
197 197 retlen = NAND_CACHE_SIZE;
198   - if (nand_read(&nand_info[id->num], nand_cache_off,
  198 + if (nand_read(nand_info[id->num], nand_cache_off,
199 199 &retlen, nand_cache) != 0 ||
200 200 retlen != NAND_CACHE_SIZE) {
201 201 printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
fs/jffs2/jffs2_nand_1pass.c
... ... @@ -796,7 +796,7 @@
796 796 u32 counterN = 0;
797 797  
798 798 struct mtdids *id = part->dev->id;
799   - mtd = nand_info + id->num;
  799 + mtd = nand_info[id->num];
800 800  
801 801 /* if we are building a list we need to refresh the cache. */
802 802 jffs_init_1pass_list(part);
fs/yaffs2/yaffs_uboot_glue.c
... ... @@ -141,8 +141,6 @@
141 141 }
142 142 }
143 143  
144   -extern struct mtd_info nand_info[];
145   -
146 144 void cmd_yaffs_tracemask(unsigned set, unsigned mask)
147 145 {
148 146 if (set)
... ... @@ -171,7 +169,7 @@
171 169 dev = calloc(1, sizeof(*dev));
172 170 mp = strdup(_mp);
173 171  
174   - mtd = &nand_info[flash_dev];
  172 + mtd = nand_info[flash_dev];
175 173  
176 174 if (!dev || !mp) {
177 175 /* Alloc error */
... ... @@ -260,9 +258,7 @@
260 258 dev = yaffs_next_dev();
261 259 if (!dev)
262 260 return;
263   - flash_dev =
264   - ((unsigned) dev->driver_context - (unsigned) nand_info)/
265   - sizeof(nand_info[0]);
  261 + flash_dev = nand_mtd_to_devnum(dev->driver_context);
266 262 printf("%-10s %5d 0x%05x 0x%05x %s",
267 263 dev->param.name, flash_dev,
268 264 dev->param.start_block, dev->param.end_block,
include/linux/mtd/nand.h
... ... @@ -659,6 +659,7 @@
659 659 */
660 660  
661 661 struct nand_chip {
  662 + struct mtd_info mtd;
662 663 void __iomem *IO_ADDR_R;
663 664 void __iomem *IO_ADDR_W;
664 665  
... ... @@ -33,15 +33,17 @@
33 33 #include <linux/mtd/mtd.h>
34 34 #include <linux/mtd/nand.h>
35 35  
  36 +int nand_mtd_to_devnum(struct mtd_info *mtd);
  37 +
36 38 #ifdef CONFIG_SYS_NAND_SELF_INIT
37 39 void board_nand_init(void);
38   -int nand_register(int devnum);
  40 +int nand_register(int devnum, struct mtd_info *mtd);
39 41 #else
40 42 extern int board_nand_init(struct nand_chip *nand);
41 43 #endif
42 44  
43 45 extern int nand_curr_device;
44   -extern struct mtd_info nand_info[];
  46 +extern struct mtd_info *nand_info[];
45 47  
46 48 static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
47 49 u_char *buf)