Eric Lee / smarc-uboot

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Commit b64b5ad11505b79fc9212fa04124addd34792f65

Authored by Adam Ford
Committed by Stefano Babic
1 parent 79ae06ff58
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: DTS: imx6q-logicpd: Update DTS/DTSI files 

The i.MX6 SOM and development kits have undergone significant
updates and changes over the past few months.  This re-sync's
the U-Boot with Logic PD's BSP.

Signed-off-by: Adam Ford <aford173@gmail.com>

Showing 5 changed files with 1060 additions and 461 deletions Side-by-side Diff

arch/arm/dts/imx6-logicpd-baseboard.dtsi
Diff comments   View file @ b64b5ad
  1 +/*
  2 + * Copyright 2018 Logic PD, Inc.
  3 + * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
  4 + *
  5 + * This file is dual-licensed: you can use it either under the terms
  6 + * of the GPL or the X11 license, at your option. Note that this dual
  7 + * licensing only applies to this file, and not this project as a
  8 + * whole.
  9 + *
  10 + * a) This file is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of the
  13 + * License, or (at your option) any later version.
  14 + *
  15 + * This file is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * Or, alternatively,
  21 + *
  22 + * b) Permission is hereby granted, free of charge, to any person
  23 + * obtaining a copy of this software and associated documentation
  24 + * files (the "Software"), to deal in the Software without
  25 + * restriction, including without limitation the rights to use,
  26 + * copy, modify, merge, publish, distribute, sublicense, and/or
  27 + * sell copies of the Software, and to permit persons to whom the
  28 + * Software is furnished to do so, subject to the following
  29 + * conditions:
  30 + *
  31 + * The above copyright notice and this permission notice shall be
  32 + * included in all copies or substantial portions of the Software.
  33 + *
  34 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41 + * OTHER DEALINGS IN THE SOFTWARE.
  42 + */
  43 +
  44 +/ {
  45 + keyboard {
  46 + compatible = "gpio-keys";
  47 +
  48 + btn0 {
  49 + gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
  50 + label = "btn0";
  51 + linux,code = <KEY_WAKEUP>;
  52 + debounce-interval = <10>;
  53 + wakeup-source;
  54 + };
  55 +
  56 + btn1 {
  57 + gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
  58 + label = "btn1";
  59 + linux,code = <KEY_WAKEUP>;
  60 + debounce-interval = <10>;
  61 + wakeup-source;
  62 + };
  63 +
  64 + btn2 {
  65 + gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
  66 + label = "btn2";
  67 + linux,code = <KEY_WAKEUP>;
  68 + debounce-interval = <10>;
  69 + wakeup-source;
  70 + };
  71 + btn3 {
  72 + gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
  73 + label = "btn3";
  74 + linux,code = <KEY_WAKEUP>;
  75 + debounce-interval = <10>;
  76 + wakeup-source;
  77 + };
  78 +
  79 + };
  80 +
  81 + leds {
  82 + compatible = "gpio-leds";
  83 +
  84 + gen_led0 {
  85 + label = "led0";
  86 + pinctrl-names = "default";
  87 + pinctrl-0 = <&pinctrl_led0>;
  88 + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  89 + linux,default-trigger = "cpu0";
  90 + };
  91 +
  92 + gen_led1 {
  93 + label = "led1";
  94 + gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
  95 + };
  96 +
  97 + gen_led2 {
  98 + label = "led2";
  99 + gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
  100 + linux,default-trigger = "heartbeat";
  101 + };
  102 +
  103 + gen_led3 {
  104 + label = "led3";
  105 + gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
  106 + linux,default-trigger = "default-on";
  107 + };
  108 + };
  109 +
  110 + reg_usb_otg_vbus: regulator-otg-vbus@0 {
  111 + compatible = "regulator-fixed";
  112 + regulator-name = "usb_otg_vbus";
  113 + regulator-min-microvolt = <5000000>;
  114 + regulator-max-microvolt = <5000000>;
  115 + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  116 + enable-active-high;
  117 + };
  118 +
  119 + reg_usb_h1_vbus: regulator-usbh1vbus@1 {
  120 + compatible = "regulator-fixed";
  121 + regulator-name = "usb_h1_vbus";
  122 + regulator-min-microvolt = <5000000>;
  123 + regulator-max-microvolt = <5000000>;
  124 + };
  125 +
  126 + reg_3v3: regulator-3v3@2 {
  127 + pinctrl-names = "default";
  128 + pinctrl-0 = <&pinctrl_reg_3v3>;
  129 + compatible = "regulator-fixed";
  130 + regulator-name = "reg_3v3";
  131 + regulator-min-microvolt = <3300000>;
  132 + regulator-max-microvolt = <3300000>;
  133 + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  134 + enable-active-high;
  135 + regulator-always-on;
  136 + };
  137 +
  138 + reg_enet: regulator-ethernet@3 {
  139 + pinctrl-names = "default";
  140 + pinctrl-0 = <&pinctrl_enet_pwr>;
  141 + compatible = "regulator-fixed";
  142 + regulator-name = "ethernet-supply";
  143 + regulator-min-microvolt = <3300000>;
  144 + regulator-max-microvolt = <3300000>;
  145 + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  146 + startup-delay-us = <70000>;
  147 + enable-active-high;
  148 + vin-supply = <&sw4_reg>;
  149 + };
  150 +
  151 + reg_audio: regulator-audio@4 {
  152 + pinctrl-names = "default";
  153 + pinctrl-0 = <&pinctrl_reg_audio>;
  154 + compatible = "regulator-fixed";
  155 + regulator-name = "3v3_aud";
  156 + regulator-min-microvolt = <3300000>;
  157 + regulator-max-microvolt = <3300000>;
  158 + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  159 + enable-active-high;
  160 + regulator-always-on;
  161 + vin-supply = <&reg_3v3>;
  162 + };
  163 +
  164 + reg_hdmi: regulator-hdmi@5 {
  165 + pinctrl-names = "default";
  166 + pinctrl-0 = <&pinctrl_reg_hdmi>;
  167 + compatible = "regulator-fixed";
  168 + regulator-name = "hdmi-supply";
  169 + regulator-min-microvolt = <3300000>;
  170 + regulator-max-microvolt = <3300000>;
  171 + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  172 + enable-active-high;
  173 + vin-supply = <&reg_3v3>;
  174 + };
  175 +
  176 + reg_uart3: regulator-uart3@6 {
  177 + pinctrl-names = "default";
  178 + pinctrl-0 = <&pinctrl_reg_uart3>;
  179 + compatible = "regulator-fixed";
  180 + regulator-name = "uart3-supply";
  181 + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  182 + enable-active-high;
  183 + regulator-always-on;
  184 + vin-supply = <&reg_3v3>;
  185 + };
  186 +
  187 + reg_1v8: regulator-1v8@7 {
  188 + pinctrl-names = "default";
  189 + pinctrl-0 = <&pinctrl_reg_1v8>;
  190 + compatible = "regulator-fixed";
  191 + regulator-name = "1v8-supply";
  192 + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
  193 + enable-active-high;
  194 + regulator-always-on;
  195 + vin-supply = <&reg_3v3>;
  196 + };
  197 +
  198 + reg_pcie: regulator@8 {
  199 + compatible = "regulator-fixed";
  200 + pinctrl-names = "default";
  201 + pinctrl-0 = <&pinctrl_pcie_reg>;
  202 + regulator-name = "MPCIE_3V3";
  203 + regulator-min-microvolt = <3300000>;
  204 + regulator-max-microvolt = <3300000>;
  205 + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  206 + enable-active-high;
  207 + };
  208 +
  209 + mipi_pwr: regulator@9 {
  210 + compatible = "regulator-fixed";
  211 + pinctrl-names = "default";
  212 + pinctrl-0 = <&pinctrl_mipi_pwr>;
  213 + regulator-name = "mipi_pwr_en";
  214 + regulator-min-microvolt = <2800000>;
  215 + regulator-max-microvolt = <2800000>;
  216 + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  217 + enable-active-high;
  218 + };
  219 +
  220 + sound {
  221 + compatible = "fsl,imx-audio-wm8962";
  222 + model = "wm8962-audio";
  223 + ssi-controller = <&ssi2>;
  224 + audio-codec = <&codec>;
  225 + audio-routing =
  226 + "Headphone Jack", "HPOUTL",
  227 + "Headphone Jack", "HPOUTR",
  228 + "Ext Spk", "SPKOUTL",
  229 + "Ext Spk", "SPKOUTR",
  230 + "AMIC", "MICBIAS",
  231 + "IN3R", "AMIC";
  232 + mux-int-port = <2>;
  233 + mux-ext-port = <4>;
  234 + };
  235 +};
  236 +
  237 +&audmux {
  238 + pinctrl-names = "default";
  239 + pinctrl-0 = <&pinctrl_audmux>;
  240 + status = "okay";
  241 +};
  242 +
  243 +&ecspi1 {
  244 + pinctrl-names = "default";
  245 + pinctrl-0 = <&pinctrl_ecspi1>;
  246 + status = "disabled";
  247 +};
  248 +
  249 +&pwm3 {
  250 + pinctrl-names = "default";
  251 + pinctrl-0 = <&pinctrl_pwm3>;
  252 +};
  253 +
  254 +&uart3 {
  255 + pinctrl-names = "default";
  256 + pinctrl-0 = <&pinctrl_uart3>;
  257 + status = "okay";
  258 +};
  259 +
  260 +&usbh1 {
  261 + vbus-supply = <&reg_usb_h1_vbus>;
  262 + status = "okay";
  263 +};
  264 +
  265 +&usbotg {
  266 + vbus-supply = <&reg_usb_otg_vbus>;
  267 + pinctrl-names = "default";
  268 + pinctrl-0 = <&pinctrl_usbotg>;
  269 + disable-over-current;
  270 + status = "okay";
  271 +};
  272 +
  273 +&fec {
  274 + pinctrl-names = "default";
  275 + pinctrl-0 = <&pinctrl_enet>;
  276 + phy-mode = "rgmii";
  277 + phy-reset-duration = <10>;
  278 + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  279 + phy-supply = <&reg_enet>;
  280 + interrupt-parent = <&gpio1>;
  281 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  282 + status = "okay";
  283 +};
  284 +
  285 +&usdhc2 {
  286 + pinctrl-names = "default";
  287 + pinctrl-0 = <&pinctrl_usdhc2>;
  288 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  289 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  290 + no-1-8-v;
  291 + keep-power-in-suspend;
  292 + status = "okay";
  293 +};
  294 +
  295 +&i2c1 {
  296 + pinctrl-names = "default";
  297 + pinctrl-0 = <&pinctrl_i2c1>;
  298 + clock-frequency = <400000>;
  299 + status = "okay";
  300 +
  301 + codec: wm8962@1a {
  302 + compatible = "wlf,wm8962";
  303 + reg = <0x1a>;
  304 + clocks = <&clks IMX6QDL_CLK_CKO>;
  305 + clock-names = "xclk";
  306 + DCVDD-supply = <&reg_audio>;
  307 + DBVDD-supply = <&reg_audio>;
  308 + AVDD-supply = <&reg_audio>;
  309 + CPVDD-supply = <&reg_audio>;
  310 + MICVDD-supply = <&reg_audio>;
  311 + PLLVDD-supply = <&reg_audio>;
  312 + SPKVDD1-supply = <&reg_audio>;
  313 + SPKVDD2-supply = <&reg_audio>;
  314 + gpio-cfg = <
  315 + 0x0000 /* 0:Default */
  316 + 0x0000 /* 1:Default */
  317 + 0x0013 /* 2:FN_DMICCLK */
  318 + 0x0000 /* 3:Default */
  319 + 0x8014 /* 4:FN_DMICCDAT */
  320 + 0x0000 /* 5:Default */
  321 + >;
  322 + };
  323 +};
  324 +
  325 +&i2c3 {
  326 + ov5640: camera@10 {
  327 + compatible = "ovti,ov5640";
  328 + pinctrl-names = "default";
  329 + pinctrl-0 = <&pinctrl_ov5640>;
  330 + reg = <0x10>;
  331 + clocks = <&clks IMX6QDL_CLK_CKO>;
  332 + clock-names = "xclk";
  333 + DOVDD-supply = <&mipi_pwr>;
  334 + AVDD-supply = <&mipi_pwr>;
  335 + DVDD-supply = <&mipi_pwr>;
  336 + reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  337 + powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
  338 +
  339 + port {
  340 + ov5640_to_mipi_csi2: endpoint {
  341 + remote-endpoint = <&mipi_csi2_in>;
  342 + clock-lanes = <0>;
  343 + data-lanes = <1 2>;
  344 + };
  345 + };
  346 + };
  347 +
  348 + pcf8575: gpio@20 {
  349 + pinctrl-names = "default";
  350 + pinctrl-0 = <&pinctrl_pcf8574>;
  351 + compatible = "nxp,pcf8575";
  352 + reg = <0x20>;
  353 + interrupt-parent = <&gpio6>;
  354 + interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
  355 + gpio-controller;
  356 + #gpio-cells = <2>;
  357 + interrupt-controller;
  358 + #interrupt-cells = <2>;
  359 + lines-initial-states = <0x0710>;
  360 + wakeup-source;
  361 + };
  362 +};
  363 +
  364 +&mipi_csi {
  365 + status = "okay";
  366 +
  367 + port@0 {
  368 + reg = <0>;
  369 +
  370 + mipi_csi2_in: endpoint {
  371 + remote-endpoint = <&ov5640_to_mipi_csi2>;
  372 + clock-lanes = <0>;
  373 + data-lanes = <1 2>;
  374 + };
  375 + };
  376 +};
  377 +
  378 +&pcie {
  379 + pinctrl-names = "default";
  380 + pinctrl-0 = <&pinctrl_pcie>;
  381 + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
  382 + status = "okay";
  383 + vpcie-supply = <&reg_pcie>;
  384 + /* fsl,max-link-speed = <2>; */
  385 +};
  386 +
  387 +&ssi2 {
  388 + status = "okay";
  389 +};
  390 +
  391 +&iomuxc {
  392 +
  393 + pinctrl_audmux: audmuxgrp {
  394 + fsl,pins = <
  395 + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
  396 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
  397 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
  398 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
  399 + >;
  400 + };
  401 +
  402 + pinctrl_i2c1: i2c1 {
  403 + fsl,pins = <
  404 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  405 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  406 + >;
  407 + };
  408 +
  409 + pinctrl_enet_pwr: enet_pwr {
  410 + fsl,pins = <
  411 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
  412 + >;
  413 + };
  414 +
  415 + pinctrl_mipi_pwr: pwr_mipi {
  416 + fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
  417 + };
  418 +
  419 + pinctrl_ov5640: ov5640grp {
  420 + fsl,pins = <
  421 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
  422 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1
  423 + >;
  424 + };
  425 +
  426 + pinctrl_reg_hdmi: reg_hdmi {
  427 + fsl,pins = <
  428 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
  429 + >;
  430 + };
  431 +
  432 + pinctrl_uart3: uart3grp {
  433 + fsl,pins = <
  434 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  435 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  436 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  437 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  438 + >;
  439 + };
  440 +
  441 + pinctrl_usbotg: usbotggrp {
  442 + fsl,pins = <
  443 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
  444 + MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
  445 + >;
  446 + };
  447 +
  448 + pinctrl_ecspi1: ecspi1grp {
  449 + fsl,pins = <
  450 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  451 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  452 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  453 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
  454 + >;
  455 + };
  456 +
  457 + pinctrl_usdhc2: usdhc2grp {
  458 + fsl,pins = <
  459 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  460 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
  461 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
  462 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
  463 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
  464 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
  465 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
  466 + >;
  467 + };
  468 +
  469 + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
  470 + fsl,pins = <
  471 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  472 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  473 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  474 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  475 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  476 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  477 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  478 + >;
  479 + };
  480 +
  481 + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
  482 + fsl,pins = <
  483 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  484 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  485 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  486 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  487 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  488 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  489 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  490 + >;
  491 + };
  492 +
  493 + pinctrl_enet: enetgrp {
  494 + fsl,pins = <
  495 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
  496 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  497 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  498 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  499 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  500 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  501 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  502 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  503 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  504 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  505 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  506 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
  507 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
  508 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  509 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  510 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
  511 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
  512 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
  513 + >;
  514 + };
  515 +
  516 + pinctrl_reg_audio: audio-reg {
  517 + fsl,pins = <
  518 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  519 + >;
  520 + };
  521 +
  522 + pinctrl_pcie: pcie {
  523 + fsl,pins = <
  524 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
  525 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  526 + >;
  527 + };
  528 +
  529 + pinctrl_pcie_reg: pciereggrp {
  530 + fsl,pins = <
  531 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  532 + >;
  533 + };
  534 +
  535 + pinctrl_pcf8574: pcf8575-pins {
  536 + fsl,pins = <
  537 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
  538 + >;
  539 + };
  540 +
  541 + pinctrl_lcd: lcdgrp {
  542 + fsl,pins = <
  543 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
  544 + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
  545 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
  546 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
  547 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
  548 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  549 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  550 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  551 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  552 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  553 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  554 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  555 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  556 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  557 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  558 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  559 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  560 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  561 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  562 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  563 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  564 + >;
  565 + };
  566 +
  567 + pinctrl_pwm3: pwm3grp {
  568 + fsl,pins = <
  569 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  570 + >;
  571 + };
  572 +
  573 + pinctrl_reg_uart3: uart3reg {
  574 + fsl,pins = <
  575 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  576 + >;
  577 + };
  578 +
  579 + pinctrl_reg_3v3: reg-3v3 {
  580 + fsl,pins = <
  581 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
  582 + >;
  583 + };
  584 +
  585 + pinctrl_reg_1v8: reg-1v8 {
  586 + fsl,pins = <
  587 + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
  588 + >;
  589 + };
  590 +
  591 + pinctrl_led0: led0 {
  592 + fsl,pins = <
  593 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  594 + >;
  595 + };
  596 +};
arch/arm/dts/imx6-logicpd-som.dtsi
Diff comments   View file @ b64b5ad
  1 +/*
  2 + * Copyright 2018 Logic PD
  3 + * This file is adapted from imx6qdl-sabresd.dtsi.
  4 + * Copyright 2012 Freescale Semiconductor, Inc.
  5 + * Copyright 2011 Linaro Ltd.
  6 + *
  7 + * The code contained herein is licensed under the GNU General Public
  8 + * License. You may obtain a copy of the GNU General Public License
  9 + * Version 2 or later at the following locations:
  10 + *
  11 + * http://www.opensource.org/licenses/gpl-license.html
  12 + * http://www.gnu.org/copyleft/gpl.html
  13 + */
  14 +
  15 +#include <dt-bindings/gpio/gpio.h>
  16 +#include <dt-bindings/input/input.h>
  17 +
  18 +/ {
  19 + chosen {
  20 + stdout-path = &uart1;
  21 + };
  22 +
  23 + memory {
  24 + reg = <0x10000000 0x80000000>;
  25 + };
  26 +
  27 + reg_wl18xx_vmmc: regulator-wl18xx {
  28 + compatible = "regulator-fixed";
  29 + regulator-name = "vwl1837";
  30 + regulator-min-microvolt = <3300000>;
  31 + regulator-max-microvolt = <3300000>;
  32 + gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  33 + startup-delay-us = <70000>;
  34 + enable-active-high;
  35 + };
  36 +};
  37 +
  38 +/* Reroute power feeding the CPU to come from the external PMIC */
  39 +&reg_arm
  40 +{
  41 + vin-supply = <&sw1a_reg>;
  42 +};
  43 +
  44 +&reg_soc
  45 +{
  46 + vin-supply = <&sw1c_reg>;
  47 +};
  48 +
  49 +&clks {
  50 + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  51 + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  52 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  53 + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  54 +};
  55 +
  56 +&gpmi {
  57 + pinctrl-names = "default";
  58 + pinctrl-0 = <&pinctrl_gpmi_nand>;
  59 + status = "okay";
  60 + nand-on-flash-bbt;
  61 +};
  62 +
  63 +&i2c3 {
  64 + clock-frequency = <100000>;
  65 + pinctrl-names = "default";
  66 + pinctrl-0 = <&pinctrl_i2c3>;
  67 + status = "okay";
  68 +
  69 + pmic: pfuze100@08 {
  70 + compatible = "fsl,pfuze100";
  71 + reg = <0x08>;
  72 +
  73 + regulators {
  74 + sw1a_reg: sw1ab {
  75 + regulator-min-microvolt = <725000>;
  76 + regulator-max-microvolt = <1450000>;
  77 + regulator-name = "vddcore";
  78 + regulator-boot-on;
  79 + regulator-always-on;
  80 + regulator-ramp-delay = <6250>;
  81 + };
  82 +
  83 + sw1c_reg: sw1c {
  84 + regulator-min-microvolt = <725000>;
  85 + regulator-max-microvolt = <1450000>;
  86 + regulator-name = "vddsoc";
  87 + regulator-boot-on;
  88 + regulator-always-on;
  89 + regulator-ramp-delay = <6250>;
  90 + };
  91 +
  92 + sw2_reg: sw2 {
  93 + regulator-min-microvolt = <3300000>;
  94 + regulator-max-microvolt = <3300000>;
  95 + regulator-name = "gen_3v3";
  96 + regulator-boot-on;
  97 + /* regulator-always-on; */
  98 + };
  99 +
  100 + sw3a_reg: sw3a {
  101 + regulator-min-microvolt = <400000>;
  102 + regulator-max-microvolt = <1975000>;
  103 + regulator-name = "sw3a_vddr";
  104 + regulator-boot-on;
  105 + regulator-always-on;
  106 + };
  107 +
  108 + sw3b_reg: sw3b {
  109 + regulator-min-microvolt = <400000>;
  110 + regulator-max-microvolt = <1975000>;
  111 + regulator-name = "sw3b_vddr";
  112 + regulator-boot-on;
  113 + regulator-always-on;
  114 + };
  115 +
  116 + sw4_reg: sw4 {
  117 + regulator-min-microvolt = <1800000>;
  118 + regulator-max-microvolt = <3300000>;
  119 + regulator-name = "gen_rgmii";
  120 + };
  121 +
  122 + swbst_reg: swbst {
  123 + regulator-min-microvolt = <5000000>;
  124 + regulator-max-microvolt = <5150000>;
  125 + regulator-name = "gen_5v0";
  126 + };
  127 +
  128 + snvs_reg: vsnvs {
  129 + regulator-min-microvolt = <1000000>;
  130 + regulator-max-microvolt = <3000000>;
  131 + regulator-name = "gen_vsns";
  132 + regulator-boot-on;
  133 + regulator-always-on;
  134 + };
  135 +
  136 + vref_reg: vrefddr {
  137 + regulator-boot-on;
  138 + regulator-always-on;
  139 + };
  140 +
  141 + vgen1_reg: vgen1 {
  142 + regulator-min-microvolt = <1500000>;
  143 + regulator-max-microvolt = <1500000>;
  144 + regulator-name = "gen_1v5";
  145 + };
  146 +
  147 + vgen2_reg: vgen2 {
  148 + regulator-name = "vgen2";
  149 + regulator-min-microvolt = <800000>;
  150 + regulator-max-microvolt = <1550000>;
  151 + };
  152 +
  153 + vgen3_reg: vgen3 {
  154 + regulator-name = "gen_vadj_0";
  155 + regulator-min-microvolt = <3000000>;
  156 + regulator-max-microvolt = <3000000>;
  157 + };
  158 +
  159 + vgen4_reg: vgen4 {
  160 + regulator-name = "gen_1v8";
  161 + regulator-min-microvolt = <1800000>;
  162 + regulator-max-microvolt = <1800000>;
  163 + regulator-always-on;
  164 + };
  165 +
  166 + vgen5_reg: vgen5 {
  167 + regulator-name = "gen_adj_1";
  168 + regulator-min-microvolt = <3300000>;
  169 + regulator-max-microvolt = <3300000>;
  170 + regulator-always-on;
  171 + };
  172 +
  173 + vgen6_reg: vgen6 {
  174 + regulator-name = "gen_2v5";
  175 + regulator-min-microvolt = <2500000>;
  176 + regulator-max-microvolt = <2500000>;
  177 + regulator-always-on;
  178 + };
  179 +
  180 + coin_reg: coin {
  181 + regulator-min-microvolt = <2500000>;
  182 + regulator-max-microvolt = <3000000>;
  183 + regulator-always-on;
  184 + };
  185 + };
  186 + };
  187 +
  188 + temp_sense0: tmp102@4a {
  189 + compatible = "ti,tmp102";
  190 + reg = <0x4a>;
  191 + pinctrl-names = "default";
  192 + pinctrl-0 = <&pinctrl_tempsense>;
  193 + interrupt-parent = <&gpio6>;
  194 + interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
  195 + #thermal-sensor-cells = <1>;
  196 + };
  197 +
  198 + temp_sense1: tmp102@49 {
  199 + compatible = "ti,tmp102";
  200 + reg = <0x49>;
  201 + interrupt-parent = <&gpio6>;
  202 + interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
  203 + #thermal-sensor-cells = <1>;
  204 + };
  205 +
  206 + mfg_eeprom: at24@51 {
  207 + compatible = "atmel,24c64";
  208 + pagesize = <32>;
  209 + read-only;
  210 + reg = <0x51>;
  211 + };
  212 +
  213 + user_eeprom: at24@52 {
  214 + compatible = "atmel,24c64";
  215 + pagesize = <32>;
  216 + reg = <0x52>;
  217 + };
  218 +};
  219 +
  220 +&iomuxc {
  221 + pinctrl-names = "default";
  222 + pinctrl-0 = <&pinctrl_hog>;
  223 +
  224 + pinctrl_hog: hoggrp {
  225 + fsl,pins = <
  226 + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
  227 + MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
  228 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
  229 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
  230 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
  231 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
  232 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
  233 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
  234 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
  235 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
  236 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
  237 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
  238 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
  239 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
  240 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
  241 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
  242 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
  243 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
  244 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
  245 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  246 + >;
  247 + };
  248 +
  249 + pinctrl_gpmi_nand: gpminandgrp {
  250 + fsl,pins = <
  251 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
  252 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
  253 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
  254 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
  255 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
  256 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
  257 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
  258 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
  259 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
  260 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
  261 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
  262 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
  263 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
  264 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
  265 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
  266 + >;
  267 + };
  268 +
  269 + pinctrl_i2c3: i2c3grp {
  270 + fsl,pins = <
  271 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
  272 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
  273 + >;
  274 + };
  275 +
  276 + pinctrl_uart1: uart1grp {
  277 + fsl,pins = <
  278 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  279 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  280 + >;
  281 + };
  282 +
  283 + pinctrl_uart2: uart2grp {
  284 + fsl,pins = <
  285 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
  286 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  287 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  288 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  289 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  290 + >;
  291 + };
  292 +
  293 + pinctrl_usdhc1: usdhc1grp {
  294 + fsl,pins = <
  295 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
  296 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
  297 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
  298 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
  299 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
  300 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
  301 + >;
  302 + };
  303 +
  304 + pinctrl_usdhc3: usdhc3grp {
  305 + fsl,pins = <
  306 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049
  307 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049
  308 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
  309 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
  310 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
  311 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
  312 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
  313 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
  314 + >;
  315 + };
  316 +
  317 + pinctrl_tempsense: tempsensegrp {
  318 + fsl,pins = <
  319 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
  320 + >;
  321 + };
  322 +};
  323 +
  324 +&snvs_poweroff {
  325 + status = "okay";
  326 +};
  327 +
  328 +&uart1 {
  329 + pinctrl-names = "default";
  330 + pinctrl-0 = <&pinctrl_uart1>;
  331 + status = "okay";
  332 +};
  333 +
  334 +&uart2 {
  335 + pinctrl-names = "default";
  336 + pinctrl-0 = <&pinctrl_uart2>;
  337 + status = "okay";
  338 + uart-has-rtscts;
  339 + bluetooth {
  340 + compatible = "ti,wl1837-st";
  341 + enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  342 + };
  343 +};
  344 +
  345 +&usdhc1 {
  346 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  347 + pinctrl-0 = <&pinctrl_usdhc1>;
  348 + non-removable;
  349 + keep-power-in-suspend;
  350 + enable-sdio-wakeup;
  351 + status = "okay";
  352 + vmmc-supply = <&sw2_reg>;
  353 +};
  354 +
  355 +&usdhc3 {
  356 + pinctrl-names = "default";
  357 + pinctrl-0 = <&pinctrl_usdhc3>;
  358 + non-removable;
  359 + cap-power-off-card;
  360 + keep-power-in-suspend;
  361 + wakeup-source;
  362 + vmmc-supply = <&reg_wl18xx_vmmc>;
  363 + status = "okay";
  364 + #address-cells = <1>;
  365 + #size-cells = <0>;
  366 + wlcore: wlcore@2 {
  367 + compatible = "ti,wl1837";
  368 + reg = <2>;
  369 + interrupt-parent = <&gpio7>;
  370 + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  371 + tcxo-clock-frequency = <26000000>;
  372 + };
  373 +};
arch/arm/dts/imx6q-logicpd.dts
Diff comments   View file @ b64b5ad
1 1 /*
2   - * Copyright 2017 Logic PD, Inc.
  2 + * Copyright 2018 Logic PD, Inc.
3 3 * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
4 4 *
5 5 * This file is dual-licensed: you can use it either under the terms
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
28 28  
29 29  
30 30  
... ... @@ -42,149 +42,136 @@
42 42 */
43 43  
44 44 /dts-v1/;
  45 +#include "imx6q.dtsi"
  46 +#include "imx6-logicpd-som.dtsi"
  47 +#include "imx6-logicpd-baseboard.dtsi"
45 48  
46   -#include "imx6qdl-logicpd.dtsi"
47   -
48 49 / {
49   - model = "Logic PD i.MX6QDL SOM";
  50 + model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
50 51 compatible = "fsl,imx6q";
51 52  
52   - reg_usb_otg_vbus: regulator-otg-vbus@0 {
53   - compatible = "regulator-fixed";
54   - regulator-name = "usb_otg_vbus";
55   - regulator-min-microvolt = <5000000>;
56   - regulator-max-microvolt = <5000000>;
57   - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
58   - enable-active-high;
  53 + backlight: backlight_lvds {
  54 + compatible = "pwm-backlight";
  55 + pwms = <&pwm3 0 20000>;
  56 + brightness-levels = <0 4 8 16 32 64 128 255>;
  57 + default-brightness-level = <6>;
  58 + power-supply = <&reg_lcd>;
59 59 };
60 60  
61   - reg_usb_h1_vbus: regulator-usbh1vbus@1 {
  61 + reg_lcd: regulator-lcd {
  62 + pinctrl-names = "default";
  63 + pinctrl-0 = <&pinctrl_lcd_reg>;
62 64 compatible = "regulator-fixed";
63   - regulator-name = "usb_h1_vbus";
64   - regulator-min-microvolt = <5000000>;
65   - regulator-max-microvolt = <5000000>;
  65 + regulator-name = "lcd_panel_pwr";
  66 + regulator-min-microvolt = <3300000>;
  67 + regulator-max-microvolt = <3300000>;
  68 + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
66 69 enable-active-high;
67 70 regulator-always-on;
68   - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
  71 + vin-supply = <&reg_3v3>;
  72 + startup-delay-us = <500000>;
69 73 };
70 74  
71   - reg_3v3: regulator-3v3@2 {
  75 + lcd_reset: lcd_reset {
  76 + pinctrl-names = "default";
  77 + pinctrl-0 = <&pinctrl_lcd_reset>;
72 78 compatible = "regulator-fixed";
73   - regulator-name = "reg_3v3";
  79 + regulator-name = "nLCD_RESET";
74 80 regulator-min-microvolt = <3300000>;
75 81 regulator-max-microvolt = <3300000>;
  82 + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  83 + enable-active-high;
  84 + regulator-always-on;
  85 + vin-supply = <&reg_lcd>;
76 86 };
  87 +
  88 + panel-lvds0 {
  89 + compatible = "ampire,am800480b3tmqw";
  90 + backlight = <&backlight>;
  91 +
  92 + port {
  93 + panel_in_lvds0: endpoint {
  94 + remote-endpoint = <&lvds0_out>;
  95 + };
  96 + };
  97 + };
77 98 };
78 99  
79   -&uart3 {
80   - pinctrl-names = "default";
81   - pinctrl-0 = <&pinctrl_uart3>;
  100 +&hdmi {
  101 + ddc-i2c-bus = <&i2c3>;
82 102 status = "okay";
83 103 };
84 104  
85   -&usbh1 {
86   - pinctrl-names = "default";
87   - pinctrl-0 = <&pinctrl_usbh1>;
88   - vbus-supply = <&reg_usb_h1_vbus>;
89   - status = "okay";
  105 +&i2c1 {
  106 + ili_touch: ilitouch@26 {
  107 + compatible = "ili,ili2117a";
  108 + reg = <0x26>;
  109 + pinctrl-names = "default";
  110 + pinctrl-0 = <&pinctrl_touchscreen>;
  111 + interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
  112 + ili2117a,poll-period = <10>;
  113 + ili2117a,max-touch = <2>;
  114 + };
90 115 };
91 116  
92   -&usbh2 {
93   - pinctrl-names = "default";
94   - pinctrl-0 = <&pinctrl_usbh2>;
95   - phy_type = "hsic";
96   - disable-over-current;
97   - status = "okay";
  117 +&reg_hdmi {
  118 + regulator-always-on;
98 119 };
99 120  
100   -&usbotg {
101   - vbus-supply = <&reg_usb_otg_vbus>;
102   - pinctrl-names = "default";
103   - pinctrl-0 = <&pinctrl_usbotg>;
104   - disable-over-current;
  121 +&ldb {
105 122 status = "okay";
  123 +
  124 + lvds-channel@0 {
  125 + fsl,data-mapping = "spwg";
  126 + fsl,data-width = <24>;
  127 + status = "okay";
  128 +
  129 + port@4 {
  130 + reg = <4>;
  131 +
  132 + lvds0_out: endpoint {
  133 + remote-endpoint = <&panel_in_lvds0>;
  134 + };
  135 + };
  136 + };
  137 +
106 138 };
107 139  
108   -&fec {
109   - pinctrl-names = "default";
110   - pinctrl-0 = <&pinctrl_enet>;
111   - phy-mode = "rmii";
112   - phy-speed = <10>;
  140 +&clks {
  141 + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  142 + <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
  143 + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
  144 + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
  145 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
  146 + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
  147 + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  148 + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
  149 +};
  150 +
  151 +&pwm3 {
113 152 status = "okay";
114 153 };
115 154  
116 155 &usdhc2 {
117   - pinctrl-names = "default";
118   - pinctrl-0 = <&pinctrl_usdhc2>;
119 156 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
120   - no-1-8-v;
121   - keep-power-in-suspend;
122   - status = "okay";
123 157 };
124 158  
125 159 &iomuxc {
126   - pinctrl_enet: enetgrp {
  160 + pinctrl_lcd_reg: lcdreg {
127 161 fsl,pins = <
128   - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
129   - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
130   - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
131   - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
132   - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
133   - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
134   - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
135   - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
136   - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
137   - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
138   - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */
139   - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */
  162 + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
140 163 >;
141 164 };
142 165  
143   - pinctrl_gpio_leds: gpioledsgrp {
  166 + pinctrl_lcd_reset: lcdreset {
144 167 fsl,pins = <
145   - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0
146   - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0
147   - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0
148   - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
  168 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
149 169 >;
150 170 };
151   - pinctrl_uart3: uart3grp {
152   - fsl,pins = <
153   - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
154   - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
155   - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
156   - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
157   - >;
158   - };
159 171  
160   - pinctrl_usbh1: usbh1grp {
  172 + pinctrl_touchscreen: touchscreengrp {
161 173 fsl,pins = <
162   - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */
163   - >;
164   - };
165   -
166   - pinctrl_usbh2: usbh2grp {
167   - fsl,pins = <
168   - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030
169   - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030
170   - >;
171   - };
172   -
173   - pinctrl_usbotg: usbotggrp {
174   - fsl,pins = <
175   - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
176   - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */
177   - >;
178   - };
179   -
180   - pinctrl_usdhc2: usdhc2grp {
181   - fsl,pins = <
182   - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
183   - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
184   - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
185   - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
186   - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
187   - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  174 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */
188 175 >;
189 176 };
190 177 };
arch/arm/dts/imx6qdl-logicpd.dtsi
View file @ b64b5ad
1   -/*
2   - * Copyright 2016 Logic PD
3   - * This file is adapted from imx6qdl-sabresd.dtsi.
4   - * Copyright 2012 Freescale Semiconductor, Inc.
5   - * Copyright 2011 Linaro Ltd.
6   - *
7   - * The code contained herein is licensed under the GNU General Public
8   - * License. You may obtain a copy of the GNU General Public License
9   - * Version 2 or later at the following locations:
10   - *
11   - * http://www.opensource.org/licenses/gpl-license.html
12   - * http://www.gnu.org/copyleft/gpl.html
13   - */
14   -
15   -#include <dt-bindings/gpio/gpio.h>
16   -#include <dt-bindings/input/input.h>
17   -#include "imx6q.dtsi"
18   -
19   -/ {
20   - chosen {
21   - stdout-path = &uart1;
22   - };
23   -
24   - memory {
25   - reg = <0x10000000 0x80000000>;
26   - };
27   -};
28   -
29   -/* Reroute power feeding the CPU to come from the external PMIC */
30   -&reg_arm
31   -{
32   - vin-supply = <&sw1a_reg>;
33   -};
34   -
35   -&reg_soc
36   -{
37   - vin-supply = <&sw1c_reg>;
38   -};
39   -
40   -&clks {
41   - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
42   - <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
43   - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
44   - <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
45   -};
46   -
47   -&i2c3 {
48   - clock-frequency = <100000>;
49   - pinctrl-names = "default";
50   - pinctrl-0 = <&pinctrl_i2c3>;
51   - status = "okay";
52   -
53   - pmic: pfuze100@08 {
54   - compatible = "fsl,pfuze100";
55   - reg = <0x08>;
56   -
57   - regulators {
58   - sw1a_reg: sw1ab {
59   - regulator-min-microvolt = <725000>;
60   - regulator-max-microvolt = <1450000>;
61   - regulator-name = "vddcore";
62   - regulator-boot-on;
63   - regulator-always-on;
64   - regulator-ramp-delay = <6250>;
65   - };
66   -
67   - sw1c_reg: sw1c {
68   - regulator-min-microvolt = <725000>;
69   - regulator-max-microvolt = <1450000>;
70   - regulator-name = "vddsoc";
71   - regulator-boot-on;
72   - regulator-always-on;
73   - regulator-ramp-delay = <6250>;
74   - };
75   -
76   - sw2_reg: sw2 {
77   - regulator-min-microvolt = <3300000>;
78   - regulator-max-microvolt = <3300000>;
79   - regulator-name = "gen_3v3";
80   - regulator-boot-on;
81   - regulator-always-on;
82   - };
83   -
84   - sw3a_reg: sw3a {
85   - regulator-min-microvolt = <400000>;
86   - regulator-max-microvolt = <1975000>;
87   - regulator-name = "sw3a_vddr";
88   - regulator-boot-on;
89   - regulator-always-on;
90   - };
91   -
92   - sw3b_reg: sw3b {
93   - regulator-min-microvolt = <400000>;
94   - regulator-max-microvolt = <1975000>;
95   - regulator-name = "sw3b_vddr";
96   - regulator-boot-on;
97   - regulator-always-on;
98   - };
99   -
100   - sw4_reg: sw4 {
101   - regulator-min-microvolt = <800000>;
102   - regulator-max-microvolt = <3300000>;
103   - regulator-name = "gen_rgmii";
104   - };
105   -
106   -
107   - swbst_reg: swbst {
108   - regulator-min-microvolt = <5000000>;
109   - regulator-max-microvolt = <5150000>;
110   - regulator-name = "gen_5v0";
111   - };
112   -
113   - snvs_reg: vsnvs {
114   - regulator-min-microvolt = <1000000>;
115   - regulator-max-microvolt = <3000000>;
116   - regulator-name = "gen_vsns";
117   - regulator-boot-on;
118   - regulator-always-on;
119   - };
120   -
121   - vref_reg: vrefddr {
122   - regulator-boot-on;
123   - regulator-always-on;
124   - };
125   -
126   - vgen1_reg: vgen1 {
127   - regulator-min-microvolt = <1500000>;
128   - regulator-max-microvolt = <1500000>;
129   - regulator-name = "gen_1v5";
130   - };
131   -
132   - vgen2_reg: vgen2 {
133   - regulator-name = "vgen2";
134   - regulator-min-microvolt = <800000>;
135   - regulator-max-microvolt = <1550000>;
136   - };
137   -
138   - vgen3_reg: vgen3 {
139   - regulator-name = "gen_vadj_0";
140   - regulator-min-microvolt = <3000000>;
141   - regulator-max-microvolt = <3000000>;
142   - };
143   -
144   - vgen4_reg: vgen4 {
145   - regulator-name = "gen_1v8";
146   - regulator-min-microvolt = <1800000>;
147   - regulator-max-microvolt = <1800000>;
148   - regulator-always-on;
149   - };
150   -
151   - vgen5_reg: vgen5 {
152   - regulator-name = "gen_adj_1";
153   - regulator-min-microvolt = <3300000>;
154   - regulator-max-microvolt = <3300000>;
155   - regulator-always-on;
156   - };
157   -
158   - vgen6_reg: vgen6 {
159   - regulator-name = "gen_2v5";
160   - regulator-min-microvolt = <2500000>;
161   - regulator-max-microvolt = <2500000>;
162   - regulator-always-on;
163   - };
164   - };
165   - };
166   -
167   - mfg_eeprom: at24@51 {
168   - compatible = "atmel,24c64";
169   - pagesize = <32>;
170   - read-only;
171   - reg = <0x51>;
172   - };
173   -
174   - user_eeprom: at24@52 {
175   - compatible = "atmel,24c64";
176   - pagesize = <32>;
177   - reg = <0x52>;
178   - };
179   -};
180   -
181   -&iomuxc {
182   - pinctrl-names = "default";
183   - pinctrl-0 = <&pinctrl_hog>;
184   -
185   - pinctrl_hog: hoggrp {
186   - fsl,pins = <
187   - MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
188   - MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
189   - MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
190   - MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
191   - MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
192   - MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
193   - MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
194   - MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
195   - MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
196   - MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
197   - MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
198   - MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
199   - MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
200   - MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
201   - MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
202   - MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
203   - MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
204   - MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
205   - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0
206   - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000
207   - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
208   - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000
209   - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
210   - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
211   - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
212   - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
213   - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
214   - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000
215   - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
216   - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000
217   - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
218   - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
219   - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
220   - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
221   - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000
222   - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000
223   - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000
224   - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000
225   - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
226   - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
227   - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000
228   - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000
229   - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
230   - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
231   - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000
232   - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000
233   - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000
234   - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
235   - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000
236   - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000
237   - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
238   - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
239   - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
240   - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000
241   - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
242   - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
243   - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000
244   - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
245   - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
246   - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
247   - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
248   - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000
249   - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
250   - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
251   - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
252   - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
253   - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
254   - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
255   - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
256   - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000
257   - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000
258   - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
259   - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000
260   - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
261   - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
262   - MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000
263   - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000
264   - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000
265   - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000
266   - MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000
267   - MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000
268   - MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000
269   - MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000
270   - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000
271   - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
272   - >;
273   - };
274   -
275   - pinctrl_i2c3: i2c3grp {
276   - fsl,pins = <
277   - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
278   - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
279   - >;
280   - };
281   -
282   - pinctrl_uart1: uart1grp {
283   - fsl,pins = <
284   - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
285   - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
286   - >;
287   - };
288   -
289   - pinctrl_uart2: uart2grp {
290   - fsl,pins = <
291   - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
292   - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
293   - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
294   - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
295   - >;
296   - };
297   -
298   - pinctrl_usdhc1: usdhc1grp {
299   - fsl,pins = <
300   - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
301   - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
302   - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
303   - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
304   - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
305   - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
306   - >;
307   - };
308   -
309   - pinctrl_usdhc3: usdhc3grp {
310   - fsl,pins = <
311   - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
312   - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
313   - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
314   - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
315   - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
316   - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
317   - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */
318   - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */
319   - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */
320   - >;
321   - };
322   -};
323   -
324   -&uart1 {
325   - pinctrl-names = "default";
326   - pinctrl-0 = <&pinctrl_uart1>;
327   - status = "okay";
328   -};
329   -
330   -&uart2 {
331   - pinctrl-names = "default";
332   - pinctrl-0 = <&pinctrl_uart2>;
333   - status = "okay";
334   -};
335   -
336   -&usdhc1 {
337   - pinctrl-names = "default";
338   - pinctrl-0 = <&pinctrl_usdhc1>;
339   - cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
340   - keep-power-in-suspend;
341   - enable-sdio-wakeup;
342   - status = "okay";
343   -};
344   -
345   -&usdhc3 {
346   - pinctrl-names = "default";
347   - pinctrl-0 = <&pinctrl_usdhc3>;
348   - non-removable;
349   - keep-power-in-suspend;
350   - enable-sdio-wakeup;
351   - vmmc-supply = <&sw2_reg>;
352   - status = "okay";
353   - #address-cells = <1>;
354   - #size-cells = <0>;
355   - wlcore: wlcore@0 {
356   - compatible = "ti,wl1837";
357   - reg = <2>;
358   - interrupt-parent = <&gpio7>;
359   - interrupts = <1 GPIO_ACTIVE_HIGH>;
360   - };
361   -};
board/logicpd/imx6/MAINTAINERS
Diff comments   View file @ b64b5ad
... ... @@ -4,4 +4,7 @@
4 4 F: board/logicpd/imx6/
5 5 F: include/configs/imx6_logic.h
6 6 F: configs/imx6q_logic_defconfig
  7 +F: arch/arm/dts/imx6-logicpd-baseboard.dtsi
  8 +F: arch/arm/dts/imx6-logicpd-som.dtsi
  9 +F: arch/arm/dts/imx6q-logicpd.dts