Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit b653516769160a7ba5bb4318c014535e063fdc0b

Authored by Albert ARIBAUD
2 parents 681f785f7c 5cecf21fb1
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Showing 44 changed files Side-by-side Diff

arch/arm/cpu/armv7/exynos/Kconfig
Diff comments   View file @ b653516
... ... @@ -18,6 +18,9 @@
18 18 config TARGET_TRATS2
19 19 bool "Exynos4412 Trat2 board"
20 20  
  21 +config TARGET_ODROID
  22 + bool "Exynos4412 Odroid board"
  23 +
21 24 config TARGET_ARNDALE
22 25 bool "Exynos5250 Arndale board"
23 26  
... ... @@ -48,6 +51,7 @@
48 51 source "board/samsung/universal_c210/Kconfig"
49 52 source "board/samsung/origen/Kconfig"
50 53 source "board/samsung/trats2/Kconfig"
  54 +source "board/samsung/odroid/Kconfig"
51 55 source "board/samsung/arndale/Kconfig"
52 56 source "board/samsung/smdk5250/Kconfig"
53 57 source "board/samsung/smdk5420/Kconfig"
arch/arm/cpu/armv7/exynos/clock.c
Diff comments   View file @ b653516
... ... @@ -82,7 +82,8 @@
82 82 * VPLL_CON: MIDV [24:16]
83 83 * BPLL_CON: MIDV [25:16]: Exynos5
84 84 */
85   - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
  85 + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
  86 + pllreg == SPLL)
86 87 mask = 0x3ff;
87 88 else
88 89 mask = 0x1ff;
... ... @@ -391,6 +392,9 @@
391 392 r = readl(&clk->rpll_con0);
392 393 k = readl(&clk->rpll_con1);
393 394 break;
  395 + case SPLL:
  396 + r = readl(&clk->spll_con0);
  397 + break;
394 398 default:
395 399 printf("Unsupported PLL (%d)\n", pllreg);
396 400 return 0;
... ... @@ -1027,6 +1031,40 @@
1027 1031 return pclk;
1028 1032 }
1029 1033  
  1034 +static unsigned long exynos5420_get_lcd_clk(void)
  1035 +{
  1036 + struct exynos5420_clock *clk =
  1037 + (struct exynos5420_clock *)samsung_get_base_clock();
  1038 + unsigned long pclk, sclk;
  1039 + unsigned int sel;
  1040 + unsigned int ratio;
  1041 +
  1042 + /*
  1043 + * CLK_SRC_DISP10
  1044 + * FIMD1_SEL [4]
  1045 + * 0: SCLK_RPLL
  1046 + * 1: SCLK_SPLL
  1047 + */
  1048 + sel = readl(&clk->src_disp10);
  1049 + sel &= (1 << 4);
  1050 +
  1051 + if (sel)
  1052 + sclk = get_pll_clk(SPLL);
  1053 + else
  1054 + sclk = get_pll_clk(RPLL);
  1055 +
  1056 + /*
  1057 + * CLK_DIV_DISP10
  1058 + * FIMD1_RATIO [3:0]
  1059 + */
  1060 + ratio = readl(&clk->div_disp10);
  1061 + ratio = ratio & 0xf;
  1062 +
  1063 + pclk = sclk / (ratio + 1);
  1064 +
  1065 + return pclk;
  1066 +}
  1067 +
1030 1068 void exynos4_set_lcd_clk(void)
1031 1069 {
1032 1070 struct exynos4_clock *clk =
... ... @@ -1131,6 +1169,33 @@
1131 1169 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1132 1170 }
1133 1171  
  1172 +void exynos5420_set_lcd_clk(void)
  1173 +{
  1174 + struct exynos5420_clock *clk =
  1175 + (struct exynos5420_clock *)samsung_get_base_clock();
  1176 + unsigned int cfg;
  1177 +
  1178 + /*
  1179 + * CLK_SRC_DISP10
  1180 + * FIMD1_SEL [4]
  1181 + * 0: SCLK_RPLL
  1182 + * 1: SCLK_SPLL
  1183 + */
  1184 + cfg = readl(&clk->src_disp10);
  1185 + cfg &= ~(0x1 << 4);
  1186 + cfg |= (0 << 4);
  1187 + writel(cfg, &clk->src_disp10);
  1188 +
  1189 + /*
  1190 + * CLK_DIV_DISP10
  1191 + * FIMD1_RATIO [3:0]
  1192 + */
  1193 + cfg = readl(&clk->div_disp10);
  1194 + cfg &= ~(0xf << 0);
  1195 + cfg |= (0 << 0);
  1196 + writel(cfg, &clk->div_disp10);
  1197 +}
  1198 +
1134 1199 void exynos4_set_mipi_clk(void)
1135 1200 {
1136 1201 struct exynos4_clock *clk =
1137 1202  
... ... @@ -1602,16 +1667,24 @@
1602 1667 {
1603 1668 if (cpu_is_exynos4())
1604 1669 return exynos4_get_lcd_clk();
1605   - else
1606   - return exynos5_get_lcd_clk();
  1670 + else {
  1671 + if (proid_is_exynos5420())
  1672 + return exynos5420_get_lcd_clk();
  1673 + else
  1674 + return exynos5_get_lcd_clk();
  1675 + }
1607 1676 }
1608 1677  
1609 1678 void set_lcd_clk(void)
1610 1679 {
1611 1680 if (cpu_is_exynos4())
1612 1681 exynos4_set_lcd_clk();
1613   - else
1614   - exynos5_set_lcd_clk();
  1682 + else {
  1683 + if (proid_is_exynos5250())
  1684 + exynos5_set_lcd_clk();
  1685 + else if (proid_is_exynos5420())
  1686 + exynos5420_set_lcd_clk();
  1687 + }
1615 1688 }
1616 1689  
1617 1690 void set_mipi_clk(void)
arch/arm/cpu/armv7/exynos/clock_init.h
Diff comments   View file @ b653516
... ... @@ -75,6 +75,9 @@
75 75 unsigned spll_mdiv;
76 76 unsigned spll_pdiv;
77 77 unsigned spll_sdiv;
  78 + unsigned rpll_mdiv;
  79 + unsigned rpll_pdiv;
  80 + unsigned rpll_sdiv;
78 81 unsigned pclk_cdrex_ratio;
79 82 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
80 83  
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
Diff comments   View file @ b653516
... ... @@ -179,6 +179,10 @@
179 179 .spll_mdiv = 0xc8,
180 180 .spll_pdiv = 0x3,
181 181 .spll_sdiv = 0x2,
  182 + /* RPLL @70.5Mhz */
  183 + .rpll_mdiv = 0x5E,
  184 + .rpll_pdiv = 0x2,
  185 + .rpll_sdiv = 0x4,
182 186  
183 187 .direct_cmd_msr = {
184 188 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
... ... @@ -800,6 +804,7 @@
800 804 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
801 805 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
802 806 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
  807 + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
803 808  
804 809 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
805 810  
... ... @@ -896,6 +901,14 @@
896 901 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
897 902 writel(val, &clk->spll_con0);
898 903 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
  904 + ;
  905 +
  906 + /* Set RPLL */
  907 + writel(RPLL_CON2_VAL, &clk->rpll_con2);
  908 + writel(RPLL_CON1_VAL, &clk->rpll_con1);
  909 + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
  910 + writel(val, &clk->rpll_con0);
  911 + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
899 912 ;
900 913  
901 914 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
arch/arm/cpu/armv7/exynos/exynos5_setup.h
Diff comments   View file @ b653516
... ... @@ -783,7 +783,7 @@
783 783 #define CLK_SRC_TOP2_VAL 0x11101000
784 784 #define CLK_SRC_TOP3_VAL 0x11111111
785 785 #define CLK_SRC_TOP4_VAL 0x11110111
786   -#define CLK_SRC_TOP5_VAL 0x11111100
  786 +#define CLK_SRC_TOP5_VAL 0x11111101
787 787 #define CLK_SRC_TOP6_VAL 0x11110111
788 788 #define CLK_SRC_TOP7_VAL 0x00022200
789 789  
arch/arm/cpu/armv7/exynos/pinmux.c
Diff comments   View file @ b653516
... ... @@ -704,8 +704,8 @@
704 704 ext_func = S5P_GPIO_FUNC(0x3);
705 705 break;
706 706 case PERIPH_ID_SDMMC4:
707   - start = EXYNOS4_GPIO_K00;
708   - start_ext = EXYNOS4_GPIO_K13;
  707 + start = EXYNOS4X12_GPIO_K00;
  708 + start_ext = EXYNOS4X12_GPIO_K13;
709 709 func = S5P_GPIO_FUNC(0x3);
710 710 ext_func = S5P_GPIO_FUNC(0x4);
711 711 break;
arch/arm/cpu/armv7/exynos/power.c
Diff comments   View file @ b653516
... ... @@ -202,4 +202,11 @@
202 202 else
203 203 exynos4_power_exit_wakeup();
204 204 }
  205 +
  206 +unsigned int get_boot_mode(void)
  207 +{
  208 + unsigned int om_pin = samsung_get_base_power();
  209 +
  210 + return readl(om_pin) & OM_PIN_MASK;
  211 +}
arch/arm/cpu/armv7/exynos/spl_boot.c
Diff comments   View file @ b653516
... ... @@ -20,7 +20,6 @@
20 20 #include "clock_init.h"
21 21  
22 22 DECLARE_GLOBAL_DATA_PTR;
23   -#define OM_STAT (0x1f << 1)
24 23  
25 24 /* Index into irom ptr table */
26 25 enum index {
... ... @@ -184,7 +183,7 @@
184 183 */
185 184 void copy_uboot_to_ram(void)
186 185 {
187   - enum boot_mode bootmode = BOOT_MODE_OM;
  186 + unsigned int bootmode = BOOT_MODE_OM;
188 187  
189 188 u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
190 189 u32 offset = 0, size = 0;
... ... @@ -207,7 +206,7 @@
207 206 #endif
208 207  
209 208 if (bootmode == BOOT_MODE_OM)
210   - bootmode = readl(samsung_get_base_power()) & OM_STAT;
  209 + bootmode = get_boot_mode();
211 210  
212 211 switch (bootmode) {
213 212 #ifdef CONFIG_SPI_BOOTING
... ... @@ -216,7 +215,7 @@
216 215 exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
217 216 break;
218 217 #endif
219   - case BOOT_MODE_MMC:
  218 + case BOOT_MODE_SD:
220 219 offset = BL2_START_OFFSET;
221 220 size = BL2_SIZE_BLOC_COUNT;
222 221 copy_bl2 = get_irom_func(MMC_INDEX);
arch/arm/dts/Makefile
Diff comments   View file @ b653516
1 1 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
2 2 exynos4210-universal_c210.dtb \
3 3 exynos4210-trats.dtb \
4   - exynos4412-trats2.dtb
  4 + exynos4412-trats2.dtb \
  5 + exynos4412-odroid.dtb
5 6  
6 7 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
7 8 exynos5250-snow.dtb \
arch/arm/dts/exynos4412-odroid.dts
Diff comments   View file @ b653516
  1 +/*
  2 + * Odroid-U3/X2 board device tree source
  3 + *
  4 + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  5 + * http://www.samsung.com
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +/dts-v1/;
  11 +/include/ "exynos4.dtsi"
  12 +
  13 +/ {
  14 + model = "Odroid based on Exynos4412";
  15 + compatible = "samsung,odroid", "samsung,exynos4412";
  16 +
  17 + aliases {
  18 + i2c0 = "/i2c@13860000";
  19 + serial0 = "/serial@13800000";
  20 + console = "/serial@13810000";
  21 + mmc2 = "sdhci@12530000";
  22 + mmc4 = "dwmmc@12550000";
  23 + };
  24 +
  25 + i2c@13860000 {
  26 + samsung,i2c-sda-delay = <100>;
  27 + samsung,i2c-slave-addr = <0x10>;
  28 + samsung,i2c-max-bus-freq = <100000>;
  29 + status = "okay";
  30 +
  31 + max77686_pmic@09 {
  32 + compatible = "maxim,max77686_pmic";
  33 + interrupts = <7 0>;
  34 + reg = <0x09 0 0>;
  35 + #clock-cells = <1>;
  36 + };
  37 + };
  38 +
  39 + serial@13810000 {
  40 + status = "okay";
  41 + };
  42 +
  43 + sdhci@12510000 {
  44 + status = "disabled";
  45 + };
  46 +
  47 + sdhci@12520000 {
  48 + status = "disabled";
  49 + };
  50 +
  51 + sdhci@12530000 {
  52 + samsung,bus-width = <4>;
  53 + samsung,timing = <1 2 3>;
  54 + cd-gpios = <&gpio 0xC2 0>;
  55 + };
  56 +
  57 + sdhci@12540000 {
  58 + status = "disabled";
  59 + };
  60 +
  61 + dwmmc@12550000 {
  62 + samsung,bus-width = <8>;
  63 + samsung,timing = <2 1 0>;
  64 + samsung,removable = <0>;
  65 + fifoth_val = <0x203f0040>;
  66 + bus_hz = <400000000>;
  67 + div = <0x3>;
  68 + index = <4>;
  69 + };
  70 +};
arch/arm/dts/exynos5420-peach-pit.dts
Diff comments   View file @ b653516
... ... @@ -63,6 +63,11 @@
63 63 reg = <0x20>;
64 64 compatible = "maxim,max98090-codec";
65 65 };
  66 +
  67 + edp-lvds-bridge@48 {
  68 + compatible = "parade,ps8625";
  69 + reg = <0x48>;
  70 + };
66 71 };
67 72  
68 73 sound@3830000 {
... ... @@ -123,6 +128,31 @@
123 128  
124 129 xhci@12400000 {
125 130 samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
  131 + };
  132 +
  133 + fimd@14400000 {
  134 + samsung,vl-freq = <60>;
  135 + samsung,vl-col = <1366>;
  136 + samsung,vl-row = <768>;
  137 + samsung,vl-width = <1366>;
  138 + samsung,vl-height = <768>;
  139 +
  140 + samsung,vl-clkp;
  141 + samsung,vl-dp;
  142 + samsung,vl-bpix = <4>;
  143 +
  144 + samsung,vl-hspw = <32>;
  145 + samsung,vl-hbpd = <40>;
  146 + samsung,vl-hfpd = <40>;
  147 + samsung,vl-vspw = <6>;
  148 + samsung,vl-vbpd = <10>;
  149 + samsung,vl-vfpd = <12>;
  150 + samsung,vl-cmd-allow-len = <0xf>;
  151 +
  152 + samsung,winid = <3>;
  153 + samsung,interface-mode = <1>;
  154 + samsung,dp-enabled = <1>;
  155 + samsung,dual-lcd-enabled = <0>;
126 156 };
127 157 };
arch/arm/dts/exynos54xx.dtsi
Diff comments   View file @ b653516
... ... @@ -113,6 +113,16 @@
113 113 status = "disabled";
114 114 };
115 115  
  116 + fimdm0_sysmmu@0x14640000 {
  117 + compatible = "samsung,sysmmu-v3.3";
  118 + reg = <0x14640000 0x100>;
  119 + };
  120 +
  121 + fimdm1_sysmmu@0x14680000 {
  122 + compatible = "samsung,sysmmu-v3.3";
  123 + reg = <0x14680000 0x100>;
  124 + };
  125 +
116 126 fimd@14400000 {
117 127 /* sysmmu is not used in U-Boot */
118 128 samsung,disable-sysmmu;
arch/arm/include/asm/arch-exynos/clk.h
Diff comments   View file @ b653516
... ... @@ -15,6 +15,7 @@
15 15 #define VPLL 4
16 16 #define BPLL 5
17 17 #define RPLL 6
  18 +#define SPLL 7
18 19  
19 20 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
20 21 #define MASK_RATIO(x) (0xf << (x << 4))
arch/arm/include/asm/arch-exynos/gpio.h
Diff comments   View file @ b653516
... ... @@ -1504,6 +1504,7 @@
1504 1504 void gpio_cfg_pin(int gpio, int cfg);
1505 1505 void gpio_set_pull(int gpio, int mode);
1506 1506 void gpio_set_drv(int gpio, int mode);
  1507 +int gpio_direction_input(unsigned gpio);
1507 1508 int gpio_direction_output(unsigned gpio, int value);
1508 1509 int gpio_set_value(unsigned gpio, int value);
1509 1510 int gpio_get_value(unsigned gpio);
arch/arm/include/asm/arch-exynos/power.h
Diff comments   View file @ b653516
... ... @@ -1670,6 +1670,27 @@
1670 1670 };
1671 1671 #endif /* __ASSEMBLY__ */
1672 1672  
  1673 +#define OM_PIN_BITS 0x1f
  1674 +#define OM_PIN_SHIFT 0x1
  1675 +#define OM_PIN_MASK (OM_PIN_BITS << OM_PIN_SHIFT)
  1676 +
  1677 +enum {
  1678 + /*
  1679 + * Assign the OM pin values for respective boot modes.
  1680 + * Exynos4 does not support spi boot and the mmc boot OM
  1681 + * pin values are the same across Exynos4 and Exynos5.
  1682 + */
  1683 + BOOT_MODE_SD = 4, /* SD_CH2 | USB */
  1684 + BOOT_MODE_EMMC = 8, /* EMMC4.4 | USB */
  1685 + BOOT_MODE_EMMC_SD = 40, /* EMMC4.4 | SD_CH2 */
  1686 + BOOT_MODE_SERIAL = 20,
  1687 + /* Boot based on Operating Mode pin settings */
  1688 + BOOT_MODE_OM = 32,
  1689 + BOOT_MODE_USB, /* Boot using USB download */
  1690 +};
  1691 +
  1692 +unsigned int get_boot_mode(void);
  1693 +
1673 1694 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
1674 1695  
1675 1696 #define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
arch/arm/include/asm/arch-exynos/spl.h
Diff comments   View file @ b653516
... ... @@ -8,21 +8,8 @@
8 8 #define __ASM_ARCH_EXYNOS_SPL_H__
9 9  
10 10 #include <asm/arch-exynos/dmc.h>
  11 +#include <asm/arch/power.h>
11 12  
12   -enum boot_mode {
13   - /*
14   - * Assign the OM pin values for respective boot modes.
15   - * Exynos4 does not support spi boot and the mmc boot OM
16   - * pin values are the same across Exynos4 and Exynos5.
17   - */
18   - BOOT_MODE_MMC = 4,
19   - BOOT_MODE_EMMC = 8, /* EMMC4.4 */
20   - BOOT_MODE_SERIAL = 20,
21   - /* Boot based on Operating Mode pin settings */
22   - BOOT_MODE_OM = 32,
23   - BOOT_MODE_USB, /* Boot using USB download */
24   -};
25   -
26 13 #ifndef __ASSEMBLY__
27 14 /* Parameters of early board initialization in SPL */
28 15 struct spl_machine_param {
... ... @@ -62,7 +49,7 @@
62 49 * table only for mmc boot.
63 50 */
64 51 u32 uboot_size;
65   - enum boot_mode boot_source; /* Boot device */
  52 + unsigned boot_source; /* Boot device */
66 53 unsigned frequency_mhz; /* Frequency of memory in MHz */
67 54 unsigned arm_freq_mhz; /* ARM Frequency in MHz */
68 55 u32 serial_base; /* Serial base address */
arch/arm/include/asm/arch-exynos/system.h
Diff comments   View file @ b653516
... ... @@ -39,6 +39,10 @@
39 39  
40 40 void set_usbhost_mode(unsigned int mode);
41 41 void set_system_display_ctrl(void);
  42 +int exynos_lcd_early_init(const void *blob);
  43 +
  44 +/* Initialize the Parade dP<->LVDS bridge if present */
  45 +int parade_init(const void *blob);
42 46  
43 47 #endif /* _EXYNOS4_SYSTEM_H */
arch/arm/lib/reset.c
Diff comments   View file @ b653516
... ... @@ -23,6 +23,10 @@
23 23  
24 24 #include <common.h>
25 25  
  26 +__weak void reset_misc(void)
  27 +{
  28 +}
  29 +
26 30 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
27 31 {
28 32 puts ("resetting ...\n");
... ... @@ -30,6 +34,8 @@
30 34 udelay (50000); /* wait 50 ms */
31 35  
32 36 disable_interrupts();
  37 +
  38 + reset_misc();
33 39 reset_cpu(0);
34 40  
35 41 /*NOTREACHED*/
board/samsung/arndale/MAINTAINERS
Diff comments   View file @ b653516
1 1 ARNDALE BOARD
2   -M: Inderpal Singh <inderpal.singh@linaro.org>
  2 +M: Chander Kashyap <k.chander@samsung.com>
3 3 S: Maintained
4 4 F: board/samsung/arndale/
5 5 F: include/configs/arndale.h
board/samsung/common/board.c
Diff comments   View file @ b653516
... ... @@ -20,6 +20,7 @@
20 20 #include <asm/arch/mmc.h>
21 21 #include <asm/arch/pinmux.h>
22 22 #include <asm/arch/power.h>
  23 +#include <asm/arch/system.h>
23 24 #include <power/pmic.h>
24 25 #include <asm/arch/sromc.h>
25 26 #include <lcd.h>
... ... @@ -137,7 +138,9 @@
137 138 int board_early_init_f(void)
138 139 {
139 140 int err;
140   -
  141 +#ifdef CONFIG_BOARD_TYPES
  142 + set_board_type();
  143 +#endif
141 144 err = board_uart_init();
142 145 if (err) {
143 146 debug("UART init failed\n");
... ... @@ -148,6 +151,20 @@
148 151 board_i2c_init(gd->fdt_blob);
149 152 #endif
150 153  
  154 +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
  155 +/*
  156 + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
  157 + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
  158 + * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
  159 + * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
  160 + */
  161 + err = exynos_lcd_early_init(gd->fdt_blob);
  162 + if (err) {
  163 + debug("LCD early init failed\n");
  164 + return err;
  165 + }
  166 +#endif
  167 +
151 168 return exynos_early_init_f();
152 169 }
153 170 #endif
154 171  
155 172  
156 173  
157 174  
158 175  
... ... @@ -240,22 +257,39 @@
240 257 }
241 258  
242 259 #ifdef CONFIG_GENERIC_MMC
243   -int board_mmc_init(bd_t *bis)
  260 +static int init_mmc(void)
244 261 {
245   - int ret;
  262 +#ifdef CONFIG_SDHCI
  263 + return exynos_mmc_init(gd->fdt_blob);
  264 +#else
  265 + return 0;
  266 +#endif
  267 +}
  268 +
  269 +static int init_dwmmc(void)
  270 +{
246 271 #ifdef CONFIG_DWMMC
247   - /* dwmmc initializattion for available channels */
248   - ret = exynos_dwmmc_init(gd->fdt_blob);
249   - if (ret)
250   - debug("dwmmc init failed\n");
  272 + return exynos_dwmmc_init(gd->fdt_blob);
  273 +#else
  274 + return 0;
251 275 #endif
  276 +}
252 277  
253   -#ifdef CONFIG_SDHCI
254   - /* mmc initializattion for available channels */
255   - ret = exynos_mmc_init(gd->fdt_blob);
  278 +int board_mmc_init(bd_t *bis)
  279 +{
  280 + int ret;
  281 +
  282 + if (get_boot_mode() == BOOT_MODE_SD) {
  283 + ret = init_mmc();
  284 + ret |= init_dwmmc();
  285 + } else {
  286 + ret = init_dwmmc();
  287 + ret |= init_mmc();
  288 + }
  289 +
256 290 if (ret)
257 291 debug("mmc init failed\n");
258   -#endif
  292 +
259 293 return ret;
260 294 }
261 295 #endif
262 296  
263 297  
... ... @@ -263,11 +297,15 @@
263 297 #ifdef CONFIG_DISPLAY_BOARDINFO
264 298 int checkboard(void)
265 299 {
266   - const char *board_name;
  300 + const char *board_info;
267 301  
268   - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
269   - printf("Board: %s\n", board_name ? board_name : "unknown");
  302 + board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
  303 + printf("Board: %s\n", board_info ? board_info : "unknown");
  304 +#ifdef CONFIG_BOARD_TYPES
  305 + board_info = get_board_type();
270 306  
  307 + printf("Model: %s\n", board_info ? board_info : "unknown");
  308 +#endif
271 309 return 0;
272 310 }
273 311 #endif
... ... @@ -307,6 +345,9 @@
307 345 #ifdef CONFIG_MISC_INIT_R
308 346 int misc_init_r(void)
309 347 {
  348 +#ifdef CONFIG_SET_DFU_ALT_INFO
  349 + set_dfu_alt_info();
  350 +#endif
310 351 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
311 352 set_board_info();
312 353 #endif
board/samsung/common/misc.c
Diff comments   View file @ b653516
... ... @@ -11,6 +11,7 @@
11 11 #include <samsung/misc.h>
12 12 #include <errno.h>
13 13 #include <version.h>
  14 +#include <malloc.h>
14 15 #include <linux/sizes.h>
15 16 #include <asm/arch/cpu.h>
16 17 #include <asm/arch/gpio.h>
17 18  
... ... @@ -21,13 +22,53 @@
21 22  
22 23 DECLARE_GLOBAL_DATA_PTR;
23 24  
  25 +#ifdef CONFIG_SET_DFU_ALT_INFO
  26 +void set_dfu_alt_info(void)
  27 +{
  28 + size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
  29 + ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
  30 + char *alt_info = "Settings not found!";
  31 + char *status = "error!\n";
  32 + char *alt_setting;
  33 + char *alt_sep;
  34 + int offset = 0;
  35 +
  36 + puts("DFU alt info setting: ");
  37 +
  38 + alt_setting = get_dfu_alt_boot();
  39 + if (alt_setting) {
  40 + setenv("dfu_alt_boot", alt_setting);
  41 + offset = snprintf(buf, buf_size, "%s", alt_setting);
  42 + }
  43 +
  44 + alt_setting = get_dfu_alt_system();
  45 + if (alt_setting) {
  46 + if (offset)
  47 + alt_sep = ";";
  48 + else
  49 + alt_sep = "";
  50 +
  51 + offset += snprintf(buf + offset, buf_size - offset,
  52 + "%s%s", alt_sep, alt_setting);
  53 + }
  54 +
  55 + if (offset) {
  56 + alt_info = buf;
  57 + status = "done\n";
  58 + }
  59 +
  60 + setenv("dfu_alt_info", alt_info);
  61 + puts(status);
  62 +}
  63 +#endif
  64 +
24 65 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
25 66 void set_board_info(void)
26 67 {
27 68 char info[64];
28 69  
29   - snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f,
30   - (s5p_cpu_rev & 0xf0) >> 0x04);
  70 + snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4,
  71 + s5p_cpu_rev & 0xf);
31 72 setenv("soc_rev", info);
32 73  
33 74 snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
... ... @@ -38,8 +79,16 @@
38 79 setenv("board_rev", info);
39 80 #endif
40 81 #ifdef CONFIG_OF_LIBFDT
41   - snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb",
42   - CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
  82 + const char *bdtype = "";
  83 + const char *bdname = CONFIG_SYS_BOARD;
  84 +
  85 +#ifdef CONFIG_BOARD_TYPES
  86 + bdtype = get_board_type();
  87 + sprintf(info, "%s%s", bdname, bdtype);
  88 + setenv("boardname", info);
  89 +#endif
  90 + snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb",
  91 + CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
43 92 setenv("fdtfile", info);
44 93 #endif
45 94 }
board/samsung/odroid/Kconfig
Diff comments   View file @ b653516
  1 +if TARGET_ODROID
  2 +
  3 +config SYS_BOARD
  4 + string
  5 + default "odroid"
  6 +
  7 +config SYS_VENDOR
  8 + string
  9 + default "samsung"
  10 +
  11 +config SYS_CONFIG_NAME
  12 + string
  13 + default "odroid"
  14 +
  15 +endif
board/samsung/odroid/MAINTAINERS
Diff comments   View file @ b653516
  1 +ODROID BOARD
  2 +M: Przemyslaw Marczak <p.marczak@samsung.com>
  3 +S: Maintained
  4 +F: board/samsung/odroid/
  5 +F: include/configs/odroid.h
  6 +F: configs/odroid_defconfig
board/samsung/odroid/Makefile
Diff comments   View file @ b653516
  1 +#
  2 +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
  3 +# Przemyslaw Marczak <p.marczak@samsung.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := odroid.o
board/samsung/odroid/odroid.c
Diff comments   View file @ b653516
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + * Przemyslaw Marczak <p.marczak@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/arch/pinmux.h>
  10 +#include <asm/arch/power.h>
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/gpio.h>
  13 +#include <asm/gpio.h>
  14 +#include <asm/arch/cpu.h>
  15 +#include <power/pmic.h>
  16 +#include <power/max77686_pmic.h>
  17 +#include <errno.h>
  18 +#include <usb.h>
  19 +#include <usb/s3c_udc.h>
  20 +#include <samsung/misc.h>
  21 +#include "setup.h"
  22 +
  23 +DECLARE_GLOBAL_DATA_PTR;
  24 +
  25 +#ifdef CONFIG_BOARD_TYPES
  26 +/* Odroid board types */
  27 +enum {
  28 + ODROID_TYPE_U3,
  29 + ODROID_TYPE_X2,
  30 + ODROID_TYPES,
  31 +};
  32 +
  33 +void set_board_type(void)
  34 +{
  35 + /* Set GPA1 pin 1 to HI - enable XCL205 output */
  36 + writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
  37 + writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
  38 + writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
  39 + writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
  40 +
  41 + /* Set GPC1 pin 2 to IN - check XCL205 output state */
  42 + writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
  43 + writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
  44 +
  45 + /* XCL205 - needs some latch time */
  46 + sdelay(200000);
  47 +
  48 + /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
  49 + if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
  50 + gd->board_type = ODROID_TYPE_X2;
  51 + else
  52 + gd->board_type = ODROID_TYPE_U3;
  53 +}
  54 +
  55 +const char *get_board_type(void)
  56 +{
  57 + const char *board_type[] = {"u3", "x2"};
  58 +
  59 + return board_type[gd->board_type];
  60 +}
  61 +#endif
  62 +
  63 +#ifdef CONFIG_SET_DFU_ALT_INFO
  64 +char *get_dfu_alt_system(void)
  65 +{
  66 + return getenv("dfu_alt_system");
  67 +}
  68 +
  69 +char *get_dfu_alt_boot(void)
  70 +{
  71 + char *alt_boot;
  72 +
  73 + switch (get_boot_mode()) {
  74 + case BOOT_MODE_SD:
  75 + alt_boot = CONFIG_DFU_ALT_BOOT_SD;
  76 + break;
  77 + case BOOT_MODE_EMMC:
  78 + case BOOT_MODE_EMMC_SD:
  79 + alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
  80 + break;
  81 + default:
  82 + alt_boot = NULL;
  83 + break;
  84 + }
  85 + return alt_boot;
  86 +}
  87 +#endif
  88 +
  89 +static void board_clock_init(void)
  90 +{
  91 + unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
  92 + struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
  93 + samsung_get_base_clock();
  94 +
  95 + /*
  96 + * CMU_CPU clocks src to MPLL
  97 + * Bit values: 0 ; 1
  98 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
  99 + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
  100 + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
  101 + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
  102 + */
  103 + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
  104 + MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
  105 + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
  106 + MUX_MPLL_USER_SEL_C(1);
  107 +
  108 + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  109 +
  110 + /* Wait for mux change */
  111 + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  112 + continue;
  113 +
  114 + /* Set APLL to 1000MHz */
  115 + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
  116 + set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
  117 +
  118 + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
  119 +
  120 + /* Wait for PLL to be locked */
  121 + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
  122 + continue;
  123 +
  124 + /* Set CMU_CPU clocks src to APLL */
  125 + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
  126 + MUX_MPLL_USER_SEL_C(1);
  127 + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  128 +
  129 + /* Wait for mux change */
  130 + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  131 + continue;
  132 +
  133 + set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
  134 + PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  135 + APLL_RATIO(0) | CORE2_RATIO(0);
  136 + /*
  137 + * Set dividers for MOUTcore = 1000 MHz
  138 + * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
  139 + * corem0 = armclk / (ratio + 1) = 333 MHz (2)
  140 + * corem1 = armclk / (ratio + 1) = 166 MHz (5)
  141 + * periph = armclk / (ratio + 1) = 1000 MHz (0)
  142 + * atbout = MOUT / (ratio + 1) = 200 MHz (4)
  143 + * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  144 + * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  145 + * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  146 + */
  147 + clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
  148 + PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
  149 + APLL_RATIO(7) | CORE2_RATIO(7);
  150 +
  151 + clrsetbits_le32(&clk->div_cpu0, clr, set);
  152 +
  153 + /* Wait for divider ready status */
  154 + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
  155 + continue;
  156 +
  157 + /*
  158 + * For MOUThpm = 1000 MHz (MOUTapll)
  159 + * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  160 + * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  161 + * cores_out = armclk / (ratio + 1) = 1000 (0)
  162 + */
  163 + clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
  164 + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
  165 +
  166 + clrsetbits_le32(&clk->div_cpu1, clr, set);
  167 +
  168 + /* Wait for divider ready status */
  169 + while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
  170 + continue;
  171 +
  172 + /*
  173 + * Set CMU_DMC clocks src to APLL
  174 + * Bit values: 0 ; 1
  175 + * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
  176 + * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
  177 + * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
  178 + * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
  179 + * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  180 + * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  181 + * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  182 + * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
  183 + */
  184 + clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
  185 + MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
  186 + MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
  187 + MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  188 + set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
  189 + MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  190 + MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  191 +
  192 + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  193 +
  194 + /* Wait for mux change */
  195 + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  196 + continue;
  197 +
  198 + /* Set MPLL to 880MHz */
  199 + set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1);
  200 +
  201 + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
  202 +
  203 + /* Wait for PLL to be locked */
  204 + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
  205 + continue;
  206 +
  207 + /* Switch back CMU_DMC mux */
  208 + set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
  209 + MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  210 + MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  211 +
  212 + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  213 +
  214 + /* Wait for mux change */
  215 + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  216 + continue;
  217 +
  218 + /* CLK_DIV_DMC0 */
  219 + clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
  220 + DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
  221 + /*
  222 + * For:
  223 + * MOUTdmc = 880 MHz
  224 + * MOUTdphy = 880 MHz
  225 + *
  226 + * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3)
  227 + * pclk_acp = aclk_acp / (ratio + 1) = 110 (1)
  228 + * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1)
  229 + * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1)
  230 + * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1)
  231 + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1)
  232 + */
  233 + set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
  234 + DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  235 +
  236 + clrsetbits_le32(&clk->div_dmc0, clr, set);
  237 +
  238 + /* Wait for divider ready status */
  239 + while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
  240 + continue;
  241 +
  242 + /* CLK_DIV_DMC1 */
  243 + clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
  244 + C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
  245 + /*
  246 + * For:
  247 + * MOUTg2d = 880 MHz
  248 + * MOUTc2c = 880 Mhz
  249 + * MOUTpwi = 108 MHz
  250 + *
  251 + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1)
  252 + * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1)
  253 + * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1)
  254 + * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  255 + */
  256 + set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
  257 + C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  258 +
  259 + clrsetbits_le32(&clk->div_dmc1, clr, set);
  260 +
  261 + /* Wait for divider ready status */
  262 + while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
  263 + continue;
  264 +
  265 + /* CLK_SRC_PERIL0 */
  266 + clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
  267 + UART3_SEL(15) | UART4_SEL(15);
  268 + /*
  269 + * Set CLK_SRC_PERIL0 clocks src to MPLL
  270 + * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  271 + * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  272 + * 8(SCLK_VPLL)
  273 + *
  274 + * Set all to SCLK_MPLL_USER_T
  275 + */
  276 + set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
  277 + UART4_SEL(6);
  278 +
  279 + clrsetbits_le32(&clk->src_peril0, clr, set);
  280 +
  281 + /* CLK_DIV_PERIL0 */
  282 + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
  283 + UART3_RATIO(15) | UART4_RATIO(15);
  284 + /*
  285 + * For MOUTuart0-4: 880MHz
  286 + *
  287 + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7)
  288 + */
  289 + set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
  290 + UART3_RATIO(7) | UART4_RATIO(7);
  291 +
  292 + clrsetbits_le32(&clk->div_peril0, clr, set);
  293 +
  294 + while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
  295 + continue;
  296 +
  297 + /* CLK_DIV_FSYS1 */
  298 + clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
  299 + MMC1_PRE_RATIO(255);
  300 + /*
  301 + * For MOUTmmc0-3 = 880 MHz (MPLL)
  302 + *
  303 + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7)
  304 + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1)
  305 + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7)
  306 + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1)
  307 + */
  308 + set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
  309 + MMC1_PRE_RATIO(1);
  310 +
  311 + clrsetbits_le32(&clk->div_fsys1, clr, set);
  312 +
  313 + /* Wait for divider ready status */
  314 + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
  315 + continue;
  316 +
  317 + /* CLK_DIV_FSYS2 */
  318 + clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
  319 + MMC3_PRE_RATIO(255);
  320 + /*
  321 + * For MOUTmmc0-3 = 880 MHz (MPLL)
  322 + *
  323 + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7)
  324 + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1)
  325 + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7)
  326 + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1)
  327 + */
  328 + set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
  329 + MMC3_PRE_RATIO(1);
  330 +
  331 + clrsetbits_le32(&clk->div_fsys2, clr, set);
  332 +
  333 + /* Wait for divider ready status */
  334 + while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
  335 + continue;
  336 +
  337 + /* CLK_DIV_FSYS3 */
  338 + clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
  339 + /*
  340 + * For MOUTmmc4 = 880 MHz (MPLL)
  341 + *
  342 + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7)
  343 + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0)
  344 + */
  345 + set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
  346 +
  347 + clrsetbits_le32(&clk->div_fsys3, clr, set);
  348 +
  349 + /* Wait for divider ready status */
  350 + while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
  351 + continue;
  352 +
  353 + return;
  354 +}
  355 +
  356 +static void board_gpio_init(void)
  357 +{
  358 + /* eMMC Reset Pin */
  359 + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
  360 + gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
  361 + gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
  362 +
  363 + /* Enable FAN (Odroid U3) */
  364 + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
  365 + gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
  366 + gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
  367 +
  368 + /* OTG Vbus output (Odroid U3+) */
  369 + gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
  370 + gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
  371 + gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
  372 +
  373 + /* OTG INT (Odroid U3+) */
  374 + gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
  375 + gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
  376 + gpio_direction_input(EXYNOS4X12_GPIO_X31);
  377 +}
  378 +
  379 +static int pmic_init_max77686(void)
  380 +{
  381 + struct pmic *p = pmic_get("MAX77686_PMIC");
  382 +
  383 + if (pmic_probe(p))
  384 + return -ENODEV;
  385 +
  386 + /* Set LDO Voltage */
  387 + max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
  388 + max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
  389 + max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */
  390 +
  391 + return 0;
  392 +}
  393 +
  394 +#ifdef CONFIG_SYS_I2C_INIT_BOARD
  395 +static void board_init_i2c(void)
  396 +{
  397 + /* I2C_0 */
  398 + if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))
  399 + debug("I2C%d not configured\n", (I2C_0));
  400 +}
  401 +#endif
  402 +
  403 +int exynos_early_init_f(void)
  404 +{
  405 + board_clock_init();
  406 + board_gpio_init();
  407 +
  408 + return 0;
  409 +}
  410 +
  411 +int exynos_init(void)
  412 +{
  413 + /* The last MB of memory is reserved for secure firmware */
  414 + gd->ram_size -= SZ_1M;
  415 + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
  416 +
  417 + return 0;
  418 +}
  419 +
  420 +int exynos_power_init(void)
  421 +{
  422 +#ifdef CONFIG_SYS_I2C_INIT_BOARD
  423 + board_init_i2c();
  424 +#endif
  425 + pmic_init(I2C_0);
  426 + pmic_init_max77686();
  427 +
  428 + return 0;
  429 +}
  430 +
  431 +#ifdef CONFIG_USB_GADGET
  432 +static int s5pc210_phy_control(int on)
  433 +{
  434 + struct pmic *p_pmic;
  435 +
  436 + p_pmic = pmic_get("MAX77686_PMIC");
  437 + if (!p_pmic)
  438 + return -ENODEV;
  439 +
  440 + if (pmic_probe(p_pmic))
  441 + return -1;
  442 +
  443 + if (on)
  444 + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
  445 + else
  446 + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
  447 +}
  448 +
  449 +struct s3c_plat_otg_data s5pc210_otg_data = {
  450 + .phy_control = s5pc210_phy_control,
  451 + .regs_phy = EXYNOS4X12_USBPHY_BASE,
  452 + .regs_otg = EXYNOS4X12_USBOTG_BASE,
  453 + .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
  454 + .usb_flags = PHY0_SLEEP,
  455 +};
  456 +
  457 +int board_usb_init(int index, enum usb_init_type init)
  458 +{
  459 + debug("USB_udc_probe\n");
  460 + return s3c_udc_probe(&s5pc210_otg_data);
  461 +}
  462 +#endif
  463 +
  464 +void reset_misc(void)
  465 +{
  466 + /* Reset eMMC*/
  467 + gpio_set_value(EXYNOS4X12_GPIO_K12, 0);
  468 + mdelay(10);
  469 + gpio_set_value(EXYNOS4X12_GPIO_K12, 1);
  470 +}
board/samsung/odroid/setup.h
Diff comments   View file @ b653516
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + * Przemyslaw Marczak <p.marczak@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ODROIDU3_SETUP__
  9 +#define __ODROIDU3_SETUP__
  10 +
  11 +/* A/M PLL_CON0 */
  12 +#define SDIV(x) ((x) & 0x7)
  13 +#define PDIV(x) (((x) & 0x3f) << 8)
  14 +#define MDIV(x) (((x) & 0x3ff) << 16)
  15 +#define FSEL(x) (((x) & 0x1) << 27)
  16 +#define PLL_LOCKED_BIT (0x1 << 29)
  17 +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
  18 +
  19 +/* CLK_SRC_CPU */
  20 +#define MUX_APLL_SEL(x) ((x) & 0x1)
  21 +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
  22 +#define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
  23 +#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
  24 +
  25 +#define MUX_STAT_CHANGING 0x100
  26 +
  27 +/* CLK_MUX_STAT_CPU */
  28 +#define APLL_SEL(x) ((x) & 0x7)
  29 +#define CORE_SEL(x) (((x) & 0x7) << 16)
  30 +#define HPM_SEL(x) (((x) & 0x7) << 20)
  31 +#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
  32 +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
  33 + CORE_SEL(MUX_STAT_CHANGING) | \
  34 + HPM_SEL(MUX_STAT_CHANGING) | \
  35 + MPLL_USER_SEL_C(MUX_STAT_CHANGING))
  36 +
  37 +/* CLK_DIV_CPU0 */
  38 +#define CORE_RATIO(x) ((x) & 0x7)
  39 +#define COREM0_RATIO(x) (((x) & 0x7) << 4)
  40 +#define COREM1_RATIO(x) (((x) & 0x7) << 8)
  41 +#define PERIPH_RATIO(x) (((x) & 0x7) << 12)
  42 +#define ATB_RATIO(x) (((x) & 0x7) << 16)
  43 +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
  44 +#define APLL_RATIO(x) (((x) & 0x7) << 24)
  45 +#define CORE2_RATIO(x) (((x) & 0x7) << 28)
  46 +
  47 +/* CLK_DIV_STAT_CPU0 */
  48 +#define DIV_CORE(x) ((x) & 0x1)
  49 +#define DIV_COREM0(x) (((x) & 0x1) << 4)
  50 +#define DIV_COREM1(x) (((x) & 0x1) << 8)
  51 +#define DIV_PERIPH(x) (((x) & 0x1) << 12)
  52 +#define DIV_ATB(x) (((x) & 0x1) << 16)
  53 +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
  54 +#define DIV_APLL(x) (((x) & 0x1) << 24)
  55 +#define DIV_CORE2(x) (((x) & 0x1) << 28)
  56 +
  57 +#define DIV_STAT_CHANGING 0x1
  58 +#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
  59 + DIV_COREM0(DIV_STAT_CHANGING) | \
  60 + DIV_COREM1(DIV_STAT_CHANGING) | \
  61 + DIV_PERIPH(DIV_STAT_CHANGING) | \
  62 + DIV_ATB(DIV_STAT_CHANGING) | \
  63 + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
  64 + DIV_APLL(DIV_STAT_CHANGING) | \
  65 + DIV_CORE2(DIV_STAT_CHANGING))
  66 +
  67 +/* CLK_DIV_CPU1 */
  68 +#define COPY_RATIO(x) ((x) & 0x7)
  69 +#define HPM_RATIO(x) (((x) & 0x7) << 4)
  70 +#define CORES_RATIO(x) (((x) & 0x7) << 8)
  71 +
  72 +/* CLK_DIV_STAT_CPU1 */
  73 +#define DIV_COPY(x) ((x) & 0x7)
  74 +#define DIV_HPM(x) (((x) & 0x1) << 4)
  75 +#define DIV_CORES(x) (((x) & 0x1) << 8)
  76 +
  77 +#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
  78 + DIV_HPM(DIV_STAT_CHANGING) | \
  79 + DIV_CORES(DIV_STAT_CHANGING))
  80 +
  81 +/* CLK_SRC_DMC */
  82 +#define MUX_C2C_SEL(x) ((x) & 0x1)
  83 +#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
  84 +#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
  85 +#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
  86 +#define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
  87 +#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
  88 +#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
  89 +#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
  90 +
  91 +/* CLK_MUX_STAT_DMC */
  92 +#define C2C_SEL(x) (((x)) & 0x7)
  93 +#define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
  94 +#define DPHY_SEL(x) (((x) & 0x7) << 8)
  95 +#define MPLL_SEL(x) (((x) & 0x7) << 12)
  96 +/* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
  97 +#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
  98 +#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
  99 +#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
  100 +
  101 +#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
  102 + DMC_BUS_SEL(MUX_STAT_CHANGING) | \
  103 + DPHY_SEL(MUX_STAT_CHANGING) | \
  104 + MPLL_SEL(MUX_STAT_CHANGING) |\
  105 + G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
  106 + G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
  107 + G2D_ACP_SEL(MUX_STAT_CHANGING))
  108 +
  109 +/* CLK_DIV_DMC0 */
  110 +#define ACP_RATIO(x) ((x) & 0x7)
  111 +#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
  112 +#define DPHY_RATIO(x) (((x) & 0x7) << 8)
  113 +#define DMC_RATIO(x) (((x) & 0x7) << 12)
  114 +#define DMCD_RATIO(x) (((x) & 0x7) << 16)
  115 +#define DMCP_RATIO(x) (((x) & 0x7) << 20)
  116 +
  117 +/* CLK_DIV_STAT_DMC0 */
  118 +#define DIV_ACP(x) ((x) & 0x1)
  119 +#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
  120 +#define DIV_DPHY(x) (((x) & 0x1) << 8)
  121 +#define DIV_DMC(x) (((x) & 0x1) << 12)
  122 +#define DIV_DMCD(x) (((x) & 0x1) << 16)
  123 +#define DIV_DMCP(x) (((x) & 0x1) << 20)
  124 +
  125 +#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
  126 + DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
  127 + DIV_DPHY(DIV_STAT_CHANGING) | \
  128 + DIV_DMC(DIV_STAT_CHANGING) | \
  129 + DIV_DMCD(DIV_STAT_CHANGING) | \
  130 + DIV_DMCP(DIV_STAT_CHANGING))
  131 +
  132 +/* CLK_DIV_DMC1 */
  133 +#define G2D_ACP_RATIO(x) ((x) & 0xf)
  134 +#define C2C_RATIO(x) (((x) & 0x7) << 4)
  135 +#define PWI_RATIO(x) (((x) & 0xf) << 8)
  136 +#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
  137 +#define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
  138 +#define DPM_RATIO(x) (((x) & 0x7f) << 24)
  139 +
  140 +/* CLK_DIV_STAT_DMC1 */
  141 +#define DIV_G2D_ACP(x) ((x) & 0x1)
  142 +#define DIV_C2C(x) (((x) & 0x1) << 4)
  143 +#define DIV_PWI(x) (((x) & 0x1) << 8)
  144 +#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
  145 +#define DIV_DVSEM(x) (((x) & 0x1) << 16)
  146 +#define DIV_DPM(x) (((x) & 0x1) << 24)
  147 +
  148 +#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
  149 + DIV_C2C(DIV_STAT_CHANGING) | \
  150 + DIV_PWI(DIV_STAT_CHANGING) | \
  151 + DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
  152 + DIV_DVSEM(DIV_STAT_CHANGING) | \
  153 + DIV_DPM(DIV_STAT_CHANGING))
  154 +
  155 +/* Set CLK_SRC_PERIL0 */
  156 +#define UART4_SEL(x) (((x) & 0xf) << 16)
  157 +#define UART3_SEL(x) (((x) & 0xf) << 12)
  158 +#define UART2_SEL(x) (((x) & 0xf) << 8)
  159 +#define UART1_SEL(x) (((x) & 0xf) << 4)
  160 +#define UART0_SEL(x) ((x) & 0xf)
  161 +
  162 +/* Set CLK_DIV_PERIL0 */
  163 +#define UART4_RATIO(x) (((x) & 0xf) << 16)
  164 +#define UART3_RATIO(x) (((x) & 0xf) << 12)
  165 +#define UART2_RATIO(x) (((x) & 0xf) << 8)
  166 +#define UART1_RATIO(x) (((x) & 0xf) << 4)
  167 +#define UART0_RATIO(x) ((x) & 0xf)
  168 +
  169 +/* Set CLK_DIV_STAT_PERIL0 */
  170 +#define DIV_UART4(x) (((x) & 0x1) << 16)
  171 +#define DIV_UART3(x) (((x) & 0x1) << 12)
  172 +#define DIV_UART2(x) (((x) & 0x1) << 8)
  173 +#define DIV_UART1(x) (((x) & 0x1) << 4)
  174 +#define DIV_UART0(x) ((x) & 0x1)
  175 +
  176 +#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
  177 + DIV_UART3(DIV_STAT_CHANGING) | \
  178 + DIV_UART2(DIV_STAT_CHANGING) | \
  179 + DIV_UART1(DIV_STAT_CHANGING) | \
  180 + DIV_UART0(DIV_STAT_CHANGING))
  181 +
  182 +/* CLK_DIV_FSYS1 */
  183 +#define MMC0_RATIO(x) ((x) & 0xf)
  184 +#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
  185 +#define MMC1_RATIO(x) (((x) & 0xf) << 16)
  186 +#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
  187 +
  188 +/* CLK_DIV_STAT_FSYS1 */
  189 +#define DIV_MMC0(x) ((x) & 1)
  190 +#define DIV_MMC0_PRE(x) (((x) & 1) << 8)
  191 +#define DIV_MMC1(x) (((x) & 1) << 16)
  192 +#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
  193 +
  194 +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
  195 + DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
  196 + DIV_MMC1(DIV_STAT_CHANGING) | \
  197 + DIV_MMC1_PRE(DIV_STAT_CHANGING))
  198 +
  199 +/* CLK_DIV_FSYS2 */
  200 +#define MMC2_RATIO(x) ((x) & 0xf)
  201 +#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
  202 +#define MMC3_RATIO(x) (((x) & 0xf) << 16)
  203 +#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
  204 +
  205 +/* CLK_DIV_STAT_FSYS2 */
  206 +#define DIV_MMC2(x) ((x) & 0x1)
  207 +#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
  208 +#define DIV_MMC3(x) (((x) & 0x1) << 16)
  209 +#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
  210 +
  211 +#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
  212 + DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
  213 + DIV_MMC3(DIV_STAT_CHANGING) | \
  214 + DIV_MMC3_PRE(DIV_STAT_CHANGING))
  215 +
  216 +/* CLK_DIV_FSYS3 */
  217 +#define MMC4_RATIO(x) ((x) & 0x7)
  218 +#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
  219 +
  220 +/* CLK_DIV_STAT_FSYS3 */
  221 +#define DIV_MMC4(x) ((x) & 0x1)
  222 +#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
  223 +
  224 +#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
  225 + DIV_MMC4_PRE(DIV_STAT_CHANGING))
  226 +
  227 +/* XCL205 GPIO config - Odroid U3 */
  228 +#define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE
  229 +#define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */
  230 +#define XCL205_EN_GPIO_PIN 1
  231 +#define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \
  232 + XCL205_EN_GPIO_OFFSET)
  233 +#define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \
  234 + 4 * XCL205_EN_GPIO_PIN)
  235 +#define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN)
  236 +#define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \
  237 + 2 * XCL205_EN_GPIO_PIN)
  238 +#define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \
  239 + 2 * XCL205_EN_GPIO_PIN)
  240 +
  241 +#define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */
  242 +#define XCL205_STATE_GPIO_PIN 2
  243 +#define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \
  244 + XCL205_STATE_GPIO_OFFSET)
  245 +#define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4
  246 +#define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \
  247 + 4 * XCL205_STATE_GPIO_PIN)
  248 +#define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \
  249 + 2 * XCL205_STATE_GPIO_PIN)
  250 +
  251 +#ifdef CONFIG_BOARD_TYPES
  252 +extern void sdelay(unsigned long);
  253 +#endif
  254 +
  255 +#endif /*__ODROIDU3_SETUP__ */
board/samsung/smdk5420/smdk5420.c
Diff comments   View file @ b653516
... ... @@ -10,11 +10,14 @@
10 10 #include <i2c.h>
11 11 #include <lcd.h>
12 12 #include <spi.h>
  13 +#include <errno.h>
13 14 #include <asm/arch/board.h>
14 15 #include <asm/arch/cpu.h>
15 16 #include <asm/arch/gpio.h>
16 17 #include <asm/arch/pinmux.h>
  18 +#include <asm/arch/system.h>
17 19 #include <asm/arch/dp_info.h>
  20 +#include <power/tps65090_pmic.h>
18 21  
19 22 DECLARE_GLOBAL_DATA_PTR;
20 23  
21 24  
22 25  
23 26  
24 27  
25 28  
26 29  
27 30  
28 31  
29 32  
30 33  
31 34  
32 35  
... ... @@ -40,95 +43,57 @@
40 43 }
41 44  
42 45 #ifdef CONFIG_LCD
43   -void cfg_lcd_gpio(void)
  46 +static int has_edp_bridge(void)
44 47 {
45   - /* For Backlight */
46   - gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
47   - gpio_set_value(EXYNOS5420_GPIO_B20, 1);
  48 + int node;
48 49  
49   - /* LCD power on */
50   - gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
51   - gpio_set_value(EXYNOS5420_GPIO_X15, 1);
  50 + node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
52 51  
53   - /* Set Hotplug detect for DP */
54   - gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
  52 + /* No node for bridge in device tree. */
  53 + if (node <= 0)
  54 + return 0;
  55 +
  56 + /* Default is with bridge ic */
  57 + return 1;
55 58 }
56 59  
57   -vidinfo_t panel_info = {
58   - .vl_freq = 60,
59   - .vl_col = 2560,
60   - .vl_row = 1600,
61   - .vl_width = 2560,
62   - .vl_height = 1600,
63   - .vl_clkp = CONFIG_SYS_LOW,
64   - .vl_hsp = CONFIG_SYS_LOW,
65   - .vl_vsp = CONFIG_SYS_LOW,
66   - .vl_dp = CONFIG_SYS_LOW,
67   - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
  60 +void exynos_lcd_power_on(void)
  61 +{
  62 + int ret;
68 63  
69   - /* wDP panel timing infomation */
70   - .vl_hspw = 32,
71   - .vl_hbpd = 80,
72   - .vl_hfpd = 48,
  64 +#ifdef CONFIG_POWER_TPS65090
  65 + ret = tps65090_init();
  66 + if (ret < 0) {
  67 + printf("%s: tps65090_init() failed\n", __func__);
  68 + return;
  69 + }
73 70  
74   - .vl_vspw = 6,
75   - .vl_vbpd = 37,
76   - .vl_vfpd = 3,
77   - .vl_cmd_allow_len = 0xf,
  71 + tps65090_fet_enable(6);
  72 +#endif
78 73  
79   - .win_id = 3,
80   - .cfg_gpio = cfg_lcd_gpio,
81   - .backlight_on = NULL,
82   - .lcd_power_on = NULL,
83   - .reset_lcd = NULL,
84   - .dual_lcd_enabled = 0,
  74 + mdelay(5);
85 75  
86   - .init_delay = 0,
87   - .power_on_delay = 0,
88   - .reset_delay = 0,
89   - .interface_mode = FIMD_RGB_INTERFACE,
90   - .dp_enabled = 1,
91   -};
  76 + /* TODO(ajaykumar.rs@samsung.com): Use device tree */
  77 + gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
  78 + mdelay(10);
  79 + gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
  80 + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
  81 + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
92 82  
93   -static struct edp_device_info edp_info = {
94   - .disp_info = {
95   - .h_res = 2560,
96   - .h_sync_width = 32,
97   - .h_back_porch = 80,
98   - .h_front_porch = 48,
99   - .v_res = 1600,
100   - .v_sync_width = 6,
101   - .v_back_porch = 37,
102   - .v_front_porch = 3,
103   - .v_sync_rate = 60,
104   - },
105   - .lt_info = {
106   - .lt_status = DP_LT_NONE,
107   - },
108   - .video_info = {
109   - .master_mode = 0,
110   - .bist_mode = DP_DISABLE,
111   - .bist_pattern = NO_PATTERN,
112   - .h_sync_polarity = 0,
113   - .v_sync_polarity = 0,
114   - .interlaced = 0,
115   - .color_space = COLOR_RGB,
116   - .dynamic_range = VESA,
117   - .ycbcr_coeff = COLOR_YCBCR601,
118   - .color_depth = COLOR_8,
119   - },
120   -};
  83 + if (has_edp_bridge())
  84 + if (parade_init(gd->fdt_blob))
  85 + printf("%s: ps8625_init() failed\n", __func__);
  86 +}
121 87  
122   -static struct exynos_dp_platform_data dp_platform_data = {
123   - .phy_enable = set_dp_phy_ctrl,
124   - .edp_dev_info = &edp_info,
125   -};
126   -
127   -void init_panel_info(vidinfo_t *vid)
  88 +void exynos_backlight_on(unsigned int onoff)
128 89 {
129   - vid->rgb_mode = MODE_RGB_P;
  90 + /* For PWM */
  91 + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
  92 + gpio_set_value(EXYNOS5420_GPIO_B20, 1);
130 93  
131   - exynos_set_dp_platform_data(&dp_platform_data);
  94 +#ifdef CONFIG_POWER_TPS65090
  95 + tps65090_fet_enable(1);
  96 +#endif
132 97 }
133 98 #endif
134 99  
configs/odroid_defconfig
Diff comments   View file @ b653516
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_EXYNOS=y
  3 +CONFIG_TARGET_ODROID=y
  1 + U-boot for Odroid X2/U3
  2 +========================
  3 +
  4 +1. Summary
  5 +==========
  6 +This is a quick instruction for setup Odroid boards based on Exynos4412.
  7 +Board config: odroid_config
  8 +
  9 +2. Supported devices
  10 +====================
  11 +This U-BOOT config can be used on two boards:
  12 +- Odroid U3
  13 +- Odroid X2
  14 +with CPU Exynos 4412 rev 2.0 and 2GB of RAM
  15 +
  16 +3. Boot sequence
  17 +================
  18 +iROM->BL1->(BL2 + TrustZone)->U-BOOT
  19 +
  20 +This version of U-BOOT doesn't implement SPL but it is required(BL2)
  21 +and can be found in "boot.tar.gz" from here:
  22 +http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boot.tar.gz
  23 +or here:
  24 +http://odroid.in/guides/ubuntu-lfs/boot.tar.gz
  25 +
  26 +4. Boot media layout
  27 +====================
  28 +The table below shows SD/eMMC cards layout for U-boot.
  29 +The block offset is starting from 0 and the block size is 512B.
  30 + -------------------------------------
  31 +| Binary | Block offset| part type |
  32 +| name | SD | eMMC |(eMMC only)|
  33 + -------------------------------------
  34 +| Bl1 | 1 | 0 | 1 (boot) |
  35 +| Bl2 | 31 | 30 | 1 (boot) |
  36 +| U-boot | 63 | 62 | 1 (boot) |
  37 +| Tzsw | 2111 | 2110 | 1 (boot) |
  38 +| Uboot Env | 2500 | 2500 | 0 (user) |
  39 + -------------------------------------
  40 +
  41 +5. Prepare the SD boot card - with SD card reader
  42 +=================================================
  43 +To prepare bootable media you need boot binaries provided by hardkernel.
  44 +File "boot.tar.gz" (link in point 3.) contains:
  45 +- E4412_S.bl1.HardKernel.bin
  46 +- E4412_S.tzsw.signed.bin
  47 +- bl2.signed.bin
  48 +- sd_fusing.sh
  49 +- u-boot.bin
  50 +
  51 +This is all you need to boot this board. But if you want to use your custom
  52 +u-boot then you need to change u-boot.bin with your own u-boot binary*
  53 +and run the script "sd_fusing.sh" - this script is valid only for SD card.
  54 +
  55 +*note:
  56 +The proper binary file of current U-boot is u-boot-dtb.bin.
  57 +
  58 +quick steps for Linux:
  59 +- extract boot.tar.gz
  60 +- put any SD card into the SD reader
  61 +- check the device with "dmesg"
  62 +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition)
  63 +Check if Hardkernel U-boot is booting, and next do the same with your U-boot.
  64 +
  65 +6. Prepare the eMMC boot card
  66 + with a eMMC card reader (boot from eMMC card slot)
  67 +=====================================================
  68 +To boot the device from the eMMC slot you should use a special card reader
  69 +which supports eMMC partiion switch. All of the boot binaries are stored
  70 +on the eMMC boot partition which is normally hidden.
  71 +
  72 +The "sd_fusing.sh" script can be used after updating offsets of binaries
  73 +according to the table from point 4. Be sure that you are working on the right
  74 +eMMC partition - its size is usually very small, about 1-4 MiB.
  75 +
  76 +7. Prepare the eMMC boot card
  77 + with a SD card reader (boot from SD card slot)
  78 +=================================================
  79 +If you have an eMMC->microSD adapter you can prepare the card as in point 5.
  80 +But then the device can boot only from the SD card slot.
  81 +
  82 +8. Prepare the boot media using Hardkernel U-boot
  83 +=================================================
  84 +You can update the U-boot to the custom one if you have an working bootloader
  85 +delivered with the board on a eMMC/SD card. Then follow the steps:
  86 +- install the android fastboot tool
  87 +- connect a micro usb cable to the board
  88 +- on the U-boot prompt, run command: fastboot (as a root)
  89 +- on the host, run command: "fastboot flash bootloader u-boot-dtb.bin"
  90 +- the custom U-boot should start after the board resets.
  91 +
  92 +9. Partition layout
  93 +====================
  94 +Default U-boot environment is setup for fixed partiion layout.
  95 +
  96 +Partition table: MSDOS. Disk layout and files as listed in the table below.
  97 + ----- ------ ------ ------ -------- ---------------------------------
  98 +| Num | Name | FS | Size | Offset | Reguired files |
  99 +| | | Type | MiB | MiB | |
  100 + ----- ------ ------ ------ -------- ---------------------------------
  101 +| 1 | BOOT | fat | 100 | 2 | kernel, fdt** |
  102 +| 2 | ROOT | ext4 | - | | any Linux system |
  103 + ----- ------ ------ ------ -------- ---------------------------------
  104 +
  105 +**note:
  106 +Supported fdt files are:
  107 +- exynos4412-odroidx2.dtb
  108 +- exynos4412-odroidu3.dtb
  109 +
  110 +Supported kernel files are:
  111 +- Image.itb
  112 +- zImage
  113 +- uImage
  114 +
  115 +The default environmental variable "dfu_alt_info" is set* for above layout.
  116 +Each partition size is just an example, dfu_alt_info tries init two partitions.
  117 +The size of each is not important.
  118 +
  119 +*note:
  120 +$dfu_alt_info is set on a boot time and it is concatenated using two variables:
  121 +- $dfu_alt_boot(set dynamically)
  122 +- $dfu_alt_system(from current env).
  123 +
  124 +To add any changes to dfu_alt_info - please modify $dfu_alt_system only.
  125 +Changes are visible after board reset.
  126 +
  127 +10. The environment and booting the kernel
  128 +==========================================
  129 +There are three macros defined in config for various boot options:
  130 +Two for both, kernel with device tree support and also without it:
  131 +- boot_uimg - load uImage
  132 +- boot_zimg - load zImage
  133 +If proper fdt file exists then it will be automatically loaded,
  134 +so for old kernel types, please remove fdt file from boot partition.
  135 +
  136 +The third boot option for multi image support (more info: doc/uImage.FIT/)
  137 +- boot_fit - for binary file: "Image.itb"
  138 +
  139 +Default boot command: "autoboot"
  140 +And the boot sequence is:
  141 +- boot_fit - if "Image.itb" exists
  142 +- boot_zimg - if "zImage" exists
  143 +- boot_uimg - if "uImage" exists
doc/device-tree-bindings/video/exynos-fb.txt
Diff comments   View file @ b653516
... ... @@ -55,6 +55,12 @@
55 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
56 56 samsung,sclk-div: parent_clock/source_clock ratio
57 57 samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
  58 + samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
  59 + (needed for Exynos5420 and newer versions)
  60 + Add the required FIMD sysmmu nodes to be
  61 + disabled with compatible string
  62 + "samsung,sysmmu-v3.3", with a "reg" property
  63 + holding the register address of FIMD sysmmu.
58 64  
59 65 Example:
60 66 SOC specific part:
drivers/video/Makefile
Diff comments   View file @ b653516
... ... @@ -42,4 +42,5 @@
42 42 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
43 43 obj-$(CONFIG_FORMIKE) += formike.o
44 44 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
  45 +obj-$(CONFIG_VIDEO_PARADE) += parade.o
drivers/video/exynos_fb.c
Diff comments   View file @ b653516
... ... @@ -27,17 +27,13 @@
27 27  
28 28 static unsigned int panel_width, panel_height;
29 29  
30   -/*
31   - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
32   - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
33   - * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
34   - * is called. So, we are forced to statically assign it.
35   - */
36 30 #ifdef CONFIG_OF_CONTROL
37 31 vidinfo_t panel_info = {
38   - .vl_col = LCD_XRES,
39   - .vl_row = LCD_YRES,
40   - .vl_bpix = LCD_COLOR16,
  32 + /*
  33 + * Insert a value here so that we don't end up in the BSS
  34 + * Reference: drivers/video/tegra.c
  35 + */
  36 + .vl_col = -1,
41 37 };
42 38 #endif
43 39  
... ... @@ -141,7 +137,7 @@
141 137 }
142 138  
143 139 #ifdef CONFIG_OF_CONTROL
144   -int exynos_fimd_parse_dt(const void *blob)
  140 +int exynos_lcd_early_init(const void *blob)
145 141 {
146 142 unsigned int node;
147 143 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
... ... @@ -286,8 +282,6 @@
286 282 set_lcd_clk();
287 283  
288 284 #ifdef CONFIG_OF_CONTROL
289   - if (exynos_fimd_parse_dt(gd->fdt_blob))
290   - debug("Can't get proper panel info\n");
291 285 #ifdef CONFIG_EXYNOS_MIPI_DSIM
292 286 exynos_init_dsim_platform_data(&panel_info);
293 287 #endif
drivers/video/exynos_fimd.c
Diff comments   View file @ b653516
... ... @@ -251,7 +251,46 @@
251 251 writel(cfg, &fimd_ctrl->winshmap);
252 252 }
253 253  
  254 +#ifdef CONFIG_OF_CONTROL
  255 +/*
  256 +* The reset value for FIMD SYSMMU register MMU_CTRL is 3
  257 +* on Exynos5420 and newer versions.
  258 +* This means FIMD SYSMMU is on by default on Exynos5420
  259 +* and newer versions.
  260 +* Since in u-boot we don't use SYSMMU, we should disable
  261 +* those FIMD SYSMMU.
  262 +* Note that there are 2 SYSMMU for FIMD: m0 and m1.
  263 +* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
  264 +* We disable both of them here.
  265 +*/
  266 +void exynos_fimd_disable_sysmmu(void)
  267 +{
  268 + u32 *sysmmufimd;
  269 + unsigned int node;
  270 + int node_list[2];
  271 + int count;
  272 + int i;
254 273  
  274 + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
  275 + COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
  276 + for (i = 0; i < count; i++) {
  277 + node = node_list[i];
  278 + if (node <= 0) {
  279 + debug("Can't get device node for fimd sysmmu\n");
  280 + return;
  281 + }
  282 +
  283 + sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
  284 + if (!sysmmufimd) {
  285 + debug("Can't get base address for sysmmu fimdm0");
  286 + return;
  287 + }
  288 +
  289 + writel(0x0, sysmmufimd);
  290 + }
  291 +}
  292 +#endif
  293 +
255 294 void exynos_fimd_lcd_init(vidinfo_t *vid)
256 295 {
257 296 unsigned int cfg = 0, rgb_mode;
... ... @@ -268,6 +307,10 @@
268 307 node, "reg");
269 308 if (fimd_ctrl == NULL)
270 309 debug("Can't get the FIMD base address\n");
  310 +
  311 + if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
  312 + exynos_fimd_disable_sysmmu();
  313 +
271 314 #else
272 315 fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
273 316 #endif
drivers/video/parade.c
Diff comments   View file @ b653516
  1 +/*
  2 + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * This file is a driver for Parade dP<->LVDS bridges. The original submission
  9 + * is for the ps8625 chip.
  10 + */
  11 +#include <config.h>
  12 +#include <common.h>
  13 +#include <i2c.h>
  14 +#include <fdtdec.h>
  15 +
  16 +/*
  17 + * Initialization of the chip is a process of writing certaing values into
  18 + * certain registers over i2c bus. The chip in fact responds to a range of
  19 + * addresses on the i2c bus, so for each written value three parameters are
  20 + * required: i2c address, register address and the actual value.
  21 + *
  22 + * The base address is derived from the device tree, only address offset is
  23 + * stored in the table below.
  24 + */
  25 +/**
  26 + * struct reg_data() - data for a parade register write
  27 + *
  28 + * @addr_off offset from the i2c base address for parade
  29 + * @reg_addr register address to write
  30 + * @value value to be written
  31 + */
  32 +struct reg_data {
  33 + uint8_t addr_off;
  34 + uint8_t reg;
  35 + uint8_t value;
  36 +} _packed;
  37 +
  38 +#define END_OF_TABLE 0xff /* Ficticious offset */
  39 +
  40 +static const struct reg_data parade_values[] = {
  41 + {0x02, 0xa1, 0x01}, /* HPD low */
  42 + /*
  43 + * SW setting
  44 + * [1:0] SW output 1.2V voltage is lower to 96%
  45 + */
  46 + {0x04, 0x14, 0x01},
  47 + /*
  48 + * RCO SS setting
  49 + * [5:4] = b01 0.5%, b10 1%, b11 1.5%
  50 + */
  51 + {0x04, 0xe3, 0x20},
  52 + {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
  53 + /*
  54 + * RPHY Setting
  55 + * [3:2] CDR tune wait cycle before
  56 + * measure for fine tune b00: 1us,
  57 + * 01: 0.5us, 10:2us, 11:4us.
  58 + */
  59 + {0x04, 0x8a, 0x0c},
  60 + {0x04, 0x89, 0x08}, /* [3] RFD always on */
  61 + /*
  62 + * CTN lock in/out:
  63 + * 20000ppm/80000ppm. Lock out 2
  64 + * times.
  65 + */
  66 + {0x04, 0x71, 0x2d},
  67 + /*
  68 + * 2.7G CDR settings
  69 + * NOF=40LSB for HBR CDR setting
  70 + */
  71 + {0x04, 0x7d, 0x07},
  72 + {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
  73 + {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
  74 + /*
  75 + * 1.62G CDR settings
  76 + * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
  77 + */
  78 + {0x04, 0xc0, 0x12},
  79 + {0x04, 0xc1, 0x92}, /* Gitune=-37% */
  80 + {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
  81 + {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
  82 + /*
  83 + * RPIO Setting
  84 + * [7:4] LVDS driver bias current :
  85 + * 75% (250mV swing)
  86 + */
  87 + {0x04, 0x00, 0xb0},
  88 + /*
  89 + * [7:6] Right-bar GPIO output strength is 8mA
  90 + */
  91 + {0x04, 0x15, 0x40},
  92 + /* EQ Training State Machine Setting */
  93 + {0x04, 0x54, 0x10}, /* RCO calibration start */
  94 + /* [4:0] MAX_LANE_COUNT set to one lane */
  95 + {0x01, 0x02, 0x81},
  96 + /* [4:0] LANE_COUNT_SET set to one lane */
  97 + {0x01, 0x21, 0x81},
  98 + {0x00, 0x52, 0x20},
  99 + {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
  100 + {0x00, 0x62, 0x41},
  101 + /* Counter number, add 1ms counter delay */
  102 + {0x00, 0xf6, 0x01},
  103 + /*
  104 + * [6]PWM function control by
  105 + * DPCD0040f[7], default is PWM
  106 + * block always works.
  107 + */
  108 + {0x00, 0x77, 0x06},
  109 + /*
  110 + * 04h Adjust VTotal tolerance to
  111 + * fix the 30Hz no display issue
  112 + */
  113 + {0x00, 0x4c, 0x04},
  114 + /* DPCD00400='h00, Parade OUI = 'h001cf8 */
  115 + {0x01, 0xc0, 0x00},
  116 + {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
  117 + {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
  118 + /*
  119 + * DPCD403~408 = ASCII code
  120 + * D2SLV5='h4432534c5635
  121 + */
  122 + {0x01, 0xc3, 0x44},
  123 + {0x01, 0xc4, 0x32}, /* DPCD404 */
  124 + {0x01, 0xc5, 0x53}, /* DPCD405 */
  125 + {0x01, 0xc6, 0x4c}, /* DPCD406 */
  126 + {0x01, 0xc7, 0x56}, /* DPCD407 */
  127 + {0x01, 0xc8, 0x35}, /* DPCD408 */
  128 + /*
  129 + * DPCD40A, Initial Code major revision
  130 + * '01'
  131 + */
  132 + {0x01, 0xca, 0x01},
  133 + /* DPCD40B, Initial Code minor revision '05' */
  134 + {0x01, 0xcb, 0x05},
  135 + /* DPCD720, Select internal PWM */
  136 + {0x01, 0xa5, 0xa0},
  137 + /*
  138 + * FFh for 100% PWM of brightness, 0h for 0%
  139 + * brightness
  140 + */
  141 + {0x01, 0xa7, 0xff},
  142 + /*
  143 + * Set LVDS output as 6bit-VESA mapping,
  144 + * single LVDS channel
  145 + */
  146 + {0x01, 0xcc, 0x13},
  147 + /* Enable SSC set by register */
  148 + {0x02, 0xb1, 0x20},
  149 + /*
  150 + * Set SSC enabled and +/-1% central
  151 + * spreading
  152 + */
  153 + {0x04, 0x10, 0x16},
  154 + /* MPU Clock source: LC => RCO */
  155 + {0x04, 0x59, 0x60},
  156 + {0x04, 0x54, 0x14}, /* LC -> RCO */
  157 + {0x02, 0xa1, 0x91}, /* HPD high */
  158 + {END_OF_TABLE}
  159 +};
  160 +
  161 +/**
  162 + * Write values table into the Parade eDP bridge
  163 + *
  164 + * @return 0 on success, non-0 on failure
  165 + */
  166 +
  167 +static int parade_write_regs(int base_addr, const struct reg_data *table)
  168 +{
  169 + int ret = 0;
  170 +
  171 + while (!ret && (table->addr_off != END_OF_TABLE)) {
  172 + ret = i2c_write(base_addr + table->addr_off,
  173 + table->reg, 1,
  174 + (uint8_t *)&table->value,
  175 + sizeof(table->value));
  176 + table++;
  177 + }
  178 + return ret;
  179 +}
  180 +
  181 +int parade_init(const void *blob)
  182 +{
  183 + int bus, old_bus;
  184 + int parent;
  185 + int node;
  186 + int addr;
  187 + int ret;
  188 +
  189 + node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625);
  190 + if (node < 0)
  191 + return 0;
  192 +
  193 + parent = fdt_parent_offset(blob, node);
  194 + if (parent < 0) {
  195 + debug("%s: Could not find parent i2c node\n", __func__);
  196 + return -1;
  197 + }
  198 + addr = fdtdec_get_int(blob, node, "reg", -1);
  199 + if (addr < 0) {
  200 + debug("%s: Could not find i2c address\n", __func__);
  201 + return -1;
  202 + }
  203 +
  204 + bus = i2c_get_bus_num_fdt(parent);
  205 + old_bus = i2c_get_bus_num();
  206 +
  207 + debug("%s: Using i2c bus %d\n", __func__, bus);
  208 +
  209 + /*
  210 + * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay
  211 + * here.
  212 + */
  213 + mdelay(40);
  214 + i2c_set_bus_num(bus);
  215 + ret = parade_write_regs(addr, parade_values);
  216 +
  217 + i2c_set_bus_num(old_bus);
  218 +
  219 + return ret;
  220 +}
... ... @@ -616,6 +616,7 @@
616 616 int checkdcache (void);
617 617 void upmconfig (unsigned int, unsigned int *, unsigned int);
618 618 ulong get_tbclk (void);
  619 +void reset_misc (void);
619 620 void reset_cpu (ulong addr);
620 621 #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
621 622 void ft_cpu_setup(void *blob, bd_t *bd);
include/configs/exynos5250-dt.h
Diff comments   View file @ b653516
... ... @@ -61,8 +61,6 @@
61 61 #ifdef CONFIG_LCD
62 62 #define CONFIG_EXYNOS_FB
63 63 #define CONFIG_EXYNOS_DP
64   -#define LCD_XRES 2560
65   -#define LCD_YRES 1600
66 64 #define LCD_BPP LCD_COLOR16
67 65 #endif
68 66  
include/configs/odroid.h
Diff comments   View file @ b653516
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + * Sanghee Kim <sh0130.kim@samsung.com>
  4 + * Piotr Wilczek <p.wilczek@samsung.com>
  5 + * Przemyslaw Marczak <p.marczak@samsung.com>
  6 + *
  7 + * Configuation settings for the Odroid-U3 (EXYNOS4412) board.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __CONFIG_ODROID_U3_H
  13 +#define __CONFIG_ODROID_U3_H
  14 +
  15 +#include <configs/exynos4-dt.h>
  16 +
  17 +#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */
  18 +
  19 +#undef CONFIG_DEFAULT_DEVICE_TREE
  20 +#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-odroid
  21 +
  22 +#define CONFIG_SYS_L2CACHE_OFF
  23 +#ifndef CONFIG_SYS_L2CACHE_OFF
  24 +#define CONFIG_SYS_L2_PL310
  25 +#define CONFIG_SYS_PL310_BASE 0x10502000
  26 +#endif
  27 +
  28 +#define CONFIG_MACH_TYPE 4289
  29 +
  30 +#define CONFIG_NR_DRAM_BANKS 8
  31 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  32 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
  33 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  34 +
  35 +/* memtest works on */
  36 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  37 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  38 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  39 +#define CONFIG_SYS_TEXT_BASE 0x43e00000
  40 +
  41 +#include <linux/sizes.h>
  42 +/* Size of malloc() pool */
  43 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
  44 +
  45 +/* select serial console configuration */
  46 +#define CONFIG_SERIAL1
  47 +#define CONFIG_BAUDRATE 115200
  48 +
  49 +/* Console configuration */
  50 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
  51 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  52 +
  53 +#define CONFIG_CMD_BOOTZ
  54 +#define CONFIG_FIT
  55 +#define CONFIG_FIT_VERBOSE
  56 +#define CONFIG_BOOTARGS "Please use defined boot"
  57 +#define CONFIG_BOOTCOMMAND "run autoboot"
  58 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
  59 +
  60 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  61 + - GENERATED_GBL_DATA_SIZE)
  62 +
  63 +#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */
  64 +
  65 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  66 +
  67 +#define CONFIG_ENV_IS_IN_MMC
  68 +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
  69 +#define CONFIG_ENV_SIZE 4096
  70 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
  71 +#define CONFIG_ENV_OVERWRITE
  72 +
  73 +/* Partitions name */
  74 +#define PARTS_BOOT "boot"
  75 +#define PARTS_ROOT "platform"
  76 +
  77 +#define CONFIG_DFU_ALT \
  78 + "uImage fat 0 1;" \
  79 + "zImage fat 0 1;" \
  80 + "Image.itb fat 0 1;" \
  81 + "uInitrd fat 0 1;" \
  82 + "exynos4412-odroidu3.dtb fat 0 1;" \
  83 + "exynos4412-odroidx2.dtb fat 0 1;" \
  84 + ""PARTS_BOOT" part 0 1;" \
  85 + ""PARTS_ROOT" part 0 2\0" \
  86 +
  87 +#define CONFIG_SET_DFU_ALT_INFO
  88 +#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
  89 +
  90 +#define CONFIG_DFU_ALT_BOOT_EMMC \
  91 + "u-boot raw 0x3e 0x800 mmcpart 1;" \
  92 + "bl1 raw 0x0 0x1e mmcpart 1;" \
  93 + "bl2 raw 0x1e 0x1d mmcpart 1;" \
  94 + "tzsw raw 0x83e 0x138 mmcpart 1\0"
  95 +
  96 +#define CONFIG_DFU_ALT_BOOT_SD \
  97 + "u-boot raw 0x3f 0x800;" \
  98 + "bl1 raw 0x1 0x1e;" \
  99 + "bl2 raw 0x1f 0x1d;" \
  100 + "tzsw raw 0x83f 0x138\0"
  101 +
  102 +/*
  103 + * Bootable media layout:
  104 + * dev: SD eMMC(part boot)
  105 + * BL1 1 0
  106 + * BL2 31 30
  107 + * UBOOT 63 62
  108 + * TZSW 2111 2110
  109 + * ENV 2560 2560(part user)
  110 + *
  111 + * MBR Primary partiions:
  112 + * Num Name Size Offset
  113 + * 1. BOOT: 100MiB 2MiB
  114 + * 2. ROOT: -
  115 +*/
  116 +#define CONFIG_EXTRA_ENV_SETTINGS \
  117 + "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
  118 + "${kernelname}\0" \
  119 + "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
  120 + "${initrdname}\0" \
  121 + "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
  122 + "${fdtfile}\0" \
  123 + "check_ramdisk=" \
  124 + "if run loadinitrd; then " \
  125 + "setenv initrd_addr ${initrdaddr};" \
  126 + "else " \
  127 + "setenv initrd_addr -;" \
  128 + "fi;\0" \
  129 + "check_dtb=" \
  130 + "if run loaddtb; then " \
  131 + "setenv fdt_addr ${fdtaddr};" \
  132 + "else " \
  133 + "setenv fdt_addr;" \
  134 + "fi;\0" \
  135 + "kernel_args=" \
  136 + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
  137 + " rootwait ${console} ${opts}\0" \
  138 + "boot_fit=" \
  139 + "setenv kerneladdr 0x42000000;" \
  140 + "setenv kernelname Image.itb;" \
  141 + "run loadkernel;" \
  142 + "run kernel_args;" \
  143 + "bootm ${kerneladdr}#${boardname}\0" \
  144 + "boot_uimg=" \
  145 + "setenv kerneladdr 0x40007FC0;" \
  146 + "setenv kernelname uImage;" \
  147 + "run check_dtb;" \
  148 + "run check_ramdisk;" \
  149 + "run loadkernel;" \
  150 + "run kernel_args;" \
  151 + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
  152 + "boot_zimg=" \
  153 + "setenv kerneladdr 0x40007FC0;" \
  154 + "setenv kernelname zImage;" \
  155 + "run check_dtb;" \
  156 + "run check_ramdisk;" \
  157 + "run loadkernel;" \
  158 + "run kernel_args;" \
  159 + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
  160 + "autoboot=" \
  161 + "if test -e mmc 0 Image.itb; then; " \
  162 + "run boot_fit;" \
  163 + "elif test -e mmc 0 zImage; then; " \
  164 + "run boot_zimg;" \
  165 + "elif test -e mmc 0 uImage; then; " \
  166 + "run boot_uimg;" \
  167 + "fi;\0" \
  168 + "console=" CONFIG_DEFAULT_CONSOLE \
  169 + "mmcbootdev=0\0" \
  170 + "mmcbootpart=1\0" \
  171 + "mmcrootdev=0\0" \
  172 + "mmcrootpart=2\0" \
  173 + "bootdelay=0\0" \
  174 + "dfu_alt_system="CONFIG_DFU_ALT \
  175 + "dfu_alt_info=Please reset the board\0" \
  176 + "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
  177 + "consoleoff=set console console=ram; save; reset\0" \
  178 + "initrdname=uInitrd\0" \
  179 + "initrdaddr=42000000\0" \
  180 + "fdtaddr=40800000\0"
  181 +
  182 +/* I2C */
  183 +#define CONFIG_CMD_I2C
  184 +#define CONFIG_SYS_I2C
  185 +#define CONFIG_SYS_I2C_S3C24X0
  186 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
  187 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
  188 +#define CONFIG_MAX_I2C_NUM 8
  189 +#define CONFIG_SYS_I2C_INIT_BOARD
  190 +
  191 +/* POWER */
  192 +#define CONFIG_POWER
  193 +#define CONFIG_POWER_I2C
  194 +#define CONFIG_POWER_MAX77686
  195 +
  196 +/* GPT */
  197 +#define CONFIG_RANDOM_UUID
  198 +
  199 +/* Security subsystem - enable hw_rand() */
  200 +#define CONFIG_EXYNOS_ACE_SHA
  201 +#define CONFIG_LIB_HW_RAND
  202 +
  203 +#define CONFIG_CMD_GPIO
  204 +
  205 +/*
  206 + * Supported Odroid boards: X3, U3
  207 + * TODO: Add Odroid X support
  208 + */
  209 +#define CONFIG_MISC_COMMON
  210 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  211 +#define CONFIG_BOARD_TYPES
  212 +#define CONFIG_MISC_INIT_R
  213 +
  214 +#undef CONFIG_REVISION_TAG
  215 +
  216 +#endif /* __CONFIG_H */
include/configs/peach-pit.h
Diff comments   View file @ b653516
... ... @@ -22,5 +22,15 @@
22 22 #define CONFIG_SYS_PROMPT "Peach # "
23 23 #define CONFIG_IDENT_STRING " for Peach"
24 24  
  25 +#define CONFIG_VIDEO_PARADE
  26 +
  27 +/* Display */
  28 +#define CONFIG_LCD
  29 +#ifdef CONFIG_LCD
  30 +#define CONFIG_EXYNOS_FB
  31 +#define CONFIG_EXYNOS_DP
  32 +#define LCD_BPP LCD_COLOR16
  33 +#endif
  34 +
25 35 #endif /* __CONFIG_PEACH_PIT_H */
include/configs/s5pc210_universal.h
Diff comments   View file @ b653516
... ... @@ -247,8 +247,5 @@
247 247 #define CONFIG_VIDEO_BMP_GZIP
248 248 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
249 249  
250   -#define LCD_XRES 480
251   -#define LCD_YRES 800
252   -
253 250 #endif /* __CONFIG_H */
include/configs/trats.h
Diff comments   View file @ b653516
... ... @@ -261,8 +261,5 @@
261 261 #define CONFIG_VIDEO_BMP_GZIP
262 262 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
263 263  
264   -#define LCD_XRES 720
265   -#define LCD_YRES 1280
266   -
267 264 #endif /* __CONFIG_H */
include/configs/trats2.h
Diff comments   View file @ b653516
... ... @@ -241,8 +241,5 @@
241 241 #define CONFIG_VIDEO_BMP_GZIP
242 242 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
243 243  
244   -#define LCD_XRES 720
245   -#define LCD_YRES 1280
246   -
247 244 #endif /* __CONFIG_H */
... ... @@ -94,6 +94,8 @@
94 94 COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
95 95 COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
96 96 COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
  97 + COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
  98 + COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
97 99  
98 100 COMPAT_COUNT,
99 101 };
include/samsung/misc.h
Diff comments   View file @ b653516
... ... @@ -28,5 +28,15 @@
28 28 void draw_logo(void);
29 29 #endif
30 30  
  31 +#ifdef CONFIG_SET_DFU_ALT_INFO
  32 +char *get_dfu_alt_system(void);
  33 +char *get_dfu_alt_boot(void);
  34 +void set_dfu_alt_info(void);
  35 +#endif
  36 +#ifdef CONFIG_BOARD_TYPES
  37 +void set_board_type(void);
  38 +const char *get_board_type(void);
  39 +#endif
  40 +
31 41 #endif /* __SAMSUNG_MISC_COMMON_H__ */
... ... @@ -70,6 +70,8 @@
70 70 COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"),
71 71 COMPAT(TI_TPS65090, "ti,tps65090"),
72 72 COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
  73 + COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
  74 + COMPAT(PARADE_PS8625, "parade,ps8625"),
73 75 };
74 76  
75 77 const char *fdtdec_get_compatible(enum fdt_compat_id id)