Set SDelay register in the DDR controller for the MPC5200B chip.

Rafal Jaworowski
1 parent 7b4fd36b03
Showing 4 changed files with 32 additions and 8 deletions Side-by-side Diff
board/icecube/icecube.c
cpu/mpc5xxx/cpu.c
include/configs/IceCube.h
include/mpc5xxx.h
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
  
 #if defined(CONFIG_LITE5200B)
 #include "mt46v32m16.h"
@@ -89,6 +90,8 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
+	uint svr, pvr;
+
 #ifndef CFG_RAMBOOT
 	ulong test1, test2;
  
@@ -182,6 +185,24 @@
 	}
  
 #endif /* CFG_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the 
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM 
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is 
+	 * required to account for changes caused by normal wafer processing 
+	 * parameters."
+	 */ 
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && 
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
  
 	return dramsize + dramsize2;
 }
@@ -38,7 +38,7 @@
 	ulong clock = gd->cpu_clk;
 	char buf[32];
 #ifndef CONFIG_MGT5100
-	uint svr;
+	uint svr, pvr;
 #endif
  
 	puts ("CPU:   ");
@@ -47,7 +47,8 @@
 	puts   (CPU_ID_STR);
 	printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
 #else
-	svr = get_svr ();
+	svr = get_svr();
+	pvr = get_pvr();
 	switch (SVR_VER (svr)) {
 	case SVR_MPC5200:
 		printf ("MPC5200");
  
  
@@ -57,11 +58,10 @@
 		break;
 	}
  
-	printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr));
+	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), 
+		PVR_MAJ(pvr), PVR_MIN(pvr));
 #endif
-
 	printf (" at %s MHz\n", strmhz (buf, clock));
-
 	return 0;
 }
  
@@ -56,7 +56,9 @@
  * 0x40000000 - 0x4fffffff - PCI Memory
  * 0x50000000 - 0x50ffffff - PCI IO Space
  */
-#define CONFIG_PCI		1
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCI_SCAN_SHOW	1
  
@@ -67,6 +69,8 @@
 #define CONFIG_PCI_IO_BUS	0x50000000
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+#endif
  
 #define CFG_XLB_PIPELINING	1
  
@@ -75,8 +79,6 @@
 #define CONFIG_EEPRO100		1
 #define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
-
-#define ADD_PCI_CMD 		CFG_CMD_PCI
  
 #else	/* MPC5100 */
  
@@ -131,6 +131,7 @@
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)
 #endif
+#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
  
 /* Clock Distribution Module */
 #define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
...	...	@@ -27,6 +27,7 @@
27	27	#include <common.h>
28	28	#include <mpc5xxx.h>
29	29	#include <pci.h>
	30	+#include <asm/processor.h>
30	31
31	32	#if defined(CONFIG_LITE5200B)
32	33	#include "mt46v32m16.h"
...	...	@@ -89,6 +90,8 @@
89	90	{
90	91	ulong dramsize = 0;
91	92	ulong dramsize2 = 0;
	93	+ uint svr, pvr;
	94	+
92	95	#ifndef CFG_RAMBOOT
93	96	ulong test1, test2;
94	97
...	...	@@ -182,6 +185,24 @@
182	185	}
183	186
184	187	#endif /* CFG_RAMBOOT */
	188	+
	189	+ /*
	190	+ * On MPC5200B we need to set the special configuration delay in the
	191	+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	192	+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	193	+ *
	194	+ * "The SDelay should be written to a value of 0x00000004. It is
	195	+ * required to account for changes caused by normal wafer processing
	196	+ * parameters."
	197	+ */
	198	+ svr = get_svr();
	199	+ pvr = get_pvr();
	200	+ if ((SVR_MJREV(svr) >= 2) &&
	201	+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	202	+
	203	+ (vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	204	+ __asm__ volatile ("sync");
	205	+ }
185	206
186	207	return dramsize + dramsize2;
187	208	}
...	...	@@ -38,7 +38,7 @@
38	38	ulong clock = gd->cpu_clk;
39	39	char buf[32];
40	40	#ifndef CONFIG_MGT5100
41		- uint svr;
	41	+ uint svr, pvr;
42	42	#endif
43	43
44	44	puts ("CPU: ");
...	...	@@ -47,7 +47,8 @@
47	47	puts (CPU_ID_STR);
48	48	printf (" (JTAG ID %08lx)", (vu_long )MPC5XXX_CDM_JTAGID);
49	49	#else
50		- svr = get_svr ();
	50	+ svr = get_svr();
	51	+ pvr = get_pvr();
51	52	switch (SVR_VER (svr)) {
52	53	case SVR_MPC5200:
53	54	printf ("MPC5200");
54	55
55	56
...	...	@@ -57,11 +58,10 @@
57	58	break;
58	59	}
59	60
60		- printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr));
	61	+ printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
	62	+ PVR_MAJ(pvr), PVR_MIN(pvr));
61	63	#endif
62		-
63	64	printf (" at %s MHz\n", strmhz (buf, clock));
64		-
65	65	return 0;
66	66	}
67	67
...	...	@@ -56,7 +56,9 @@
56	56	* 0x40000000 - 0x4fffffff - PCI Memory
57	57	* 0x50000000 - 0x50ffffff - PCI IO Space
58	58	*/
59		-#define CONFIG_PCI 1
	59	+#define CONFIG_PCI
	60	+
	61	+#if defined(CONFIG_PCI)
60	62	#define CONFIG_PCI_PNP 1
61	63	#define CONFIG_PCI_SCAN_SHOW 1
62	64
...	...	@@ -67,6 +69,8 @@
67	69	#define CONFIG_PCI_IO_BUS 0x50000000
68	70	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69	71	#define CONFIG_PCI_IO_SIZE 0x01000000
	72	+#define ADD_PCI_CMD CFG_CMD_PCI
	73	+#endif
70	74
71	75	#define CFG_XLB_PIPELINING 1
72	76
...	...	@@ -75,8 +79,6 @@
75	79	#define CONFIG_EEPRO100 1
76	80	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
77	81	#define CONFIG_NS8382X 1
78		-
79		-#define ADD_PCI_CMD CFG_CMD_PCI
80	82
81	83	#else /* MPC5100 */
82	84
...	...	@@ -131,6 +131,7 @@
131	131	#if defined(CONFIG_MGT5100)
132	132	#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
133	133	#endif
	134	+#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
134	135
135	136	/* Clock Distribution Module */
136	137	#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)