arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH

The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Heiko Schocher <hs@denx.de>

arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Heiko Schocher <hs@denx.de>
Christian Riesch · Albert ARIBAUD
1 parent da104e04ec
Showing 5 changed files with 15 additions and 1 deletions Side-by-side Diff
README
arch/arm/cpu/arm926ejs/start.S
include/configs/da850evm.h
include/configs/enbw_cmc.h
include/configs/hawkboard.h
@@ -420,6 +420,12 @@
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
  
+- ARM options:
+		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+		Select high exception vectors of the ARM core, e.g., do not
+		clear the V bit of the c1 register of CP15.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
  
@@ -372,8 +372,13 @@
 	 * disable MMU and D cache, and enable I cache
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
+#else
+	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
+#endif
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
@@ -37,6 +37,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
@@ -40,6 +40,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
@@ -35,6 +35,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
...	...	@@ -420,6 +420,12 @@
420	420	XWAY SoCs for booting from NOR flash. The U-Boot image needs to
421	421	be swapped if a flash programmer is used.
422	422
	423	+- ARM options:
	424	+ CONFIG_SYS_EXCEPTION_VECTORS_HIGH
	425	+
	426	+ Select high exception vectors of the ARM core, e.g., do not
	427	+ clear the V bit of the c1 register of CP15.
	428	+
423	429	- Linux Kernel Interface:
424	430	CONFIG_CLOCKS_IN_MHZ
425	431
...	...	@@ -372,8 +372,13 @@
372	372	* disable MMU and D cache, and enable I cache
373	373	*/
374	374	mrc p15, 0, r0, c1, c0, 0
375		- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
	375	+ bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
376	376	bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
	377	+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
	378	+ orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
	379	+#else
	380	+ bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
	381	+#endif
377	382	orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
378	383	orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
379	384	mcr p15, 0, r0, c1, c0, 0
...	...	@@ -37,6 +37,7 @@
37	37	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
38	38	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
39	39	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
	40	+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
40	41	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
41	42	#define CONFIG_SYS_OSCIN_FREQ 24000000
42	43	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
...	...	@@ -40,6 +40,7 @@
40	40	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
41	41	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
42	42	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
	43	+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
43	44	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
44	45	#define CONFIG_SYS_OSCIN_FREQ 24000000
45	46	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
...	...	@@ -35,6 +35,7 @@
35	35	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
36	36	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
37	37	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
	38	+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
38	39	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
39	40	#define CONFIG_SYS_OSCIN_FREQ 24000000
40	41	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE