Eric Lee / smarc-uboot

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Commit b71bf4add68a4a532196c0bead99ed1753014c2a

Authored by Tom Rini
2 parents 080d897585 eaf8c986d3
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

Showing 10 changed files Side-by-side Diff

arch/powerpc/cpu/mpc83xx/cpu.c
Diff comments   View file @ b71bf4a
... ... @@ -19,7 +19,7 @@
19 19 #include <tsec.h>
20 20 #include <netdev.h>
21 21 #include <fsl_esdhc.h>
22   -#ifdef CONFIG_BOOTCOUNT_LIMIT
  22 +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
23 23 #include <asm/immap_qe.h>
24 24 #include <asm/io.h>
25 25 #endif
arch/powerpc/cpu/mpc83xx/fdt.c
Diff comments   View file @ b71bf4a
... ... @@ -17,7 +17,7 @@
17 17 DECLARE_GLOBAL_DATA_PTR;
18 18  
19 19 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
20   - (defined(CONFIG_QE))
  20 + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
21 21 #include <asm/immap_qe.h>
22 22  
23 23 void fdt_fixup_muram (void *blob)
... ... @@ -124,7 +124,8 @@
124 124  
125 125 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
126 126  
127   -#if defined(CONFIG_BOOTCOUNT_LIMIT)
  127 +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
  128 + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
128 129 fdt_fixup_muram (blob);
129 130 #endif
130 131 }
board/ids/ids8247/Makefile
Diff comments   View file @ b71bf4a
  1 +#
  2 +# (C) Copyright 2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2005
  6 +# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
  7 +#
  8 +# SPDX-License-Identifier: GPL-2.0+
  9 +#
  10 +
  11 +obj-y = ids8247.o
board/ids/ids8247/ids8247.c
Diff comments   View file @ b71bf4a
  1 +/*
  2 + * (C) Copyright 2005
  3 + * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <ioports.h>
  10 +#include <mpc8260.h>
  11 +
  12 +#if defined(CONFIG_OF_LIBFDT)
  13 +#include <libfdt.h>
  14 +#include <libfdt_env.h>
  15 +#include <fdt_support.h>
  16 +#endif
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +/*
  21 + * I/O Port configuration table
  22 + *
  23 + * if conf is 1, then that port pin will be configured at boot time
  24 + * according to the five values podr/pdir/ppar/psor/pdat for that entry
  25 + */
  26 +
  27 +const iop_conf_t iop_conf_tab[4][32] = {
  28 +
  29 + /* Port A configuration */
  30 + { /* conf ppar psor pdir podr pdat */
  31 + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
  32 + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
  33 + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
  34 + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
  35 + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
  36 + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
  37 + /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
  38 +#if defined(CONFIG_SYS_I2C_SOFT)
  39 + /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
  40 + /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
  41 +#else /* normal I/O port pins */
  42 + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
  43 + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
  44 +#endif
  45 + /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
  46 + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
  47 + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
  48 + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
  49 + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
  50 + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
  51 + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
  52 + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
  53 + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
  54 + /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
  55 + /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
  56 + /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
  57 + /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
  58 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
  59 + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
  60 + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  61 + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
  62 + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  63 + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  64 + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  65 + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  66 + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
  67 + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  68 + },
  69 +
  70 + /* Port B configuration */
  71 + { /* conf ppar psor pdir podr pdat */
  72 + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  73 + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  74 + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  75 + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  76 + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  77 + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  78 + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  79 + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  80 + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  81 + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  82 + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  83 + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  84 + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  85 + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  86 + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
  87 + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
  88 + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
  89 + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
  90 + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
  91 + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
  92 + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
  93 + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
  94 + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
  95 + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
  96 + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
  97 + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
  98 + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
  99 + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
  100 + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  101 + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  102 + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  103 + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  104 + },
  105 +
  106 + /* Port C */
  107 + { /* conf ppar psor pdir podr pdat */
  108 + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  109 + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  110 + /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
  111 + /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
  112 + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
  113 + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  114 + /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
  115 + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  116 + /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
  117 + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
  118 + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  119 + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  120 + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
  121 + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
  122 + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  123 + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
  124 + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
  125 + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  126 + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  127 + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
  128 + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
  129 + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
  130 + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
  131 + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  132 + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  133 + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  134 + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  135 + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  136 + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  137 + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  138 + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  139 + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  140 + },
  141 +
  142 + /* Port D */
  143 + { /* conf ppar psor pdir podr pdat */
  144 + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  145 + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  146 + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  147 + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
  148 + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
  149 + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  150 + /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
  151 + /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
  152 + /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
  153 + /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
  154 + /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
  155 + /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
  156 + /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
  157 + /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
  158 + /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
  159 + /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
  160 +#if defined(CONFIG_HARD_I2C)
  161 + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
  162 + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
  163 +#else /* normal I/O port pins */
  164 + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
  165 + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
  166 +#endif
  167 + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  168 + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  169 + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  170 + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  171 + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
  172 + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
  173 + /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
  174 + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  175 + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  176 + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  177 + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  178 + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  179 + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  180 + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  181 + }
  182 +};
  183 +
  184 +/* ------------------------------------------------------------------------- */
  185 +
  186 +/* Check Board Identity:
  187 + */
  188 +int checkboard (void)
  189 +{
  190 + puts ("Board: IDS 8247\n");
  191 + return 0;
  192 +}
  193 +
  194 +/* ------------------------------------------------------------------------- */
  195 +
  196 +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
  197 + *
  198 + * This routine performs standard 8260 initialization sequence
  199 + * and calculates the available memory size. It may be called
  200 + * several times to try different SDRAM configurations on both
  201 + * 60x and local buses.
  202 + */
  203 +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
  204 + ulong orx, volatile uchar * base)
  205 +{
  206 + volatile uchar c = 0xff;
  207 + volatile uint *sdmr_ptr;
  208 + volatile uint *orx_ptr;
  209 + ulong maxsize, size;
  210 + int i;
  211 +
  212 + /* We must be able to test a location outsize the maximum legal size
  213 + * to find out THAT we are outside; but this address still has to be
  214 + * mapped by the controller. That means, that the initial mapping has
  215 + * to be (at least) twice as large as the maximum expected size.
  216 + */
  217 + maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
  218 +
  219 + sdmr_ptr = &memctl->memc_psdmr;
  220 + orx_ptr = &memctl->memc_or2;
  221 +
  222 + *orx_ptr = orx;
  223 +
  224 + /*
  225 + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
  226 + *
  227 + * "At system reset, initialization software must set up the
  228 + * programmable parameters in the memory controller banks registers
  229 + * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
  230 + * system software should execute the following initialization sequence
  231 + * for each SDRAM device.
  232 + *
  233 + * 1. Issue a PRECHARGE-ALL-BANKS command
  234 + * 2. Issue eight CBR REFRESH commands
  235 + * 3. Issue a MODE-SET command to initialize the mode register
  236 + *
  237 + * The initial commands are executed by setting P/LSDMR[OP] and
  238 + * accessing the SDRAM with a single-byte transaction."
  239 + *
  240 + * The appropriate BRx/ORx registers have already been set when we
  241 + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
  242 + */
  243 +
  244 + *sdmr_ptr = sdmr | PSDMR_OP_PREA;
  245 + *base = c;
  246 +
  247 + *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
  248 + for (i = 0; i < 8; i++)
  249 + *base = c;
  250 +
  251 + *sdmr_ptr = sdmr | PSDMR_OP_MRW;
  252 + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
  253 +
  254 + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
  255 + *base = c;
  256 +
  257 + size = get_ram_size((long *)base, maxsize);
  258 + *orx_ptr = orx | ~(size - 1);
  259 +
  260 + return (size);
  261 +}
  262 +
  263 +phys_size_t initdram (int board_type)
  264 +{
  265 + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  266 + volatile memctl8260_t *memctl = &immap->im_memctl;
  267 +
  268 + long psize;
  269 +
  270 + psize = 16 * 1024 * 1024;
  271 +
  272 + memctl->memc_psrt = CONFIG_SYS_PSRT;
  273 + memctl->memc_mptpr = CONFIG_SYS_MPTPR;
  274 +
  275 +#ifndef CONFIG_SYS_RAMBOOT
  276 + /* 60x SDRAM setup:
  277 + */
  278 + psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
  279 + (uchar *) CONFIG_SYS_SDRAM_BASE);
  280 +#endif /* CONFIG_SYS_RAMBOOT */
  281 +
  282 + icache_enable ();
  283 +
  284 + return (psize);
  285 +}
  286 +
  287 +int misc_init_r (void)
  288 +{
  289 + gd->bd->bi_flashstart = 0xff800000;
  290 + return 0;
  291 +}
  292 +
  293 +#if defined(CONFIG_CMD_NAND)
  294 +#include <nand.h>
  295 +#include <linux/mtd/mtd.h>
  296 +#include <asm/io.h>
  297 +
  298 +static u8 hwctl;
  299 +
  300 +static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  301 +{
  302 + struct nand_chip *this = mtd->priv;
  303 +
  304 + if (ctrl & NAND_CTRL_CHANGE) {
  305 + if ( ctrl & NAND_CLE ) {
  306 + hwctl |= 0x1;
  307 + writeb(0x00, (this->IO_ADDR_W + 0x0a));
  308 + } else {
  309 + hwctl &= ~0x1;
  310 + writeb(0x00, (this->IO_ADDR_W + 0x08));
  311 + }
  312 + if ( ctrl & NAND_ALE ) {
  313 + hwctl |= 0x2;
  314 + writeb(0x00, (this->IO_ADDR_W + 0x09));
  315 + } else {
  316 + hwctl &= ~0x2;
  317 + writeb(0x00, (this->IO_ADDR_W + 0x08));
  318 + }
  319 + if ( (ctrl & NAND_NCE) != NAND_NCE)
  320 + writeb(0x00, (this->IO_ADDR_W + 0x0c));
  321 + else
  322 + writeb(0x00, (this->IO_ADDR_W + 0x08));
  323 + }
  324 + if (cmd != NAND_CMD_NONE)
  325 + writeb(cmd, this->IO_ADDR_W);
  326 +
  327 +}
  328 +
  329 +static u_char ids_nand_read_byte(struct mtd_info *mtd)
  330 +{
  331 + struct nand_chip *this = mtd->priv;
  332 +
  333 + return readb(this->IO_ADDR_R);
  334 +}
  335 +
  336 +static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  337 +{
  338 + struct nand_chip *nand = mtd->priv;
  339 + int i;
  340 +
  341 + for (i = 0; i < len; i++) {
  342 + if (hwctl & 0x1)
  343 + writeb(buf[i], (nand->IO_ADDR_W + 0x02));
  344 + else if (hwctl & 0x2)
  345 + writeb(buf[i], (nand->IO_ADDR_W + 0x01));
  346 + else
  347 + writeb(buf[i], nand->IO_ADDR_W);
  348 + }
  349 +}
  350 +
  351 +static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  352 +{
  353 + struct nand_chip *this = mtd->priv;
  354 + int i;
  355 +
  356 + for (i = 0; i < len; i++) {
  357 + buf[i] = readb(this->IO_ADDR_R);
  358 + }
  359 +}
  360 +
  361 +static int ids_nand_dev_ready(struct mtd_info *mtd)
  362 +{
  363 + /* constant delay (see also tR in the datasheet) */
  364 + udelay(12);
  365 + return 1;
  366 +}
  367 +
  368 +int board_nand_init(struct nand_chip *nand)
  369 +{
  370 + nand->ecc.mode = NAND_ECC_SOFT;
  371 +
  372 + /* Reference hardware control function */
  373 + nand->cmd_ctrl = ids_nand_hwctrl;
  374 + nand->read_byte = ids_nand_read_byte;
  375 + nand->write_buf = ids_nand_write_buf;
  376 + nand->read_buf = ids_nand_read_buf;
  377 + nand->dev_ready = ids_nand_dev_ready;
  378 + nand->chip_delay = 12;
  379 +
  380 + return 0;
  381 +}
  382 +
  383 +#endif /* CONFIG_CMD_NAND */
  384 +
  385 +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  386 +void ft_board_setup(void *blob, bd_t *bd)
  387 +{
  388 + ft_cpu_setup( blob, bd);
  389 +}
  390 +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
board/ids/ids8313/Makefile
Diff comments   View file @ b71bf4a
  1 +#
  2 +# (C) Copyright 2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2013
  6 +# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
  7 +#
  8 +# SPDX-License-Identifier: GPL-2.0+
  9 +#
  10 +
  11 +obj-y = ids8313.o
board/ids/ids8313/ids8313.c
Diff comments   View file @ b71bf4a
  1 +/*
  2 + * (C) Copyright 2013
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * Based on:
  6 + * Copyright (c) 2011 IDS GmbH, Germany
  7 + * ids8313.c - ids8313 board support.
  8 + *
  9 + * Sergej Stepanov <ste@ids.de>
  10 + * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
  11 + *
  12 + * SPDX-License-Identifier: GPL-2.0+
  13 + */
  14 +
  15 +#include <common.h>
  16 +#include <mpc83xx.h>
  17 +#include <spi.h>
  18 +#include <libfdt.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +/** CPLD contains the info about:
  22 + * - board type: *pCpld & 0xF0
  23 + * - hw-revision: *pCpld & 0x0F
  24 + * - cpld-revision: *pCpld+1
  25 + */
  26 +int checkboard(void)
  27 +{
  28 + char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
  29 + u8 u8Vers = readb(pcpld);
  30 + u8 u8Revs = readb(pcpld + 1);
  31 +
  32 + printf("Board: ");
  33 + switch (u8Vers & 0xF0) {
  34 + case '\x40':
  35 + printf("CU73X");
  36 + break;
  37 + case '\x50':
  38 + printf("CC73X");
  39 + break;
  40 + default:
  41 + printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
  42 + return 0;
  43 + }
  44 + printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
  45 + u8Vers & 0x0F, u8Revs & 0xFF);
  46 + return 0;
  47 +}
  48 +
  49 +/*
  50 + * fixed sdram init
  51 + */
  52 +int fixed_sdram(unsigned long config)
  53 +{
  54 + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  55 + u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  56 +
  57 +#ifndef CONFIG_SYS_RAMBOOT
  58 + u32 msize_log2 = __ilog2(msize);
  59 +
  60 + out_be32(&im->sysconf.ddrlaw[0].bar,
  61 + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
  62 + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
  63 + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  64 + sync();
  65 +
  66 + /*
  67 + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  68 + * or the DDR2 controller may fail to initialize correctly.
  69 + */
  70 + udelay(50000);
  71 +
  72 + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
  73 + out_be32(&im->ddr.cs_config[0], config);
  74 +
  75 + /* currently we use only one CS, so disable the other banks */
  76 + out_be32(&im->ddr.cs_config[1], 0);
  77 + out_be32(&im->ddr.cs_config[2], 0);
  78 + out_be32(&im->ddr.cs_config[3], 0);
  79 +
  80 + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  81 + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  82 + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  83 + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  84 +
  85 + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
  86 + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
  87 +
  88 + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  89 + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
  90 +
  91 + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  92 + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  93 + sync();
  94 + udelay(300);
  95 +
  96 + /* enable DDR controller */
  97 + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  98 + /* now check the real size */
  99 + disable_addr_trans();
  100 + msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
  101 + enable_addr_trans();
  102 +#endif
  103 + return msize;
  104 +}
  105 +
  106 +static int setup_sdram(void)
  107 +{
  108 + u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  109 + long int size_01, size_02;
  110 +
  111 + size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  112 + size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
  113 +
  114 + if (size_01 > size_02)
  115 + msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  116 + else
  117 + msize = size_02;
  118 +
  119 + return msize;
  120 +}
  121 +
  122 +phys_size_t initdram(int board_type)
  123 +{
  124 + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  125 + fsl_lbc_t *lbc = &im->im_lbc;
  126 + u32 msize = 0;
  127 +
  128 + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  129 + return -1;
  130 +
  131 + msize = setup_sdram();
  132 +
  133 + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  134 + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
  135 + sync();
  136 +
  137 + return msize;
  138 +}
  139 +
  140 +#if defined(CONFIG_OF_BOARD_SETUP)
  141 +void ft_board_setup(void *blob, bd_t *bd)
  142 +{
  143 + ft_cpu_setup(blob, bd);
  144 +}
  145 +#endif
  146 +
  147 +/* gpio mask for spi_cs */
  148 +#define IDSCPLD_SPI_CS_MASK 0x00000001
  149 +/* spi_cs multiplexed through cpld */
  150 +#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
  151 +
  152 +#if defined(CONFIG_MISC_INIT_R)
  153 +/* srp umcr mask for rts */
  154 +#define IDSUMCR_RTS_MASK 0x04
  155 +int misc_init_r(void)
  156 +{
  157 + /*srp*/
  158 + duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
  159 + duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
  160 +
  161 + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  162 + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  163 +
  164 + /* deactivate spi_cs channels */
  165 + out_8(spi_base, 0);
  166 + /* deactivate the spi_cs */
  167 + setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
  168 + /*srp - deactivate rts*/
  169 + out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
  170 + out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
  171 +
  172 +
  173 + gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
  174 + return 0;
  175 +}
  176 +#endif
  177 +
  178 +#ifdef CONFIG_MPC8XXX_SPI
  179 +/*
  180 + * The following are used to control the SPI chip selects
  181 + */
  182 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  183 +{
  184 + return bus == 0 && ((cs >= 0) && (cs <= 2));
  185 +}
  186 +
  187 +void spi_cs_activate(struct spi_slave *slave)
  188 +{
  189 + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  190 + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  191 +
  192 + /* select the spi_cs channel */
  193 + out_8(spi_base, 1 << slave->cs);
  194 + /* activate the spi_cs */
  195 + clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  196 +}
  197 +
  198 +void spi_cs_deactivate(struct spi_slave *slave)
  199 +{
  200 + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  201 + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  202 +
  203 + /* select the spi_cs channel */
  204 + out_8(spi_base, 1 << slave->cs);
  205 + /* deactivate the spi_cs */
  206 + setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  207 +}
  208 +#endif /* CONFIG_HARD_SPI */
board/ids8247/Makefile
View file @ b71bf4a
1   -#
2   -# (C) Copyright 2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# (C) Copyright 2005
6   -# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -obj-y = ids8247.o
board/ids8247/ids8247.c
View file @ b71bf4a
1   -/*
2   - * (C) Copyright 2005
3   - * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <ioports.h>
10   -#include <mpc8260.h>
11   -
12   -#if defined(CONFIG_OF_LIBFDT)
13   -#include <libfdt.h>
14   -#include <libfdt_env.h>
15   -#include <fdt_support.h>
16   -#endif
17   -
18   -DECLARE_GLOBAL_DATA_PTR;
19   -
20   -/*
21   - * I/O Port configuration table
22   - *
23   - * if conf is 1, then that port pin will be configured at boot time
24   - * according to the five values podr/pdir/ppar/psor/pdat for that entry
25   - */
26   -
27   -const iop_conf_t iop_conf_tab[4][32] = {
28   -
29   - /* Port A configuration */
30   - { /* conf ppar psor pdir podr pdat */
31   - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
32   - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
33   - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
34   - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
35   - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
36   - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
37   - /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
38   -#if defined(CONFIG_SYS_I2C_SOFT)
39   - /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
40   - /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
41   -#else /* normal I/O port pins */
42   - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
43   - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
44   -#endif
45   - /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
46   - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
47   - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
48   - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
49   - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
50   - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
51   - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
52   - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
53   - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
54   - /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
55   - /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
56   - /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
57   - /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
58   - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
59   - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
60   - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
61   - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
62   - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
63   - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
64   - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
65   - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
66   - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
67   - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
68   - },
69   -
70   - /* Port B configuration */
71   - { /* conf ppar psor pdir podr pdat */
72   - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
73   - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
74   - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
75   - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
76   - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
77   - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
78   - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
79   - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
80   - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
81   - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
82   - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
83   - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
84   - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
85   - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
86   - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
87   - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
88   - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
89   - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
90   - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
91   - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
92   - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
93   - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
94   - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
95   - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
96   - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
97   - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
98   - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
99   - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
100   - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
101   - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
102   - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
103   - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
104   - },
105   -
106   - /* Port C */
107   - { /* conf ppar psor pdir podr pdat */
108   - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
109   - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
110   - /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
111   - /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
112   - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
113   - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
114   - /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
115   - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
116   - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
117   - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
118   - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
119   - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
120   - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
121   - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
122   - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
123   - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
124   - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
125   - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
126   - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
127   - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
128   - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
129   - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
130   - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
131   - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
132   - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
133   - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
134   - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
135   - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
136   - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
137   - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
138   - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
139   - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
140   - },
141   -
142   - /* Port D */
143   - { /* conf ppar psor pdir podr pdat */
144   - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
145   - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
146   - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
147   - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
148   - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
149   - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
150   - /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
151   - /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
152   - /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
153   - /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
154   - /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
155   - /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
156   - /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
157   - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
158   - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
159   - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
160   -#if defined(CONFIG_HARD_I2C)
161   - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
162   - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
163   -#else /* normal I/O port pins */
164   - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
165   - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
166   -#endif
167   - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
168   - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
169   - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
170   - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
171   - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
172   - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
173   - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
174   - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
175   - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
176   - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
177   - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178   - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179   - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180   - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
181   - }
182   -};
183   -
184   -/* ------------------------------------------------------------------------- */
185   -
186   -/* Check Board Identity:
187   - */
188   -int checkboard (void)
189   -{
190   - puts ("Board: IDS 8247\n");
191   - return 0;
192   -}
193   -
194   -/* ------------------------------------------------------------------------- */
195   -
196   -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
197   - *
198   - * This routine performs standard 8260 initialization sequence
199   - * and calculates the available memory size. It may be called
200   - * several times to try different SDRAM configurations on both
201   - * 60x and local buses.
202   - */
203   -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
204   - ulong orx, volatile uchar * base)
205   -{
206   - volatile uchar c = 0xff;
207   - volatile uint *sdmr_ptr;
208   - volatile uint *orx_ptr;
209   - ulong maxsize, size;
210   - int i;
211   -
212   - /* We must be able to test a location outsize the maximum legal size
213   - * to find out THAT we are outside; but this address still has to be
214   - * mapped by the controller. That means, that the initial mapping has
215   - * to be (at least) twice as large as the maximum expected size.
216   - */
217   - maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
218   -
219   - sdmr_ptr = &memctl->memc_psdmr;
220   - orx_ptr = &memctl->memc_or2;
221   -
222   - *orx_ptr = orx;
223   -
224   - /*
225   - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
226   - *
227   - * "At system reset, initialization software must set up the
228   - * programmable parameters in the memory controller banks registers
229   - * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
230   - * system software should execute the following initialization sequence
231   - * for each SDRAM device.
232   - *
233   - * 1. Issue a PRECHARGE-ALL-BANKS command
234   - * 2. Issue eight CBR REFRESH commands
235   - * 3. Issue a MODE-SET command to initialize the mode register
236   - *
237   - * The initial commands are executed by setting P/LSDMR[OP] and
238   - * accessing the SDRAM with a single-byte transaction."
239   - *
240   - * The appropriate BRx/ORx registers have already been set when we
241   - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
242   - */
243   -
244   - *sdmr_ptr = sdmr | PSDMR_OP_PREA;
245   - *base = c;
246   -
247   - *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
248   - for (i = 0; i < 8; i++)
249   - *base = c;
250   -
251   - *sdmr_ptr = sdmr | PSDMR_OP_MRW;
252   - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
253   -
254   - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
255   - *base = c;
256   -
257   - size = get_ram_size((long *)base, maxsize);
258   - *orx_ptr = orx | ~(size - 1);
259   -
260   - return (size);
261   -}
262   -
263   -phys_size_t initdram (int board_type)
264   -{
265   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
266   - volatile memctl8260_t *memctl = &immap->im_memctl;
267   -
268   - long psize;
269   -
270   - psize = 16 * 1024 * 1024;
271   -
272   - memctl->memc_psrt = CONFIG_SYS_PSRT;
273   - memctl->memc_mptpr = CONFIG_SYS_MPTPR;
274   -
275   -#ifndef CONFIG_SYS_RAMBOOT
276   - /* 60x SDRAM setup:
277   - */
278   - psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
279   - (uchar *) CONFIG_SYS_SDRAM_BASE);
280   -#endif /* CONFIG_SYS_RAMBOOT */
281   -
282   - icache_enable ();
283   -
284   - return (psize);
285   -}
286   -
287   -int misc_init_r (void)
288   -{
289   - gd->bd->bi_flashstart = 0xff800000;
290   - return 0;
291   -}
292   -
293   -#if defined(CONFIG_CMD_NAND)
294   -#include <nand.h>
295   -#include <linux/mtd/mtd.h>
296   -#include <asm/io.h>
297   -
298   -static u8 hwctl;
299   -
300   -static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
301   -{
302   - struct nand_chip *this = mtd->priv;
303   -
304   - if (ctrl & NAND_CTRL_CHANGE) {
305   - if ( ctrl & NAND_CLE ) {
306   - hwctl |= 0x1;
307   - writeb(0x00, (this->IO_ADDR_W + 0x0a));
308   - } else {
309   - hwctl &= ~0x1;
310   - writeb(0x00, (this->IO_ADDR_W + 0x08));
311   - }
312   - if ( ctrl & NAND_ALE ) {
313   - hwctl |= 0x2;
314   - writeb(0x00, (this->IO_ADDR_W + 0x09));
315   - } else {
316   - hwctl &= ~0x2;
317   - writeb(0x00, (this->IO_ADDR_W + 0x08));
318   - }
319   - if ( (ctrl & NAND_NCE) != NAND_NCE)
320   - writeb(0x00, (this->IO_ADDR_W + 0x0c));
321   - else
322   - writeb(0x00, (this->IO_ADDR_W + 0x08));
323   - }
324   - if (cmd != NAND_CMD_NONE)
325   - writeb(cmd, this->IO_ADDR_W);
326   -
327   -}
328   -
329   -static u_char ids_nand_read_byte(struct mtd_info *mtd)
330   -{
331   - struct nand_chip *this = mtd->priv;
332   -
333   - return readb(this->IO_ADDR_R);
334   -}
335   -
336   -static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
337   -{
338   - struct nand_chip *nand = mtd->priv;
339   - int i;
340   -
341   - for (i = 0; i < len; i++) {
342   - if (hwctl & 0x1)
343   - writeb(buf[i], (nand->IO_ADDR_W + 0x02));
344   - else if (hwctl & 0x2)
345   - writeb(buf[i], (nand->IO_ADDR_W + 0x01));
346   - else
347   - writeb(buf[i], nand->IO_ADDR_W);
348   - }
349   -}
350   -
351   -static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
352   -{
353   - struct nand_chip *this = mtd->priv;
354   - int i;
355   -
356   - for (i = 0; i < len; i++) {
357   - buf[i] = readb(this->IO_ADDR_R);
358   - }
359   -}
360   -
361   -static int ids_nand_dev_ready(struct mtd_info *mtd)
362   -{
363   - /* constant delay (see also tR in the datasheet) */
364   - udelay(12);
365   - return 1;
366   -}
367   -
368   -int board_nand_init(struct nand_chip *nand)
369   -{
370   - nand->ecc.mode = NAND_ECC_SOFT;
371   -
372   - /* Reference hardware control function */
373   - nand->cmd_ctrl = ids_nand_hwctrl;
374   - nand->read_byte = ids_nand_read_byte;
375   - nand->write_buf = ids_nand_write_buf;
376   - nand->read_buf = ids_nand_read_buf;
377   - nand->dev_ready = ids_nand_dev_ready;
378   - nand->chip_delay = 12;
379   -
380   - return 0;
381   -}
382   -
383   -#endif /* CONFIG_CMD_NAND */
384   -
385   -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
386   -void ft_board_setup(void *blob, bd_t *bd)
387   -{
388   - ft_cpu_setup( blob, bd);
389   -}
390   -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
... ... @@ -649,7 +649,8 @@
649 649 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
650 650 Active powerpc mpc8260 - - cpu87 CPU87 - -
651 651 Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
652   -Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
  652 +Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
  653 +Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
653 654 Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
654 655 Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
655 656 Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
... ... @@ -718,6 +719,7 @@
718 719 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
719 720 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
720 721 Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
  722 +Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
721 723 Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
722 724 Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
723 725 Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
include/configs/ids8313.h
Diff comments   View file @ b71bf4a
  1 +/*
  2 + * (C) Copyright 2013
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * Based on:
  6 + * Copyright (c) 2011 IDS GmbH, Germany
  7 + * Sergej Stepanov <ste@ids.de>
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __CONFIG_H
  13 +#define __CONFIG_H
  14 +
  15 +/*
  16 + * High Level Configuration Options
  17 + */
  18 +#define CONFIG_MPC831x
  19 +#define CONFIG_MPC8313
  20 +#define CONFIG_IDS8313
  21 +
  22 +#define CONFIG_FSL_ELBC
  23 +
  24 +#define CONFIG_MISC_INIT_R
  25 +
  26 +#define CONFIG_AUTOBOOT_KEYED
  27 +#define CONFIG_AUTOBOOT_PROMPT \
  28 + "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
  29 +#define CONFIG_AUTOBOOT_DELAY_STR "ids"
  30 +#define CONFIG_BOOT_RETRY_TIME 900
  31 +#define CONFIG_BOOT_RETRY_MIN 30
  32 +#define CONFIG_BOOTDELAY 1
  33 +#define CONFIG_RESET_TO_RETRY
  34 +
  35 +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  36 +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  37 +
  38 +#define CONFIG_SYS_IMMR 0xF0000000
  39 +
  40 +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  41 +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  42 +
  43 +/*
  44 + * Hardware Reset Configuration Word
  45 + * if CLKIN is 66.000MHz, then
  46 + * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  47 + */
  48 +#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  49 + HRCWL_DDR_TO_SCB_CLK_2X1 |\
  50 + HRCWL_CSB_TO_CLKIN_2X1 |\
  51 + HRCWL_CORE_TO_CSB_2X1)
  52 +
  53 +#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
  54 + HRCWH_CORE_ENABLE |\
  55 + HRCWH_FROM_0XFFF00100 |\
  56 + HRCWH_BOOTSEQ_DISABLE |\
  57 + HRCWH_SW_WATCHDOG_DISABLE |\
  58 + HRCWH_ROM_LOC_LOCAL_8BIT |\
  59 + HRCWH_RL_EXT_LEGACY |\
  60 + HRCWH_TSEC1M_IN_MII |\
  61 + HRCWH_TSEC2M_IN_MII |\
  62 + HRCWH_BIG_ENDIAN)
  63 +
  64 +#define CONFIG_SYS_SICRH 0x00000000
  65 +#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
  66 +
  67 +#define CONFIG_HWCONFIG
  68 +
  69 +#define CONFIG_SYS_HID0_INIT 0x000000000
  70 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
  71 + HID0_ENABLE_INSTRUCTION_CACHE |\
  72 + HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  73 +
  74 +#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  75 +
  76 +/*
  77 + * Definitions for initial stack pointer and data area (in DCACHE )
  78 + */
  79 +#define CONFIG_SYS_INIT_RAM_LOCK
  80 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  81 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
  82 +#define CONFIG_SYS_GBL_DATA_SIZE 0x100
  83 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  84 + - CONFIG_SYS_GBL_DATA_SIZE)
  85 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  86 +
  87 +/*
  88 + * Local Bus LCRR and LBCR regs
  89 + */
  90 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  91 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  92 +#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
  93 + (0xFF << LBCR_BMT_SHIFT) |\
  94 + 0xF)
  95 +
  96 +#define CONFIG_SYS_LBC_MRTPR 0x20000000
  97 +
  98 +/*
  99 + * Internal Definitions
  100 + */
  101 +/*
  102 + * DDR Setup
  103 + */
  104 +#define CONFIG_SYS_DDR_BASE 0x00000000
  105 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  106 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  107 +
  108 +/*
  109 + * Manually set up DDR parameters,
  110 + * as this board has not the SPD connected to I2C.
  111 + */
  112 +#define CONFIG_SYS_DDR_SIZE 256 /* MB */
  113 +#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
  114 + 0x00010000 |\
  115 + CSCONFIG_ROW_BIT_13 |\
  116 + CSCONFIG_COL_BIT_10)
  117 +
  118 +#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
  119 + CSCONFIG_BANK_BIT_3)
  120 +
  121 +#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
  122 +#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  123 + (3 << TIMING_CFG0_WRT_SHIFT) |\
  124 + (3 << TIMING_CFG0_RRT_SHIFT) |\
  125 + (3 << TIMING_CFG0_WWT_SHIFT) |\
  126 + (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  127 + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  128 + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  129 + (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  130 +#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  131 + (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  132 + (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  133 + (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  134 + (4 << TIMING_CFG1_REFREC_SHIFT) |\
  135 + (4 << TIMING_CFG1_WRREC_SHIFT) |\
  136 + (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
  137 + (2 << TIMING_CFG1_WRTORD_SHIFT))
  138 +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
  139 + (5 << TIMING_CFG2_CPO_SHIFT) |\
  140 + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
  141 + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
  142 + (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
  143 + (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
  144 + (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  145 +
  146 +#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
  147 + (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  148 +
  149 +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
  150 + SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
  151 + SDRAM_CFG_DBW_32 |\
  152 + SDRAM_CFG_SDRAM_TYPE_DDR2)
  153 +
  154 +#define CONFIG_SYS_SDRAM_CFG2 0x00401000
  155 +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
  156 + (0x0242 << SDRAM_MODE_SD_SHIFT))
  157 +#define CONFIG_SYS_DDR_MODE_2 0x00000000
  158 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
  159 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
  160 + DDRCDR_PZ_NOMZ |\
  161 + DDRCDR_NZ_NOMZ |\
  162 + DDRCDR_ODT |\
  163 + DDRCDR_M_ODR |\
  164 + DDRCDR_Q_DRN)
  165 +
  166 +/*
  167 + * on-board devices
  168 + */
  169 +#define CONFIG_TSEC1
  170 +#define CONFIG_TSEC2
  171 +#define CONFIG_TSEC_ENET
  172 +#define CONFIG_NET_MULTI
  173 +#define CONFIG_HARD_SPI
  174 +#define CONFIG_HARD_I2C
  175 +
  176 +/*
  177 + * NOR FLASH setup
  178 + */
  179 +#define CONFIG_SYS_FLASH_CFI
  180 +#define CONFIG_FLASH_CFI_DRIVER
  181 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  182 +#define CONFIG_FLASH_SHOW_PROGRESS 50
  183 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  184 +
  185 +#define CONFIG_SYS_FLASH_BASE 0xFF800000
  186 +#define CONFIG_SYS_FLASH_SIZE 8
  187 +#define CONFIG_SYS_FLASH_PROTECTION
  188 +
  189 +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  190 +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
  191 +
  192 +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  193 + BR_PS_8 |\
  194 + BR_MS_GPCM |\
  195 + BR_V)
  196 +
  197 +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  198 + OR_GPCM_SCY_10 |\
  199 + OR_GPCM_EHTR |\
  200 + OR_GPCM_TRLX |\
  201 + OR_GPCM_CSNT |\
  202 + OR_GPCM_EAD)
  203 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  204 +#define CONFIG_SYS_MAX_FLASH_SECT 128
  205 +
  206 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
  207 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500
  208 +
  209 +/*
  210 + * NAND FLASH setup
  211 + */
  212 +#define CONFIG_SYS_NAND_BASE 0xE1000000
  213 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  214 +#define CONFIG_SYS_NAND_MAX_CHIPS 1
  215 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  216 +#define CONFIG_NAND_FSL_ELBC
  217 +#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
  218 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  219 +#define NAND_CACHE_PAGES 64
  220 +
  221 +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  222 +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
  223 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  224 +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  225 +
  226 +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
  227 + (2<<BR_DECC_SHIFT) |\
  228 + BR_PS_8 |\
  229 + BR_MS_FCM |\
  230 + BR_V)
  231 +
  232 +#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
  233 + OR_FCM_PGS |\
  234 + OR_FCM_CSCT |\
  235 + OR_FCM_CST |\
  236 + OR_FCM_CHT |\
  237 + OR_FCM_SCY_4 |\
  238 + OR_FCM_TRLX |\
  239 + OR_FCM_EHTR |\
  240 + OR_FCM_RST)
  241 +
  242 +/*
  243 + * MRAM setup
  244 + */
  245 +#define CONFIG_SYS_MRAM_BASE 0xE2000000
  246 +#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
  247 +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
  248 +#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
  249 +
  250 +#define CONFIG_SYS_OR_TIMING_MRAM
  251 +
  252 +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
  253 + BR_PS_8 |\
  254 + BR_MS_GPCM |\
  255 + BR_V)
  256 +
  257 +#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
  258 +
  259 +/*
  260 + * CPLD setup
  261 + */
  262 +#define CONFIG_SYS_CPLD_BASE 0xE3000000
  263 +#define CONFIG_SYS_CPLD_SIZE 0x8000
  264 +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
  265 +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
  266 +
  267 +#define CONFIG_SYS_OR_TIMING_MRAM
  268 +
  269 +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
  270 + BR_PS_8 |\
  271 + BR_MS_GPCM |\
  272 + BR_V)
  273 +
  274 +#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
  275 +
  276 +/*
  277 + * HW-Watchdog
  278 + */
  279 +#define CONFIG_WATCHDOG 1
  280 +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  281 +
  282 +/*
  283 + * I2C setup
  284 + */
  285 +#define CONFIG_CMD_I2C
  286 +#define CONFIG_SYS_I2C
  287 +#define CONFIG_SYS_I2C_FSL
  288 +#define CONFIG_SYS_FSL_I2C_SPEED 400000
  289 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  290 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  291 +#define CONFIG_RTC_PCF8563
  292 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51
  293 +
  294 +/*
  295 + * SPI setup
  296 + */
  297 +#ifdef CONFIG_HARD_SPI
  298 +#define CONFIG_MPC8XXX_SPI
  299 +#define CONFIG_CMD_SPI
  300 +#define CONFIG_SYS_GPIO1_PRELIM
  301 +#define CONFIG_SYS_GPIO1_DIR 0x00000001
  302 +#define CONFIG_SYS_GPIO1_DAT 0x00000001
  303 +#endif
  304 +
  305 +/*
  306 + * Ethernet setup
  307 + */
  308 +#ifdef CONFIG_TSEC1
  309 +#define CONFIG_HAS_ETH0
  310 +#define CONFIG_TSEC1_NAME "TSEC0"
  311 +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
  312 +#define TSEC1_PHY_ADDR 0x1
  313 +#define TSEC1_FLAGS TSEC_GIGABIT
  314 +#define TSEC1_PHYIDX 0
  315 +#endif
  316 +
  317 +#ifdef CONFIG_TSEC2
  318 +#define CONFIG_HAS_ETH1
  319 +#define CONFIG_TSEC2_NAME "TSEC1"
  320 +#define CONFIG_SYS_TSEC2_OFFSET 0x25000
  321 +#define TSEC2_PHY_ADDR 0x3
  322 +#define TSEC2_FLAGS TSEC_GIGABIT
  323 +#define TSEC2_PHYIDX 0
  324 +#endif
  325 +#define CONFIG_ETHPRIME "TSEC1"
  326 +
  327 +/*
  328 + * Serial Port
  329 + */
  330 +#define CONFIG_CONS_INDEX 1
  331 +#define CONFIG_SYS_NS16550
  332 +#define CONFIG_SYS_NS16550_SERIAL
  333 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  334 +
  335 +#define CONFIG_SYS_BAUDRATE_TABLE \
  336 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  337 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  338 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  339 +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  340 +
  341 +#define CONFIG_HAS_FSL_DR_USB
  342 +#define CONFIG_SYS_SCCR_USBDRCM 3
  343 +
  344 +/*
  345 + * BAT's
  346 + */
  347 +#define CONFIG_HIGH_BATS
  348 +
  349 +/* DDR @ 0x00000000 */
  350 +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
  351 + BATL_PP_10)
  352 +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
  353 + BATU_BL_256M |\
  354 + BATU_VS |\
  355 + BATU_VP)
  356 +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  357 +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  358 +
  359 +/* Initial RAM @ 0xFD000000 */
  360 +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
  361 + BATL_PP_10 |\
  362 + BATL_GUARDEDSTORAGE)
  363 +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
  364 + BATU_BL_256K |\
  365 + BATU_VS |\
  366 + BATU_VP)
  367 +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  368 +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  369 +
  370 +/* FLASH @ 0xFF800000 */
  371 +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
  372 + BATL_PP_10 |\
  373 + BATL_GUARDEDSTORAGE)
  374 +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
  375 + BATU_BL_8M |\
  376 + BATU_VS |\
  377 + BATU_VP)
  378 +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
  379 + BATL_PP_10 |\
  380 + BATL_CACHEINHIBIT |\
  381 + BATL_GUARDEDSTORAGE)
  382 +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  383 +
  384 +#define CONFIG_SYS_IBAT3L (0)
  385 +#define CONFIG_SYS_IBAT3U (0)
  386 +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  387 +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  388 +
  389 +#define CONFIG_SYS_IBAT4L (0)
  390 +#define CONFIG_SYS_IBAT4U (0)
  391 +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  392 +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  393 +
  394 +/* IMMRBAR @ 0xF0000000 */
  395 +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
  396 + BATL_PP_10 |\
  397 + BATL_CACHEINHIBIT |\
  398 + BATL_GUARDEDSTORAGE)
  399 +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
  400 + BATU_BL_128M |\
  401 + BATU_VS |\
  402 + BATU_VP)
  403 +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  404 +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  405 +
  406 +/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
  407 +#define CONFIG_SYS_IBAT6L (0xE0000000 |\
  408 + BATL_PP_10 |\
  409 + BATL_GUARDEDSTORAGE)
  410 +#define CONFIG_SYS_IBAT6U (0xE0000000 |\
  411 + BATU_BL_256M |\
  412 + BATU_VS |\
  413 + BATU_VP)
  414 +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  415 +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  416 +
  417 +#define CONFIG_SYS_IBAT7L (0)
  418 +#define CONFIG_SYS_IBAT7U (0)
  419 +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  420 +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  421 +
  422 +/*
  423 + * U-Boot environment setup
  424 + */
  425 +#include <config_cmd_default.h>
  426 +
  427 +#define CONFIG_CMD_DHCP
  428 +#define CONFIG_CMD_PING
  429 +#define CONFIG_CMD_NFS
  430 +#define CONFIG_CMD_NAND
  431 +#define CONFIG_CMD_FLASH
  432 +#define CONFIG_CMD_SNTP
  433 +#define CONFIG_CMD_MII
  434 +#define CONFIG_CMD_DATE
  435 +#define CONFIG_CMDLINE_EDITING
  436 +#define CONFIG_CMD_EDITENV
  437 +#define CONFIG_CMD_JFFS2
  438 +#define CONFIG_BOOTP_SUBNETMASK
  439 +#define CONFIG_BOOTP_GATEWAY
  440 +#define CONFIG_BOOTP_HOSTNAME
  441 +#define CONFIG_BOOTP_BOOTPATH
  442 +#define CONFIG_BOOTP_BOOTFILESIZE
  443 +/* pass open firmware flat tree */
  444 +#define CONFIG_OF_LIBFDT
  445 +#define CONFIG_OF_BOARD_SETUP
  446 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  447 +
  448 +/*
  449 + * The reserved memory
  450 + */
  451 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  452 +#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  453 +#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
  454 +
  455 +/*
  456 + * Environment Configuration
  457 + */
  458 +#define CONFIG_ENV_IS_IN_FLASH
  459 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
  460 + + CONFIG_SYS_MONITOR_LEN)
  461 +#define CONFIG_ENV_SIZE 0x20000
  462 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  463 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  464 +
  465 +
  466 +#define CONFIG_NETDEV eth1
  467 +#define CONFIG_HOSTNAME ids8313
  468 +#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
  469 +#define CONFIG_BOOTFILE "ids8313/uImage"
  470 +#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
  471 +#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
  472 +#define CONFIG_LOADADDR 0x400000
  473 +#define CONFIG_CMD_ENV_FLAGS
  474 +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
  475 +
  476 +#define CONFIG_BAUDRATE 115200
  477 +#define CONFIG_SYS_HZ 1000
  478 +
  479 +/* Initial Memory map for Linux*/
  480 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  481 +
  482 +/*
  483 + * Miscellaneous configurable options
  484 + */
  485 +#define CONFIG_SYS_LONGHELP
  486 +#define CONFIG_SYS_PROMPT "=> "
  487 +#define CONFIG_SYS_CBSIZE 1024
  488 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
  489 + + sizeof(CONFIG_SYS_PROMPT)+16)
  490 +#define CONFIG_SYS_MAXARGS 16
  491 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  492 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  493 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  494 +
  495 +#define CONFIG_SYS_MEMTEST_START 0x00001000
  496 +#define CONFIG_SYS_MEMTEST_END 0x00C00000
  497 +
  498 +#define CONFIG_SYS_LOAD_ADDR 0x100000
  499 +#define CONFIG_MII
  500 +#define CONFIG_LOADS_ECHO
  501 +#define CONFIG_TIMESTAMP
  502 +#define CONFIG_PREBOOT "echo;" \
  503 + "echo Type \\\"run nfsboot\\\" " \
  504 + "to mount root filesystem over NFS;echo"
  505 +#undef CONFIG_BOOTARGS
  506 +#define CONFIG_BOOTCOMMAND "run boot_cramfs"
  507 +#undef CONFIG_SYS_LOADS_BAUD_CHANGE
  508 +
  509 +#define CONFIG_JFFS2_NAND
  510 +#define CONFIG_JFFS2_DEV "0"
  511 +
  512 +/* mtdparts command line support */
  513 +#define CONFIG_CMD_MTDPARTS
  514 +#define CONFIG_FLASH_CFI_MTD
  515 +#define CONFIG_MTD_DEVICE
  516 +#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
  517 +#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \
  518 + "768k(BOOT-BIN)," \
  519 + "128k(BOOT-ENV),128k(BOOT-REDENV);" \
  520 + "e1000000.flash:-(ubi)"
  521 +
  522 +#define CONFIG_EXTRA_ENV_SETTINGS \
  523 + "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  524 + "ethprime=TSEC1\0" \
  525 + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  526 + "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
  527 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  528 + " +${filesize}; " \
  529 + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  530 + " +${filesize}; " \
  531 + "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  532 + " ${filesize}; " \
  533 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  534 + " +${filesize}; " \
  535 + "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  536 + " ${filesize}\0" \
  537 + "console=ttyS0\0" \
  538 + "fdtaddr=0x780000\0" \
  539 + "kernel_addr=ff800000\0" \
  540 + "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
  541 + "setbootargs=setenv bootargs " \
  542 + "root=${rootdev} rw console=${console}," \
  543 + "${baudrate} ${othbootargs}\0" \
  544 + "setipargs=setenv bootargs root=${rootdev} rw " \
  545 + "nfsroot=${serverip}:${rootpath} " \
  546 + "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  547 + "${netmask}:${hostname}:${netdev}:off " \
  548 + "console=${console},${baudrate} ${othbootargs}\0" \
  549 + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  550 + "mtdids=" MTDIDS_DEFAULT "\0" \
  551 + "mtdparts=" MTDPARTS_DEFAULT "\0" \
  552 + "\0"
  553 +
  554 +#define CONFIG_NFSBOOTCOMMAND \
  555 + "setenv rootdev /dev/nfs;" \
  556 + "run setipargs;run addmtd;" \
  557 + "tftp ${loadaddr} ${bootfile};" \
  558 + "tftp ${fdtaddr} ${fdtfile};" \
  559 + "fdt addr ${fdtaddr};" \
  560 + "bootm ${loadaddr} - ${fdtaddr}"
  561 +
  562 +/* UBI Support */
  563 +#define CONFIG_CMD_NAND_TRIMFFS
  564 +#define CONFIG_CMD_UBI
  565 +#define CONFIG_CMD_UBIFS
  566 +#define CONFIG_RBTREE
  567 +#define CONFIG_LZO
  568 +#define CONFIG_MTD_PARTITIONS
  569 +
  570 +/* bootcount support */
  571 +#define CONFIG_BOOTCOUNT_LIMIT
  572 +#define CONFIG_BOOTCOUNT_I2C
  573 +#define CONFIG_BOOTCOUNT_ALEN 1
  574 +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
  575 +
  576 +#define CONFIG_VERSION_VARIABLE
  577 +
  578 +#define CONFIG_FIT
  579 +#define CONFIG_FIT_SIGNATURE
  580 +#define CONFIG_CMD_FDT
  581 +#define CONFIG_CMD_HASH
  582 +#define CONFIG_RSA
  583 +#define CONFIG_SHA1
  584 +#define CONFIG_SHA256
  585 +#define CONFIG_OF_CONTROL
  586 +
  587 +#endif /* __CONFIG_H */