Eric Lee / smarc-uboot

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Commit b736e4b929197b5141b883f4f3906c4bd38dd4f3

Authored by Stefano Babic
1 parent 01968b96a2
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: Fix start.S when used with SPL in arm1136 

This patch modifies start.S for the arm1136 to make it
conform to start.S  in armv7 architecture, to make it
usable if the SPL framework is used.

Signed-off-by: Stefano Babic <sbabic@denx.de>

Showing 3 changed files with 24 additions and 11 deletions Inline Diff

arch/arm/cpu/arm1136/start.S
Diff comments   View file @ b736e4b
1 /* 1 /*
2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
3 * 3 *
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
5 * 5 *
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * 11 *
12 * See file CREDITS for list of people who contributed to this 12 * See file CREDITS for list of people who contributed to this
13 * project. 13 * project.
14 * 14 *
15 * This program is free software; you can redistribute it and/or 15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as 16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of 17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version. 18 * the License, or (at your option) any later version.
19 * 19 *
20 * This program is distributed in the hope that it will be useful, 20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details. 23 * GNU General Public License for more details.
24 * 24 *
25 * You should have received a copy of the GNU General Public License 25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software 26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA 28 * MA 02111-1307 USA
29 */ 29 */
30 30
31 #include <asm-offsets.h> 31 #include <asm-offsets.h>
32 #include <config.h> 32 #include <config.h>
33 #include <version.h> 33 #include <version.h>
34 .globl _start 34 .globl _start
35 _start: b reset 35 _start: b reset
36 #ifdef CONFIG_SPL_BUILD 36 #ifdef CONFIG_SPL_BUILD
37 ldr pc, _hang 37 ldr pc, _hang
38 ldr pc, _hang 38 ldr pc, _hang
39 ldr pc, _hang 39 ldr pc, _hang
40 ldr pc, _hang 40 ldr pc, _hang
41 ldr pc, _hang 41 ldr pc, _hang
42 ldr pc, _hang 42 ldr pc, _hang
43 ldr pc, _hang 43 ldr pc, _hang
44 44
45 _hang: 45 _hang:
46 .word do_hang 46 .word do_hang
47 .word 0x12345678 47 .word 0x12345678
48 .word 0x12345678 48 .word 0x12345678
49 .word 0x12345678 49 .word 0x12345678
50 .word 0x12345678 50 .word 0x12345678
51 .word 0x12345678 51 .word 0x12345678
52 .word 0x12345678 52 .word 0x12345678
53 .word 0x12345678 /* now 16*4=64 */ 53 .word 0x12345678 /* now 16*4=64 */
54 #else 54 #else
55 ldr pc, _undefined_instruction 55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt 56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort 57 ldr pc, _prefetch_abort
58 ldr pc, _data_abort 58 ldr pc, _data_abort
59 ldr pc, _not_used 59 ldr pc, _not_used
60 ldr pc, _irq 60 ldr pc, _irq
61 ldr pc, _fiq 61 ldr pc, _fiq
62 62
63 _undefined_instruction: .word undefined_instruction 63 _undefined_instruction: .word undefined_instruction
64 _software_interrupt: .word software_interrupt 64 _software_interrupt: .word software_interrupt
65 _prefetch_abort: .word prefetch_abort 65 _prefetch_abort: .word prefetch_abort
66 _data_abort: .word data_abort 66 _data_abort: .word data_abort
67 _not_used: .word not_used 67 _not_used: .word not_used
68 _irq: .word irq 68 _irq: .word irq
69 _fiq: .word fiq 69 _fiq: .word fiq
70 _pad: .word 0x12345678 /* now 16*4=64 */ 70 _pad: .word 0x12345678 /* now 16*4=64 */
71 #endif /* CONFIG_SPL_BUILD */ 71 #endif /* CONFIG_SPL_BUILD */
72 .global _end_vect 72 .global _end_vect
73 _end_vect: 73 _end_vect:
74 74
75 .balignl 16,0xdeadbeef 75 .balignl 16,0xdeadbeef
76 /* 76 /*
77 ************************************************************************* 77 *************************************************************************
78 * 78 *
79 * Startup Code (reset vector) 79 * Startup Code (reset vector)
80 * 80 *
81 * do important init only if we don't start from memory! 81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation. 82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram 83 * relocate armboot to ram
84 * setup stack 84 * setup stack
85 * 85 *
86 ************************************************************************* 86 *************************************************************************
87 */ 87 */
88 88
89 .globl _TEXT_BASE 89 .globl _TEXT_BASE
90 _TEXT_BASE: 90 _TEXT_BASE:
91 .word CONFIG_SYS_TEXT_BASE 91 .word CONFIG_SYS_TEXT_BASE
92 92
93 /* 93 /*
94 * These are defined in the board-specific linker script. 94 * These are defined in the board-specific linker script.
95 * Subtracting _start from them lets the linker put their 95 * Subtracting _start from them lets the linker put their
96 * relative position in the executable instead of leaving 96 * relative position in the executable instead of leaving
97 * them null. 97 * them null.
98 */ 98 */
99 .globl _bss_start_ofs 99 .globl _bss_start_ofs
100 _bss_start_ofs: 100 _bss_start_ofs:
101 .word __bss_start - _start 101 .word __bss_start - _start
102 102
103 .global _image_copy_end_ofs
104 _image_copy_end_ofs:
105 .word __image_copy_end - _start
106
103 .globl _bss_end_ofs 107 .globl _bss_end_ofs
104 _bss_end_ofs: 108 _bss_end_ofs:
105 .word __bss_end__ - _start 109 .word __bss_end__ - _start
106 110
107 .globl _end_ofs 111 .globl _end_ofs
108 _end_ofs: 112 _end_ofs:
109 .word _end - _start 113 .word _end - _start
110 114
111 #ifdef CONFIG_USE_IRQ 115 #ifdef CONFIG_USE_IRQ
112 /* IRQ stack memory (calculated at run-time) */ 116 /* IRQ stack memory (calculated at run-time) */
113 .globl IRQ_STACK_START 117 .globl IRQ_STACK_START
114 IRQ_STACK_START: 118 IRQ_STACK_START:
115 .word 0x0badc0de 119 .word 0x0badc0de
116 120
117 /* IRQ stack memory (calculated at run-time) */ 121 /* IRQ stack memory (calculated at run-time) */
118 .globl FIQ_STACK_START 122 .globl FIQ_STACK_START
119 FIQ_STACK_START: 123 FIQ_STACK_START:
120 .word 0x0badc0de 124 .word 0x0badc0de
121 #endif 125 #endif
122 126
123 /* IRQ stack memory (calculated at run-time) + 8 bytes */ 127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
124 .globl IRQ_STACK_START_IN 128 .globl IRQ_STACK_START_IN
125 IRQ_STACK_START_IN: 129 IRQ_STACK_START_IN:
126 .word 0x0badc0de 130 .word 0x0badc0de
127 131
128 /* 132 /*
129 * the actual reset code 133 * the actual reset code
130 */ 134 */
131 135
132 reset: 136 reset:
133 /* 137 /*
134 * set the cpu to SVC32 mode 138 * set the cpu to SVC32 mode
135 */ 139 */
136 mrs r0,cpsr 140 mrs r0,cpsr
137 bic r0,r0,#0x1f 141 bic r0,r0,#0x1f
138 orr r0,r0,#0xd3 142 orr r0,r0,#0xd3
139 msr cpsr,r0 143 msr cpsr,r0
140 144
141 #ifdef CONFIG_OMAP2420H4 145 #ifdef CONFIG_OMAP2420H4
142 /* Copy vectors to mask ROM indirect addr */ 146 /* Copy vectors to mask ROM indirect addr */
143 adr r0, _start /* r0 <- current position of code */ 147 adr r0, _start /* r0 <- current position of code */
144 add r0, r0, #4 /* skip reset vector */ 148 add r0, r0, #4 /* skip reset vector */
145 mov r2, #64 /* r2 <- size to copy */ 149 mov r2, #64 /* r2 <- size to copy */
146 add r2, r0, r2 /* r2 <- source end address */ 150 add r2, r0, r2 /* r2 <- source end address */
147 mov r1, #SRAM_OFFSET0 /* build vect addr */ 151 mov r1, #SRAM_OFFSET0 /* build vect addr */
148 mov r3, #SRAM_OFFSET1 152 mov r3, #SRAM_OFFSET1
149 add r1, r1, r3 153 add r1, r1, r3
150 mov r3, #SRAM_OFFSET2 154 mov r3, #SRAM_OFFSET2
151 add r1, r1, r3 155 add r1, r1, r3
152 next: 156 next:
153 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 157 ldmia r0!, {r3-r10} /* copy from source address [r0] */
154 stmia r1!, {r3-r10} /* copy to target address [r1] */ 158 stmia r1!, {r3-r10} /* copy to target address [r1] */
155 cmp r0, r2 /* until source end address [r2] */ 159 cmp r0, r2 /* until source end address [r2] */
156 bne next /* loop until equal */ 160 bne next /* loop until equal */
157 bl cpy_clk_code /* put dpll adjust code behind vectors */ 161 bl cpy_clk_code /* put dpll adjust code behind vectors */
158 #endif 162 #endif
159 /* the mask ROM code should have PLL and others stable */ 163 /* the mask ROM code should have PLL and others stable */
160 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 164 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
161 bl cpu_init_crit 165 bl cpu_init_crit
162 #endif 166 #endif
163 167
164 /* Set stackpointer in internal RAM to call board_init_f */ 168 /* Set stackpointer in internal RAM to call board_init_f */
165 call_board_init_f: 169 call_board_init_f:
166 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 170 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
167 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 171 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
168 ldr r0,=0x00000000 172 ldr r0,=0x00000000
169 173
170 bl board_init_f 174 bl board_init_f
171 175
172 /*------------------------------------------------------------------------------*/ 176 /*------------------------------------------------------------------------------*/
173 177
174 /* 178 /*
175 * void relocate_code (addr_sp, gd, addr_moni) 179 * void relocate_code (addr_sp, gd, addr_moni)
176 * 180 *
177 * This "function" does not return, instead it continues in RAM 181 * This "function" does not return, instead it continues in RAM
178 * after relocating the monitor code. 182 * after relocating the monitor code.
179 * 183 *
180 */ 184 */
181 .globl relocate_code 185 .globl relocate_code
182 relocate_code: 186 relocate_code:
183 mov r4, r0 /* save addr_sp */ 187 mov r4, r0 /* save addr_sp */
184 mov r5, r1 /* save addr of gd */ 188 mov r5, r1 /* save addr of gd */
185 mov r6, r2 /* save addr of destination */ 189 mov r6, r2 /* save addr of destination */
186 190
187 /* Set up the stack */ 191 /* Set up the stack */
188 stack_setup: 192 stack_setup:
189 mov sp, r4 193 mov sp, r4
190 194
191 adr r0, _start 195 adr r0, _start
192 cmp r0, r6 196 cmp r0, r6
193 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 197 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
194 beq clear_bss /* skip relocation */ 198 beq clear_bss /* skip relocation */
195 mov r1, r6 /* r1 <- scratch for copy_loop */ 199 mov r1, r6 /* r1 <- scratch for copy_loop */
196 ldr r3, _bss_start_ofs 200 ldr r3, _image_copy_end_ofs
197 add r2, r0, r3 /* r2 <- source end address */ 201 add r2, r0, r3 /* r2 <- source end address */
198 202
199 copy_loop: 203 copy_loop:
200 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 204 ldmia r0!, {r9-r10} /* copy from source address [r0] */
201 stmia r1!, {r9-r10} /* copy to target address [r1] */ 205 stmia r1!, {r9-r10} /* copy to target address [r1] */
202 cmp r0, r2 /* until source end address [r2] */ 206 cmp r0, r2 /* until source end address [r2] */
203 blo copy_loop 207 blo copy_loop
204 208
205 #ifndef CONFIG_SPL_BUILD 209 #ifndef CONFIG_SPL_BUILD
206 /* 210 /*
207 * fix .rel.dyn relocations 211 * fix .rel.dyn relocations
208 */ 212 */
209 ldr r0, _TEXT_BASE /* r0 <- Text base */ 213 ldr r0, _TEXT_BASE /* r0 <- Text base */
210 sub r9, r6, r0 /* r9 <- relocation offset */ 214 sub r9, r6, r0 /* r9 <- relocation offset */
211 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 215 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
212 add r10, r10, r0 /* r10 <- sym table in FLASH */ 216 add r10, r10, r0 /* r10 <- sym table in FLASH */
213 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 217 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
214 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 218 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
215 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 219 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
216 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 220 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
217 fixloop: 221 fixloop:
218 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 222 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
219 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 223 add r0, r0, r9 /* r0 <- location to fix up in RAM */
220 ldr r1, [r2, #4] 224 ldr r1, [r2, #4]
221 and r7, r1, #0xff 225 and r7, r1, #0xff
222 cmp r7, #23 /* relative fixup? */ 226 cmp r7, #23 /* relative fixup? */
223 beq fixrel 227 beq fixrel
224 cmp r7, #2 /* absolute fixup? */ 228 cmp r7, #2 /* absolute fixup? */
225 beq fixabs 229 beq fixabs
226 /* ignore unknown type of fixup */ 230 /* ignore unknown type of fixup */
227 b fixnext 231 b fixnext
228 fixabs: 232 fixabs:
229 /* absolute fix: set location to (offset) symbol value */ 233 /* absolute fix: set location to (offset) symbol value */
230 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 234 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
231 add r1, r10, r1 /* r1 <- address of symbol in table */ 235 add r1, r10, r1 /* r1 <- address of symbol in table */
232 ldr r1, [r1, #4] /* r1 <- symbol value */ 236 ldr r1, [r1, #4] /* r1 <- symbol value */
233 add r1, r1, r9 /* r1 <- relocated sym addr */ 237 add r1, r1, r9 /* r1 <- relocated sym addr */
234 b fixnext 238 b fixnext
235 fixrel: 239 fixrel:
236 /* relative fix: increase location by offset */ 240 /* relative fix: increase location by offset */
237 ldr r1, [r0] 241 ldr r1, [r0]
238 add r1, r1, r9 242 add r1, r1, r9
239 fixnext: 243 fixnext:
240 str r1, [r0] 244 str r1, [r0]
241 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 245 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
242 cmp r2, r3 246 cmp r2, r3
243 blo fixloop 247 blo fixloop
248 b clear_bss
249
250 _rel_dyn_start_ofs:
251 .word __rel_dyn_start - _start
252 _rel_dyn_end_ofs:
253 .word __rel_dyn_end - _start
254 _dynsym_start_ofs:
255 .word __dynsym_start - _start
244 #endif 256 #endif
245 257
246 clear_bss: 258 clear_bss:
247 #ifndef CONFIG_SPL_BUILD 259 #ifdef CONFIG_SPL_BUILD
260 /* No relocation for SPL */
261 ldr r0, =__bss_start
262 ldr r1, =__bss_end__
263 #else
248 ldr r0, _bss_start_ofs 264 ldr r0, _bss_start_ofs
249 ldr r1, _bss_end_ofs 265 ldr r1, _bss_end_ofs
250 mov r4, r6 /* reloc addr */ 266 mov r4, r6 /* reloc addr */
251 add r0, r0, r4 267 add r0, r0, r4
252 add r1, r1, r4 268 add r1, r1, r4
269 #endif
253 mov r2, #0x00000000 /* clear */ 270 mov r2, #0x00000000 /* clear */
254 271
255 clbss_l:cmp r0, r1 /* clear loop... */ 272 clbss_l:cmp r0, r1 /* clear loop... */
256 bhs clbss_e /* if reached end of bss, exit */ 273 bhs clbss_e /* if reached end of bss, exit */
257 str r2, [r0] 274 str r2, [r0]
258 add r0, r0, #4 275 add r0, r0, #4
259 b clbss_l 276 b clbss_l
260 clbss_e: 277 clbss_e:
261 #endif /* #ifndef CONFIG_SPL_BUILD */
262 278
263 /* 279 /*
264 * We are done. Do not return, instead branch to second part of board 280 * We are done. Do not return, instead branch to second part of board
265 * initialization, now running from RAM. 281 * initialization, now running from RAM.
266 */ 282 */
267 #ifdef CONFIG_NAND_SPL 283 #ifdef CONFIG_NAND_SPL
268 ldr r0, _nand_boot_ofs 284 ldr r0, _nand_boot_ofs
269 mov pc, r0 285 mov pc, r0
270 286
271 _nand_boot_ofs: 287 _nand_boot_ofs:
272 .word nand_boot 288 .word nand_boot
273 #else 289 #else
274 jump_2_ram: 290 jump_2_ram:
275 ldr r0, _board_init_r_ofs 291 ldr r0, _board_init_r_ofs
276 ldr r1, _TEXT_BASE 292 adr r1, _start
277 add lr, r0, r1 293 add lr, r0, r1
278 add lr, lr, r9 294 add lr, lr, r9
279 /* setup parameters for board_init_r */ 295 /* setup parameters for board_init_r */
280 mov r0, r5 /* gd_t */ 296 mov r0, r5 /* gd_t */
281 mov r1, r6 /* dest_addr */ 297 mov r1, r6 /* dest_addr */
282 /* jump to it ... */ 298 /* jump to it ... */
283 mov pc, lr 299 mov pc, lr
284 300
285 _board_init_r_ofs: 301 _board_init_r_ofs:
286 .word board_init_r - _start 302 .word board_init_r - _start
287 #endif 303 #endif
288
289 _rel_dyn_start_ofs:
290 .word __rel_dyn_start - _start
291 _rel_dyn_end_ofs:
292 .word __rel_dyn_end - _start
293 _dynsym_start_ofs:
294 .word __dynsym_start - _start
295 304
296 /* 305 /*
297 ************************************************************************* 306 *************************************************************************
298 * 307 *
299 * CPU_init_critical registers 308 * CPU_init_critical registers
300 * 309 *
301 * setup important registers 310 * setup important registers
302 * setup memory timing 311 * setup memory timing
303 * 312 *
304 ************************************************************************* 313 *************************************************************************
305 */ 314 */
306 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 315 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
307 cpu_init_crit: 316 cpu_init_crit:
308 /* 317 /*
309 * flush v4 I/D caches 318 * flush v4 I/D caches
310 */ 319 */
311 mov r0, #0 320 mov r0, #0
312 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 321 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
313 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 322 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
314 323
315 /* 324 /*
316 * disable MMU stuff and caches 325 * disable MMU stuff and caches
317 */ 326 */
318 mrc p15, 0, r0, c1, c0, 0 327 mrc p15, 0, r0, c1, c0, 0
319 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 328 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
320 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 329 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
321 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 330 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
322 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 331 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
323 mcr p15, 0, r0, c1, c0, 0 332 mcr p15, 0, r0, c1, c0, 0
324 333
325 /* 334 /*
326 * Jump to board specific initialization... The Mask ROM will have already initialized 335 * Jump to board specific initialization... The Mask ROM will have already initialized
327 * basic memory. Go here to bump up clock rate and handle wake up conditions. 336 * basic memory. Go here to bump up clock rate and handle wake up conditions.
328 */ 337 */
329 mov ip, lr /* persevere link reg across call */ 338 mov ip, lr /* persevere link reg across call */
330 bl lowlevel_init /* go setup pll,mux,memory */ 339 bl lowlevel_init /* go setup pll,mux,memory */
331 mov lr, ip /* restore link */ 340 mov lr, ip /* restore link */
332 mov pc, lr /* back to my caller */ 341 mov pc, lr /* back to my caller */
333 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 342 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
334 343
335 #ifndef CONFIG_SPL_BUILD 344 #ifndef CONFIG_SPL_BUILD
336 /* 345 /*
337 ************************************************************************* 346 *************************************************************************
338 * 347 *
339 * Interrupt handling 348 * Interrupt handling
340 * 349 *
341 ************************************************************************* 350 *************************************************************************
342 */ 351 */
343 @ 352 @
344 @ IRQ stack frame. 353 @ IRQ stack frame.
345 @ 354 @
346 #define S_FRAME_SIZE 72 355 #define S_FRAME_SIZE 72
347 356
348 #define S_OLD_R0 68 357 #define S_OLD_R0 68
349 #define S_PSR 64 358 #define S_PSR 64
350 #define S_PC 60 359 #define S_PC 60
351 #define S_LR 56 360 #define S_LR 56
352 #define S_SP 52 361 #define S_SP 52
353 362
354 #define S_IP 48 363 #define S_IP 48
355 #define S_FP 44 364 #define S_FP 44
356 #define S_R10 40 365 #define S_R10 40
357 #define S_R9 36 366 #define S_R9 36
358 #define S_R8 32 367 #define S_R8 32
359 #define S_R7 28 368 #define S_R7 28
360 #define S_R6 24 369 #define S_R6 24
361 #define S_R5 20 370 #define S_R5 20
362 #define S_R4 16 371 #define S_R4 16
363 #define S_R3 12 372 #define S_R3 12
364 #define S_R2 8 373 #define S_R2 8
365 #define S_R1 4 374 #define S_R1 4
366 #define S_R0 0 375 #define S_R0 0
367 376
368 #define MODE_SVC 0x13 377 #define MODE_SVC 0x13
369 #define I_BIT 0x80 378 #define I_BIT 0x80
370 379
371 /* 380 /*
372 * use bad_save_user_regs for abort/prefetch/undef/swi ... 381 * use bad_save_user_regs for abort/prefetch/undef/swi ...
373 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 382 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
374 */ 383 */
375 384
376 .macro bad_save_user_regs 385 .macro bad_save_user_regs
377 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 386 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
378 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 387 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
379 388
380 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 389 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
381 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 390 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
382 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 391 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
383 392
384 add r5, sp, #S_SP 393 add r5, sp, #S_SP
385 mov r1, lr 394 mov r1, lr
386 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 395 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
387 mov r0, sp @ save current stack into r0 (param register) 396 mov r0, sp @ save current stack into r0 (param register)
388 .endm 397 .endm
389 398
390 .macro irq_save_user_regs 399 .macro irq_save_user_regs
391 sub sp, sp, #S_FRAME_SIZE 400 sub sp, sp, #S_FRAME_SIZE
392 stmia sp, {r0 - r12} @ Calling r0-r12 401 stmia sp, {r0 - r12} @ Calling r0-r12
393 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 402 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
394 stmdb r8, {sp, lr}^ @ Calling SP, LR 403 stmdb r8, {sp, lr}^ @ Calling SP, LR
395 str lr, [r8, #0] @ Save calling PC 404 str lr, [r8, #0] @ Save calling PC
396 mrs r6, spsr 405 mrs r6, spsr
397 str r6, [r8, #4] @ Save CPSR 406 str r6, [r8, #4] @ Save CPSR
398 str r0, [r8, #8] @ Save OLD_R0 407 str r0, [r8, #8] @ Save OLD_R0
399 mov r0, sp 408 mov r0, sp
400 .endm 409 .endm
401 410
402 .macro irq_restore_user_regs 411 .macro irq_restore_user_regs
403 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 412 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
404 mov r0, r0 413 mov r0, r0
405 ldr lr, [sp, #S_PC] @ Get PC 414 ldr lr, [sp, #S_PC] @ Get PC
406 add sp, sp, #S_FRAME_SIZE 415 add sp, sp, #S_FRAME_SIZE
407 subs pc, lr, #4 @ return & move spsr_svc into cpsr 416 subs pc, lr, #4 @ return & move spsr_svc into cpsr
408 .endm 417 .endm
409 418
410 .macro get_bad_stack 419 .macro get_bad_stack
411 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 420 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
412 421
413 str lr, [r13] @ save caller lr in position 0 of saved stack 422 str lr, [r13] @ save caller lr in position 0 of saved stack
414 mrs lr, spsr @ get the spsr 423 mrs lr, spsr @ get the spsr
415 str lr, [r13, #4] @ save spsr in position 1 of saved stack 424 str lr, [r13, #4] @ save spsr in position 1 of saved stack
416 425
417 mov r13, #MODE_SVC @ prepare SVC-Mode 426 mov r13, #MODE_SVC @ prepare SVC-Mode
418 @ msr spsr_c, r13 427 @ msr spsr_c, r13
419 msr spsr, r13 @ switch modes, make sure moves will execute 428 msr spsr, r13 @ switch modes, make sure moves will execute
420 mov lr, pc @ capture return pc 429 mov lr, pc @ capture return pc
421 movs pc, lr @ jump to next instruction & switch modes. 430 movs pc, lr @ jump to next instruction & switch modes.
422 .endm 431 .endm
423 432
424 .macro get_bad_stack_swi 433 .macro get_bad_stack_swi
425 sub r13, r13, #4 @ space on current stack for scratch reg. 434 sub r13, r13, #4 @ space on current stack for scratch reg.
426 str r0, [r13] @ save R0's value. 435 str r0, [r13] @ save R0's value.
427 ldr r0, IRQ_STACK_START_IN @ get data regions start 436 ldr r0, IRQ_STACK_START_IN @ get data regions start
428 str lr, [r0] @ save caller lr in position 0 of saved stack 437 str lr, [r0] @ save caller lr in position 0 of saved stack
429 mrs r0, spsr @ get the spsr 438 mrs r0, spsr @ get the spsr
430 str lr, [r0, #4] @ save spsr in position 1 of saved stack 439 str lr, [r0, #4] @ save spsr in position 1 of saved stack
431 ldr r0, [r13] @ restore r0 440 ldr r0, [r13] @ restore r0
432 add r13, r13, #4 @ pop stack entry 441 add r13, r13, #4 @ pop stack entry
433 .endm 442 .endm
434 443
435 .macro get_irq_stack @ setup IRQ stack 444 .macro get_irq_stack @ setup IRQ stack
436 ldr sp, IRQ_STACK_START 445 ldr sp, IRQ_STACK_START
437 .endm 446 .endm
438 447
439 .macro get_fiq_stack @ setup FIQ stack 448 .macro get_fiq_stack @ setup FIQ stack
440 ldr sp, FIQ_STACK_START 449 ldr sp, FIQ_STACK_START
441 .endm 450 .endm
442 #endif /* CONFIG_SPL_BUILD */ 451 #endif /* CONFIG_SPL_BUILD */
443 452
444 /* 453 /*
445 * exception handlers 454 * exception handlers
446 */ 455 */
447 #ifdef CONFIG_SPL_BUILD 456 #ifdef CONFIG_SPL_BUILD
448 .align 5 457 .align 5
449 do_hang: 458 do_hang:
450 ldr sp, _TEXT_BASE /* use 32 words about stack */ 459 ldr sp, _TEXT_BASE /* use 32 words about stack */
451 bl hang /* hang and never return */ 460 bl hang /* hang and never return */
452 #else /* !CONFIG_SPL_BUILD */ 461 #else /* !CONFIG_SPL_BUILD */
453 .align 5 462 .align 5
454 undefined_instruction: 463 undefined_instruction:
455 get_bad_stack 464 get_bad_stack
456 bad_save_user_regs 465 bad_save_user_regs
457 bl do_undefined_instruction 466 bl do_undefined_instruction
458 467
459 .align 5 468 .align 5
460 software_interrupt: 469 software_interrupt:
461 get_bad_stack_swi 470 get_bad_stack_swi
462 bad_save_user_regs 471 bad_save_user_regs
463 bl do_software_interrupt 472 bl do_software_interrupt
464 473
465 .align 5 474 .align 5
466 prefetch_abort: 475 prefetch_abort:
467 get_bad_stack 476 get_bad_stack
468 bad_save_user_regs 477 bad_save_user_regs
469 bl do_prefetch_abort 478 bl do_prefetch_abort
470 479
471 .align 5 480 .align 5
472 data_abort: 481 data_abort:
473 get_bad_stack 482 get_bad_stack
474 bad_save_user_regs 483 bad_save_user_regs
475 bl do_data_abort 484 bl do_data_abort
476 485
477 .align 5 486 .align 5
478 not_used: 487 not_used:
479 get_bad_stack 488 get_bad_stack
480 bad_save_user_regs 489 bad_save_user_regs
481 bl do_not_used 490 bl do_not_used
482 491
483 #ifdef CONFIG_USE_IRQ 492 #ifdef CONFIG_USE_IRQ
484 493
485 .align 5 494 .align 5
486 irq: 495 irq:
487 get_irq_stack 496 get_irq_stack
488 irq_save_user_regs 497 irq_save_user_regs
489 bl do_irq 498 bl do_irq
490 irq_restore_user_regs 499 irq_restore_user_regs
491 500
492 .align 5 501 .align 5
493 fiq: 502 fiq:
494 get_fiq_stack 503 get_fiq_stack
495 /* someone ought to write a more effiction fiq_save_user_regs */ 504 /* someone ought to write a more effiction fiq_save_user_regs */
496 irq_save_user_regs 505 irq_save_user_regs
497 bl do_fiq 506 bl do_fiq
498 irq_restore_user_regs 507 irq_restore_user_regs
499 508
500 #else 509 #else
501 510
502 .align 5 511 .align 5
503 irq: 512 irq:
504 get_bad_stack 513 get_bad_stack
505 bad_save_user_regs 514 bad_save_user_regs
506 bl do_irq 515 bl do_irq
507 516
508 .align 5 517 .align 5
509 fiq: 518 fiq:
510 get_bad_stack 519 get_bad_stack
511 bad_save_user_regs 520 bad_save_user_regs
512 bl do_fiq 521 bl do_fiq
513 522
514 #endif 523 #endif
515 .align 5 524 .align 5
516 .global arm1136_cache_flush 525 .global arm1136_cache_flush
517 arm1136_cache_flush: 526 arm1136_cache_flush:
518 #if !defined(CONFIG_SYS_ICACHE_OFF) 527 #if !defined(CONFIG_SYS_ICACHE_OFF)
board/freescale/mx31ads/u-boot.lds
Diff comments   View file @ b736e4b
1 /* 1 /*
2 * January 2004 - Changed to support H4 device 2 * January 2004 - Changed to support H4 device
3 * Copyright (c) 2004 Texas Instruments 3 * Copyright (c) 2004 Texas Instruments
4 * 4 *
5 * (C) Copyright 2002 5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
7 * 7 *
8 * See file CREDITS for list of people who contributed to this 8 * See file CREDITS for list of people who contributed to this
9 * project. 9 * project.
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of 13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version. 14 * the License, or (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software 22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA 24 * MA 02111-1307 USA
25 */ 25 */
26 26
27 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 27 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
28 OUTPUT_ARCH(arm) 28 OUTPUT_ARCH(arm)
29 ENTRY(_start) 29 ENTRY(_start)
30 SECTIONS 30 SECTIONS
31 { 31 {
32 . = 0x00000000; 32 . = 0x00000000;
33 33
34 . = ALIGN(4); 34 . = ALIGN(4);
35 .text : 35 .text :
36 { 36 {
37 /* WARNING - the following is hand-optimized to fit within */ 37 /* WARNING - the following is hand-optimized to fit within */
38 /* the sector layout of our flash chips! XXX FIXME XXX */ 38 /* the sector layout of our flash chips! XXX FIXME XXX */
39 39
40 arch/arm/cpu/arm1136/start.o (.text) 40 arch/arm/cpu/arm1136/start.o (.text)
41 board/freescale/mx31ads/libmx31ads.o (.text) 41 board/freescale/mx31ads/libmx31ads.o (.text)
42 arch/arm/lib/libarm.o (.text) 42 arch/arm/lib/libarm.o (.text)
43 net/libnet.o (.text) 43 net/libnet.o (.text)
44 drivers/mtd/libmtd.o (.text) 44 drivers/mtd/libmtd.o (.text)
45 45
46 . = DEFINED(env_offset) ? env_offset : .; 46 . = DEFINED(env_offset) ? env_offset : .;
47 common/env_embedded.o(.text) 47 common/env_embedded.o(.text)
48 48
49 *(.text) 49 *(.text)
50 } 50 }
51 . = ALIGN(4); 51 . = ALIGN(4);
52 .rodata : { *(.rodata) } 52 .rodata : { *(.rodata) }
53 53
54 . = ALIGN(4); 54 . = ALIGN(4);
55 .data : { 55 .data : {
56 *(.data) 56 *(.data)
57 } 57 }
58 58
59 . = ALIGN(4); 59 . = ALIGN(4);
60 __u_boot_cmd_start = .; 60 __u_boot_cmd_start = .;
61 .u_boot_cmd : { *(.u_boot_cmd) } 61 .u_boot_cmd : { *(.u_boot_cmd) }
62 __u_boot_cmd_end = .; 62 __u_boot_cmd_end = .;
63 63
64 . = ALIGN(4); 64 . = ALIGN(4);
65 65
66 __image_copy_end = .;
67
66 .rel.dyn : { 68 .rel.dyn : {
67 __rel_dyn_start = .; 69 __rel_dyn_start = .;
68 *(.rel*) 70 *(.rel*)
69 __rel_dyn_end = .; 71 __rel_dyn_end = .;
70 } 72 }
71 73
72 .dynsym : { 74 .dynsym : {
73 __dynsym_start = .; 75 __dynsym_start = .;
74 *(.dynsym) 76 *(.dynsym)
75 } 77 }
76 78
77 _end = .; 79 _end = .;
78 80
79 .bss __rel_dyn_start (OVERLAY) : { 81 .bss __rel_dyn_start (OVERLAY) : {
80 __bss_start = .; 82 __bss_start = .;
81 *(.bss) 83 *(.bss)
82 . = ALIGN(4); 84 . = ALIGN(4);
83 __bss_end__ = .; 85 __bss_end__ = .;
84 } 86 }
85 87
86 /DISCARD/ : { *(.bss*) } 88 /DISCARD/ : { *(.bss*) }
87 /DISCARD/ : { *(.dynstr*) } 89 /DISCARD/ : { *(.dynstr*) }
88 /DISCARD/ : { *(.dynsym*) } 90 /DISCARD/ : { *(.dynsym*) }
89 /DISCARD/ : { *(.dynamic*) } 91 /DISCARD/ : { *(.dynamic*) }
90 /DISCARD/ : { *(.hash*) } 92 /DISCARD/ : { *(.hash*) }
91 /DISCARD/ : { *(.plt*) } 93 /DISCARD/ : { *(.plt*) }
92 /DISCARD/ : { *(.interp*) } 94 /DISCARD/ : { *(.interp*) }
93 /DISCARD/ : { *(.gnu*) } 95 /DISCARD/ : { *(.gnu*) }
94 } 96 }
95 97
nand_spl/board/freescale/mx31pdk/u-boot.lds
Diff comments   View file @ b736e4b
1 /* 1 /*
2 * (C) Copyright 2009 2 * (C) Copyright 2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 23 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
24 OUTPUT_ARCH(arm) 24 OUTPUT_ARCH(arm)
25 ENTRY(_start) 25 ENTRY(_start)
26 SECTIONS 26 SECTIONS
27 { 27 {
28 . = 0x00000000; 28 . = 0x00000000;
29 29
30 . = ALIGN(4); 30 . = ALIGN(4);
31 .text : 31 .text :
32 { 32 {
33 start.o (.text) 33 start.o (.text)
34 lowlevel_init.o (.text) 34 lowlevel_init.o (.text)
35 nand_boot_fsl_nfc.o (.text) 35 nand_boot_fsl_nfc.o (.text)
36 *(.text) 36 *(.text)
37 . = 2K; 37 . = 2K;
38 } 38 }
39 39
40 . = ALIGN(4); 40 . = ALIGN(4);
41 .rodata : { *(.rodata) } 41 .rodata : { *(.rodata) }
42 42
43 . = ALIGN(4); 43 . = ALIGN(4);
44 .data : { 44 .data : {
45 *(.data) 45 *(.data)
46 } 46 }
47 47
48 . = ALIGN(4); 48 . = ALIGN(4);
49 __u_boot_cmd_start = .; 49 __u_boot_cmd_start = .;
50 .u_boot_cmd : { *(.u_boot_cmd) } 50 .u_boot_cmd : { *(.u_boot_cmd) }
51 __u_boot_cmd_end = .; 51 __u_boot_cmd_end = .;
52 52
53 . = ALIGN(4); 53 . = ALIGN(4);
54 54
55 __image_copy_end = .;
56
55 .rel.dyn : { 57 .rel.dyn : {
56 __rel_dyn_start = .; 58 __rel_dyn_start = .;
57 *(.rel*) 59 *(.rel*)
58 __rel_dyn_end = .; 60 __rel_dyn_end = .;
59 } 61 }
60 62
61 .dynsym : { 63 .dynsym : {
62 __dynsym_start = .; 64 __dynsym_start = .;
63 *(.dynsym) 65 *(.dynsym)
64 } 66 }
65 67
66 _end = .; 68 _end = .;
67 69
68 .bss __rel_dyn_start (OVERLAY) : { 70 .bss __rel_dyn_start (OVERLAY) : {
69 __bss_start = .; 71 __bss_start = .;
70 *(.bss) 72 *(.bss)
71 . = ALIGN(4); 73 . = ALIGN(4);
72 __bss_end__ = .; 74 __bss_end__ = .;
73 } 75 }
74 76
75 /DISCARD/ : { *(.bss*) } 77 /DISCARD/ : { *(.bss*) }
76 /DISCARD/ : { *(.dynstr*) } 78 /DISCARD/ : { *(.dynstr*) }
77 /DISCARD/ : { *(.dynsym*) } 79 /DISCARD/ : { *(.dynsym*) }
78 /DISCARD/ : { *(.dynamic*) } 80 /DISCARD/ : { *(.dynamic*) }
79 /DISCARD/ : { *(.hash*) } 81 /DISCARD/ : { *(.hash*) }
80 /DISCARD/ : { *(.plt*) } 82 /DISCARD/ : { *(.plt*) }
81 /DISCARD/ : { *(.interp*) } 83 /DISCARD/ : { *(.interp*) }
82 /DISCARD/ : { *(.gnu*) } 84 /DISCARD/ : { *(.gnu*) }
83 } 85 }
84 86