MLK-13929-6 mx7ulp_evk: Enable the MIPI DSI splashscreen

Enable and setup board level codes for MIPI DSI splashscreen on EVK board. User needs set env variable"panel=HX8363_WVGA" for displaying. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 49cb68f5c17e42f9290336e1252ace6ac7d0b5ce) (cherry picked from commit be3d3d5c140a1617c1ce35e8657f2d45bc8c70eb)

MLK-13929-6 mx7ulp_evk: Enable the MIPI DSI splashscreen
Enable and setup board level codes for MIPI DSI splashscreen on EVK board. User needs set env variable"panel=HX8363_WVGA" for displaying. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 49cb68f5c17e42f9290336e1252ace6ac7d0b5ce) (cherry picked from commit be3d3d5c140a1617c1ce35e8657f2d45bc8c70eb)
Ye Li · Eric Lee · Eric Lee
1 parent 60d57156df
Showing 5 changed files with 90 additions and 1 deletions Side-by-side Diff
arch/arm/mach-imx/Makefile
board/freescale/mx7ulp_evk/mx7ulp_evk.c
configs/mx7ulp_evk_defconfig
configs/mx7ulp_evk_plugin_defconfig
include/configs/mx7ulp_evk.h
@@ -24,7 +24,7 @@
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp mx8m))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -47,6 +47,7 @@
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7ulp))
 obj-y  += cache.o
+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_SECURE_BOOT) += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
@@ -12,6 +12,7 @@
 #include <asm/gpio.h>
 #include <usb.h>
 #include <dm.h>
+#include <asm/mach-imx/video.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -19,6 +20,8 @@
 #define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
 #define OTG_ID_GPIO_PAD_CTRL	(PAD_CTL_IBE_ENABLE)
  
+#define MIPI_GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE)
+
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_SIZE;
@@ -104,6 +107,73 @@
  
 	return 0;
 }
+
+#ifdef CONFIG_VIDEO_MXS
+
+#define MIPI_RESET_GPIO	IMX_GPIO_NR(3, 19)
+#define LED_PWM_EN_GPIO	IMX_GPIO_NR(6, 2)
+
+static iomux_cfg_t const mipi_reset_pad[] = {
+	MX7ULP_PAD_PTC19__PTC19 | MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL),
+};
+
+static iomux_cfg_t const led_pwm_en_pad[] = {
+	MX7ULP_PAD_PTF2__PTF2 | MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL),
+};
+
+int board_mipi_panel_reset(void)
+{
+	gpio_direction_output(MIPI_RESET_GPIO, 0);
+	udelay(1000);
+	gpio_direction_output(MIPI_RESET_GPIO, 1);
+	return 0;
+}
+
+int board_mipi_panel_shutdown(void)
+{
+	gpio_direction_output(MIPI_RESET_GPIO, 0);
+	gpio_direction_output(LED_PWM_EN_GPIO, 0);
+	return 0;
+}
+
+void setup_mipi_reset(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(mipi_reset_pad, ARRAY_SIZE(mipi_reset_pad));
+	gpio_request(MIPI_RESET_GPIO, "mipi_panel_reset");
+}
+
+void do_enable_mipi_dsi(struct display_info_t const *dev)
+{
+	setup_mipi_reset();
+
+	/* Enable backlight */
+	mx7ulp_iomux_setup_multiple_pads(led_pwm_en_pad, ARRAY_SIZE(mipi_reset_pad));
+	gpio_request(LED_PWM_EN_GPIO, "led_pwm_en");
+	gpio_direction_output(LED_PWM_EN_GPIO, 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = LCDIF_RBASE,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_mipi_dsi,
+	.mode	= {
+		.name			= "HX8363_WVGA",
+		.xres           = 480,
+		.yres           = 854,
+		.pixclock       = 41042,
+		.left_margin    = 40,
+		.right_margin   = 60,
+		.upper_margin   = 3,
+		.lower_margin   = 3,
+		.hsync_len      = 8,
+		.vsync_len      = 4,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
  
 int board_init(void)
 {
@@ -42,4 +42,5 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_RTL8152=y
+CONFIG_VIDEO=y
@@ -42,4 +42,5 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_RTL8152=y
+CONFIG_VIDEO=y
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Configuration settings for the Freescale i.MX7ULP EVK board.
  *
@@ -194,6 +195,21 @@
  
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_MXC_MIPI_DSI_NORTHWEST
+#define CONFIG_HX8363
+#endif
  
 #define CONFIG_OF_SYSTEM_SETUP
...	...	@@ -24,7 +24,7 @@
24	24	obj-$(CONFIG_GPT_TIMER) += timer.o
25	25	obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
26	26	endif
27		-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
	27	+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp mx8m))
28	28	obj-y += misc.o
29	29	obj-$(CONFIG_SPL_BUILD) += spl.o
30	30	endif
...	...	@@ -47,6 +47,7 @@
47	47	endif
48	48	ifeq ($(SOC),$(filter $(SOC),mx7ulp))
49	49	obj-y += cache.o
	50	+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
50	51	obj-$(CONFIG_SECURE_BOOT) += hab.o
51	52	endif
52	53	ifeq ($(SOC),$(filter $(SOC),vf610))
...	...	@@ -12,6 +12,7 @@
12	12	#include <asm/gpio.h>
13	13	#include <usb.h>
14	14	#include <dm.h>
	15	+#include <asm/mach-imx/video.h>
15	16
16	17	DECLARE_GLOBAL_DATA_PTR;
17	18
...	...	@@ -19,6 +20,8 @@
19	20	#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP \| PAD_CTL_DSE)
20	21	#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE)
21	22
	23	+#define MIPI_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE)
	24	+
22	25	int dram_init(void)
23	26	{
24	27	gd->ram_size = PHYS_SDRAM_SIZE;
...	...	@@ -104,6 +107,73 @@
104	107
105	108	return 0;
106	109	}
	110	+
	111	+#ifdef CONFIG_VIDEO_MXS
	112	+
	113	+#define MIPI_RESET_GPIO IMX_GPIO_NR(3, 19)
	114	+#define LED_PWM_EN_GPIO IMX_GPIO_NR(6, 2)
	115	+
	116	+static iomux_cfg_t const mipi_reset_pad[] = {
	117	+ MX7ULP_PAD_PTC19__PTC19 \| MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL),
	118	+};
	119	+
	120	+static iomux_cfg_t const led_pwm_en_pad[] = {
	121	+ MX7ULP_PAD_PTF2__PTF2 \| MUX_PAD_CTRL(MIPI_GPIO_PAD_CTRL),
	122	+};
	123	+
	124	+int board_mipi_panel_reset(void)
	125	+{
	126	+ gpio_direction_output(MIPI_RESET_GPIO, 0);
	127	+ udelay(1000);
	128	+ gpio_direction_output(MIPI_RESET_GPIO, 1);
	129	+ return 0;
	130	+}
	131	+
	132	+int board_mipi_panel_shutdown(void)
	133	+{
	134	+ gpio_direction_output(MIPI_RESET_GPIO, 0);
	135	+ gpio_direction_output(LED_PWM_EN_GPIO, 0);
	136	+ return 0;
	137	+}
	138	+
	139	+void setup_mipi_reset(void)
	140	+{
	141	+ mx7ulp_iomux_setup_multiple_pads(mipi_reset_pad, ARRAY_SIZE(mipi_reset_pad));
	142	+ gpio_request(MIPI_RESET_GPIO, "mipi_panel_reset");
	143	+}
	144	+
	145	+void do_enable_mipi_dsi(struct display_info_t const *dev)
	146	+{
	147	+ setup_mipi_reset();
	148	+
	149	+ /* Enable backlight */
	150	+ mx7ulp_iomux_setup_multiple_pads(led_pwm_en_pad, ARRAY_SIZE(mipi_reset_pad));
	151	+ gpio_request(LED_PWM_EN_GPIO, "led_pwm_en");
	152	+ gpio_direction_output(LED_PWM_EN_GPIO, 1);
	153	+}
	154	+
	155	+struct display_info_t const displays[] = {{
	156	+ .bus = LCDIF_RBASE,
	157	+ .addr = 0,
	158	+ .pixfmt = 24,
	159	+ .detect = NULL,
	160	+ .enable = do_enable_mipi_dsi,
	161	+ .mode = {
	162	+ .name = "HX8363_WVGA",
	163	+ .xres = 480,
	164	+ .yres = 854,
	165	+ .pixclock = 41042,
	166	+ .left_margin = 40,
	167	+ .right_margin = 60,
	168	+ .upper_margin = 3,
	169	+ .lower_margin = 3,
	170	+ .hsync_len = 8,
	171	+ .vsync_len = 4,
	172	+ .sync = 0,
	173	+ .vmode = FB_VMODE_NONINTERLACED
	174	+} } };
	175	+size_t display_count = ARRAY_SIZE(displays);
	176	+#endif
107	177
108	178	int board_init(void)
109	179	{
...	...	@@ -42,4 +42,5 @@
42	42	CONFIG_USB_HOST_ETHER=y
43	43	CONFIG_USB_ETHER_ASIX=y
44	44	CONFIG_USB_ETHER_RTL8152=y
	45	+CONFIG_VIDEO=y
1	1	/*
2	2	* Copyright (C) 2016 Freescale Semiconductor, Inc.
	3	+ * Copyright 2017 NXP
3	4	*
4	5	* Configuration settings for the Freescale i.MX7ULP EVK board.
5	6	*
...	...	@@ -194,6 +195,21 @@
194	195
195	196	/* USB Configs */
196	197	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	198	+
	199	+#ifdef CONFIG_VIDEO
	200	+#define CONFIG_VIDEO_MXS
	201	+#define CONFIG_VIDEO_LOGO
	202	+#define CONFIG_SPLASH_SCREEN
	203	+#define CONFIG_SPLASH_SCREEN_ALIGN
	204	+#define CONFIG_CMD_BMP
	205	+#define CONFIG_BMP_16BPP
	206	+#define CONFIG_VIDEO_BMP_RLE8
	207	+#define CONFIG_VIDEO_BMP_LOGO
	208	+#define CONFIG_IMX_VIDEO_SKIP
	209	+
	210	+#define CONFIG_MXC_MIPI_DSI_NORTHWEST
	211	+#define CONFIG_HX8363
	212	+#endif
197	213
198	214	#define CONFIG_OF_SYSTEM_SETUP
199	215