Eric Lee / smarc-uboot

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Commit b7c19ea1ca7d3a02b8aa1e0f756ca60951fa367e

Authored by Sumit Garg
Committed by York Sun
1 parent b3635f57d9
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: LS1046AQDS: Add NOR Secure Boot Target 

Add NOR secure boot target. Also enable sec init.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 3 changed files with 62 additions and 0 deletions Side-by-side Diff

board/freescale/ls1046aqds/MAINTAINERS
Diff comments   View file @ b7c19ea
... ... @@ -8,4 +8,8 @@
8 8 F: configs/ls1046aqds_sdcard_ifc_defconfig
9 9 F: configs/ls1046aqds_sdcard_qspi_defconfig
10 10 F: configs/ls1046aqds_qspi_defconfig
  11 +
  12 +M: Sumit Garg <sumit.garg@nxp.com>
  13 +S: Maintained
  14 +F: configs/ls1046aqds_SECURE_BOOT_defconfig
board/freescale/ls1046aqds/ls1046aqds.c
Diff comments   View file @ b7c19ea
... ... @@ -22,6 +22,7 @@
22 22 #include <fsl_csu.h>
23 23 #include <fsl_esdhc.h>
24 24 #include <fsl_ifc.h>
  25 +#include <fsl_sec.h>
25 26 #include <spl.h>
26 27  
27 28 #include "../common/vid.h"
... ... @@ -265,6 +266,24 @@
265 266  
266 267 if (adjust_vdd(0))
267 268 printf("Warning: Adjusting core voltage failed.\n");
  269 +
  270 +#ifdef CONFIG_SECURE_BOOT
  271 + /*
  272 + * In case of Secure Boot, the IBR configures the SMMU
  273 + * to allow only Secure transactions.
  274 + * SMMU must be reset in bypass mode.
  275 + * Set the ClientPD bit and Clear the USFCFG Bit
  276 + */
  277 + u32 val;
  278 + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  279 + out_le32(SMMU_SCR0, val);
  280 + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  281 + out_le32(SMMU_NSCR0, val);
  282 +#endif
  283 +
  284 +#ifdef CONFIG_FSL_CAAM
  285 + sec_init();
  286 +#endif
268 287  
269 288 return 0;
270 289 }
configs/ls1046aqds_SECURE_BOOT_defconfig
Diff comments   View file @ b7c19ea
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1046AQDS=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
  4 +CONFIG_FIT=y
  5 +CONFIG_FIT_VERBOSE=y
  6 +CONFIG_OF_BOARD_SETUP=y
  7 +CONFIG_SECURE_BOOT=y
  8 +CONFIG_BOOTDELAY=10
  9 +CONFIG_HUSH_PARSER=y
  10 +CONFIG_CMD_BOOTZ=y
  11 +CONFIG_CMD_GREPENV=y
  12 +CONFIG_CMD_MEMTEST=y
  13 +CONFIG_CMD_MEMINFO=y
  14 +CONFIG_CMD_GPT=y
  15 +CONFIG_CMD_MMC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_CMD_I2C=y
  18 +CONFIG_CMD_DHCP=y
  19 +CONFIG_CMD_MII=y
  20 +CONFIG_CMD_PING=y
  21 +CONFIG_CMD_CACHE=y
  22 +CONFIG_CMD_EXT2=y
  23 +CONFIG_CMD_FAT=y
  24 +CONFIG_OF_CONTROL=y
  25 +CONFIG_DM=y
  26 +CONFIG_MTD_NOR_FLASH=y
  27 +CONFIG_SPI_FLASH=y
  28 +CONFIG_NETDEVICES=y
  29 +CONFIG_E1000=y
  30 +CONFIG_PCI=y
  31 +CONFIG_DM_PCI=y
  32 +CONFIG_DM_PCI_COMPAT=y
  33 +CONFIG_PCIE_LAYERSCAPE=y
  34 +CONFIG_SYS_NS16550=y
  35 +CONFIG_DM_SPI=y
  36 +CONFIG_FSL_DSPI=y
  37 +CONFIG_USB=y
  38 +CONFIG_DM_USB=y
  39 +CONFIG_RSA=y