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Commit b80a66033856cc89c62886ae3e5ba54a7faf31ae

Authored by pekon gupta
Committed by Tom Rini
1 parent 6e1899e633
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width 

GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL:    SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
        which is called before probing for devices, hence any ONFI parameter
        information is not available during GPMC initialization.

Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.

This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.

Signed-off-by: Pekon Gupta <pekon@ti.com>

Showing 13 changed files with 38 additions and 5 deletions Side-by-side Diff

... ... @@ -190,6 +190,24 @@
190 190 This is used by SoC platforms which do not have built-in ELM
191 191 hardware engine required for BCH ECC correction.
192 192  
  193 + CONFIG_SYS_NAND_BUSWIDTH_16BIT
  194 + Indicates that NAND device has 16-bit wide data-bus. In absence of this
  195 + config, bus-width of NAND device is assumed to be either 8-bit and later
  196 + determined by reading ONFI params.
  197 + Above config is useful when NAND device's bus-width information cannot
  198 + be determined from on-chip ONFI params, like in following scenarios:
  199 + - SPL boot does not support reading of ONFI parameters. This is done to
  200 + keep SPL code foot-print small.
  201 + - In current U-Boot flow using nand_init(), driver initialization
  202 + happens in board_nand_init() which is called before any device probe
  203 + (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
  204 + not available while configuring controller. So a static CONFIG_NAND_xx
  205 + is needed to know the device's bus-width in advance.
  206 + Some drivers using above config are:
  207 + drivers/mtd/nand/mxc_nand.c
  208 + drivers/mtd/nand/ndfc.c
  209 + drivers/mtd/nand/omap_gpmc.c
  210 +
193 211  
194 212 Platform specific options
195 213 =========================
drivers/mtd/nand/omap_gpmc.c
Diff comments   View file @ b80a660
... ... @@ -782,13 +782,18 @@
782 782 nand->priv = &omap_nand_info;
783 783 nand->cmd_ctrl = omap_nand_hwcontrol;
784 784 nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
785   - /* If we are 16 bit dev, our gpmc config tells us that */
786   - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
787   - nand->options |= NAND_BUSWIDTH_16;
788   -
789 785 nand->chip_delay = 100;
790 786 nand->ecc.layout = &omap_ecclayout;
791 787  
  788 + /* configure driver and controller based on NAND device bus-width */
  789 + gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
  790 +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  791 + nand->options |= NAND_BUSWIDTH_16;
  792 + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
  793 +#else
  794 + nand->options &= ~NAND_BUSWIDTH_16;
  795 + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
  796 +#endif
792 797 /* select ECC scheme */
793 798 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
794 799 err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
include/configs/am3517_crane.h
Diff comments   View file @ b80a660
... ... @@ -329,6 +329,7 @@
329 329 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
330 330  
331 331 /* NAND boot config */
  332 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
332 333 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
333 334 #define CONFIG_SYS_NAND_PAGE_COUNT 64
334 335 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/devkit8000.h
Diff comments   View file @ b80a660
... ... @@ -314,6 +314,7 @@
314 314 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
315 315  
316 316 /* NAND boot config */
  317 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
317 318 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
318 319 #define CONFIG_SYS_NAND_PAGE_COUNT 64
319 320 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/dig297.h
Diff comments   View file @ b80a660
... ... @@ -138,6 +138,7 @@
138 138 * Board NAND Info.
139 139 */
140 140 #define CONFIG_NAND_OMAP_GPMC
  141 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
141 142 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
142 143 /* to access nand */
143 144 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
include/configs/omap3_beagle.h
Diff comments   View file @ b80a660
... ... @@ -295,6 +295,7 @@
295 295 #define CONFIG_SPL_OMAP3_ID_NAND
296 296  
297 297 /* NAND boot config */
  298 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
298 299 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
299 300 #define CONFIG_SYS_NAND_PAGE_COUNT 64
300 301 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_evm_common.h
Diff comments   View file @ b80a660
... ... @@ -120,7 +120,7 @@
120 120  
121 121 /* Max number of NAND devices */
122 122 #define CONFIG_SYS_MAX_NAND_DEVICE 1
123   -
  123 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
124 124 /* Timeout values (in ticks) */
125 125 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
126 126 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
include/configs/omap3_igep00x0.h
Diff comments   View file @ b80a660
... ... @@ -187,6 +187,7 @@
187 187  
188 188 /* NAND boot config */
189 189 #ifdef CONFIG_NAND
  190 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
190 191 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
191 192 #define CONFIG_SYS_NAND_PAGE_COUNT 64
192 193 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_logic.h
Diff comments   View file @ b80a660
... ... @@ -141,6 +141,7 @@
141 141  
142 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
143 143 /* NAND devices */
  144 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
144 145 #define CONFIG_JFFS2_NAND
145 146 /* nand device jffs2 lives on */
146 147 #define CONFIG_JFFS2_DEV "nand0"
include/configs/omap3_overo.h
Diff comments   View file @ b80a660
... ... @@ -206,6 +206,7 @@
206 206 #define CONFIG_SYS_CACHELINE_SIZE 64
207 207  
208 208 /* NAND boot config */
  209 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
209 210 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
210 211 #define CONFIG_SYS_NAND_PAGE_COUNT 64
211 212 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_zoom1.h
Diff comments   View file @ b80a660
... ... @@ -98,6 +98,7 @@
98 98 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
99 99 /* to access nand at */
100 100 /* CS0 */
  101 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
101 102  
102 103 /* Environment information */
103 104  
include/configs/tam3517-common.h
Diff comments   View file @ b80a660
... ... @@ -249,6 +249,7 @@
249 249 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
250 250  
251 251 /* NAND boot config */
  252 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
252 253 #define CONFIG_SYS_NAND_PAGE_COUNT 64
253 254 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
254 255 #define CONFIG_SYS_NAND_OOBSIZE 64
include/configs/tao3530.h
Diff comments   View file @ b80a660
... ... @@ -141,6 +141,7 @@
141 141  
142 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
143 143 /* devices */
  144 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
144 145 /* Environment information */
145 146 #define CONFIG_BOOTDELAY 3
146 147