board/adp-ag102: add configuration of adp-ag102

board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: Macpaul Lin <macpaul@andestech.com>

board/adp-ag102: add configuration of adp-ag102
board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Macpaul Lin · Macpaul Lin
1 parent fd8fed44cc
Showing 4 changed files with 413 additions and 0 deletions Side-by-side Diff
MAINTAINERS
boards.cfg
doc/README.ag102
include/configs/adp-ag102.h
@@ -1191,6 +1191,7 @@
  
 	ADP-AG101	N1213 (AG101 SoC)
 	ADP-AG101P	N1213 (AG101P XC5 FPGA)
+	ADP-AG102	N1213f (AG102 SoC with FPU)
  
 #########################################################################
 # OpenRISC Systems:							#
@@ -370,6 +370,7 @@
 qi_lb60                      mips        xburst      qi_lb60             qi
 adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 adp-ag101p                   nds32       n1213       adp-ag101p          AndesTech      ag101
+adp-ag102                    nds32       n1213       adp-ag102           AndesTech      ag102
 nios2-generic                nios2       nios2       nios2-generic       altera
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
+Andes Technology SoC AG102
+==========================
+
+AG102 is the second SoC produced by Andes Technology using N1213 CPU core
+with FPU and DDR contoller support.
+AG102 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG102
+=========
+
+ADP-AG102 is the SoC with AG102 hardcore CPU.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from SPI ROM and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag102.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag102` in u-boot root to build the image.
+
+Burn u-boot to SPI ROM:
+====================
+
+This section will be added later.
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag102.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG102
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x04200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	(66000000 * 2)
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_01_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		33000000	/* AG102 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_MAX_ADDR	32	/* this comes from <linux/phy.h> */
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_FTGMAC100
+#define CONFIG_FTGMAC100_EGIGA
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * PCI
+ */
+#define CONFIG_PCI
+#define CONFIG_FTPCI100
+#define CONFIG_FTPCI100_MEM_BASE        0xa0000000
+#define CONFIG_FTPCI100_IO_SIZE         FTPCI100_BASE_IO_SIZE(256) /* 256M */
+#define CONFIG_FTPCI100_MEM_SIZE        FTPCI100_MEM_SIZE(128)  /* 128M */
+#define CONFIG_FTPCI100_MEM_BASE_SIZE1  0x50
+
+#define CONFIG_PCI_MEM_BUS	0xa0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000		/* 256M */
+
+#define CONFIG_PCI_IO_BUS	0x90000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00100000		/* 1M */
+
+/*
+ * USB
+ */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#if defined(CONFIG_FTPCI100)
+#define __io /* enable outl & inl */
+#define CONFIG_CMD_USB
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_PCI_EHCI_DEVICE 0
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_PREBOOT                          "usb start;"
+#endif /* #if defiend(CONFIG_FTPCI100) */
+#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
+
+/*
+ * IDE/ATA stuff
+ */
+#define __io
+#define CONFIG_IDE_AHB
+#define CONFIG_IDE_FTIDE020
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT	1	/* preinit for ide		*/
+
+/* max: 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* origin: 2 */
+/* max: 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* origin: (MAXBUS * 2) */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_FTIDE020S_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* for normal regs access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* for alternate regs */
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PCU Power Control Unit configuration
+ */
+#define CONFIG_ANDES_PCU
+
+#ifdef CONFIG_ANDES_PCU
+#include <andestech/andes_pcu.h>
+
+#endif
+
+/*
+ * DDR DRAM controller configuration
+ */
+#define CONFIG_DWCDDR21MCTL
+
+#ifdef CONFIG_DWCDDR21MCTL
+#include <synopsys/dwcddr21mctl.h>
+/* DCR:
+ *   2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
+ *   1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
+ * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
+ * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
+ * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
+ */
+#define CONFIG_SYS_DWCDDR21MCTL_CCR	0x00020004
+#define CONFIG_SYS_DWCDDR21MCTL_CCR2	(DWCDDR21MCTL_CCR_DTT(0x1)	| \
+					DWCDDR21MCTL_CCR_DFTLM(0x4)	| \
+					DWCDDR21MCTL_CCR_HOSTEN(0x1))
+
+/* 0x04: 0x000020d4 */
+#define CONFIG_SYS_DWCDDR21MCTL_DCR	0x000020ca
+
+/* 0x08: 0x0000000f */
+#define CONFIG_SYS_DWCDDR21MCTL_IOCR	0x0000000f
+
+/* 0x10: 0x00034812 */
+#define CONFIG_SYS_DWCDDR21MCTL_DRR	(DWCDDR21MCTL_DRR_TRFC(0x12)	| \
+					DWCDDR21MCTL_DRR_TRFPRD(0x0348))
+/* 0x24 */
+#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0	DWCDDR21MCTL_DLLCR_PHASE(0x0)
+
+/* 0x4c: 0x00000040 */
+#define CONFIG_SYS_DWCDDR21MCTL_RSLR0	0x00000040
+
+/* 0x5c: 0x000055CF */
+#define CONFIG_SYS_DWCDDR21MCTL_RDGR0	0x000055cf
+
+/* 0xa4: 0x00100000 */
+#define CONFIG_SYS_DWCDDR21MCTL_DTAR	(DWCDDR21MCTL_DTAR_DTBANK(0x0)	| \
+					DWCDDR21MCTL_DTAR_DTROW(0x0100)	| \
+					DWCDDR21MCTL_DTAR_DTCOL(0x0))
+/* 0x1f0: 0x00000852 */
+#define CONFIG_SYS_DWCDDR21MCTL_MR	(DWCDDR21MCTL_MR_WR(0x4)	| \
+					DWCDDR21MCTL_MR_CL(0x5)		| \
+					DWCDDR21MCTL_MR_BL(0x2))
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x80000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x80000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x10000000	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk
+ * Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+#endif	/* __CONFIG_H */
...	...	@@ -1191,6 +1191,7 @@
1191	1191
1192	1192	ADP-AG101 N1213 (AG101 SoC)
1193	1193	ADP-AG101P N1213 (AG101P XC5 FPGA)
	1194	+ ADP-AG102 N1213f (AG102 SoC with FPU)
1194	1195
1195	1196	#########################################################################
1196	1197	# OpenRISC Systems: #
...	...	@@ -370,6 +370,7 @@
370	370	qi_lb60 mips xburst qi_lb60 qi
371	371	adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
372	372	adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
	373	+adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102
373	374	nios2-generic nios2 nios2 nios2-generic altera
374	375	PCI5441 nios2 nios2 pci5441 psyent
375	376	PK1C20 nios2 nios2 pk1c20 psyent
	1	+Andes Technology SoC AG102
	2	+==========================
	3	+
	4	+AG102 is the second SoC produced by Andes Technology using N1213 CPU core
	5	+with FPU and DDR contoller support.
	6	+AG102 has integrated both AHB and APB bus and many periphals for application
	7	+and product development.
	8	+
	9	+ADP-AG102
	10	+=========
	11	+
	12	+ADP-AG102 is the SoC with AG102 hardcore CPU.
	13	+
	14	+Configurations
	15	+==============
	16	+
	17	+CONFIG_MEM_REMAP:
	18	+ Doing memory remap is essential for preparing some non-OS or RTOS
	19	+ applications.
	20	+
	21	+CONFIG_SKIP_LOWLEVEL_INIT:
	22	+ If you want to boot this system from SPI ROM and bypass e-bios (the
	23	+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
	24	+ in "include/configs/adp-ag102.h".
	25	+
	26	+Build and boot steps
	27	+====================
	28	+
	29	+build:
	30	+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
	31	+2. Use `make adp-ag102` in u-boot root to build the image.
	32	+
	33	+Burn u-boot to SPI ROM:
	34	+====================
	35	+
	36	+This section will be added later.
	1	+/*
	2	+ * Copyright (C) 2011 Andes Technology Corporation
	3	+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or modify
	9	+ * it under the terms of the GNU General Public License as published by
	10	+ * the Free Software Foundation; either version 2 of the License, or
	11	+ * (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	+ */
	22	+
	23	+#ifndef __CONFIG_H
	24	+#define __CONFIG_H
	25	+
	26	+#include <asm/arch/ag102.h>
	27	+
	28	+/*
	29	+ * CPU and Board Configuration Options
	30	+ */
	31	+#define CONFIG_ADP_AG102
	32	+
	33	+#define CONFIG_USE_INTERRUPT
	34	+
	35	+#define CONFIG_SKIP_LOWLEVEL_INIT
	36	+
	37	+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	38	+#define CONFIG_MEM_REMAP
	39	+#endif
	40	+
	41	+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	42	+#define CONFIG_SYS_TEXT_BASE 0x04200000
	43	+#else
	44	+#define CONFIG_SYS_TEXT_BASE 0x00000000
	45	+#endif
	46	+
	47	+/*
	48	+ * Timer
	49	+ */
	50	+
	51	+/*
	52	+ * According to the discussion in u-boot mailing list before,
	53	+ * CONFIG_SYS_HZ at 1000 is mandatory.
	54	+ */
	55	+#define CONFIG_SYS_HZ 1000
	56	+#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
	57	+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	58	+
	59	+/*
	60	+ * Use Externel CLOCK or PCLK
	61	+ */
	62	+#undef CONFIG_FTRTC010_EXTCLK
	63	+
	64	+#ifndef CONFIG_FTRTC010_EXTCLK
	65	+#define CONFIG_FTRTC010_PCLK
	66	+#endif
	67	+
	68	+#ifdef CONFIG_FTRTC010_EXTCLK
	69	+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	70	+#else
	71	+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	72	+#endif
	73	+
	74	+#define TIMER_LOAD_VAL 0xffffffff
	75	+
	76	+/*
	77	+ * Real Time Clock
	78	+ */
	79	+#define CONFIG_RTC_FTRTC010
	80	+
	81	+/*
	82	+ * Real Time Clock Divider
	83	+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	84	+ */
	85	+#define OSC_5MHZ (5*1000000)
	86	+#define OSC_CLK (2*OSC_5MHZ)
	87	+#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	88	+
	89	+/*
	90	+ * Serial console configuration
	91	+ */
	92	+
	93	+/* FTUART is a high speed NS 16C550A compatible UART */
	94	+#define CONFIG_BAUDRATE 38400
	95	+#define CONFIG_CONS_INDEX 1
	96	+#define CONFIG_SYS_NS16550
	97	+#define CONFIG_SYS_NS16550_SERIAL
	98	+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
	99	+#define CONFIG_SYS_NS16550_REG_SIZE -4
	100	+#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
	101	+
	102	+/* valid baudrates */
	103	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	104	+
	105	+/*
	106	+ * Ethernet
	107	+ */
	108	+#define CONFIG_NET_MULTI
	109	+#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
	110	+#define CONFIG_SYS_DISCOVER_PHY
	111	+#define CONFIG_FTGMAC100
	112	+#define CONFIG_FTGMAC100_EGIGA
	113	+
	114	+#define CONFIG_BOOTDELAY 3
	115	+
	116	+/*
	117	+ * SD (MMC) controller
	118	+ */
	119	+#define CONFIG_MMC
	120	+#define CONFIG_CMD_MMC
	121	+#define CONFIG_GENERIC_MMC
	122	+#define CONFIG_DOS_PARTITION
	123	+#define CONFIG_FTSDC010
	124	+#define CONFIG_FTSDC010_NUMBER 1
	125	+#define CONFIG_FTSDC010_SDIO
	126	+#define CONFIG_CMD_FAT
	127	+#define CONFIG_CMD_EXT2
	128	+
	129	+/*
	130	+ * Command line configuration.
	131	+ */
	132	+#include <config_cmd_default.h>
	133	+
	134	+#define CONFIG_CMD_CACHE
	135	+#define CONFIG_CMD_DATE
	136	+#define CONFIG_CMD_PING
	137	+#define CONFIG_CMD_IDE
	138	+#define CONFIG_CMD_FAT
	139	+#define CONFIG_CMD_ELF
	140	+
	141	+#undef CONFIG_CMD_FLASH
	142	+#undef CONFIG_CMD_IMLS
	143	+
	144	+/*
	145	+ * PCI
	146	+ */
	147	+#define CONFIG_PCI
	148	+#define CONFIG_FTPCI100
	149	+#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
	150	+#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
	151	+#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
	152	+#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
	153	+
	154	+#define CONFIG_PCI_MEM_BUS 0xa0000000
	155	+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	156	+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
	157	+
	158	+#define CONFIG_PCI_IO_BUS 0x90000000
	159	+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	160	+#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
	161	+
	162	+/*
	163	+ * USB
	164	+ */
	165	+#if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI)
	166	+#if defined(CONFIG_FTPCI100)
	167	+#define __io /* enable outl & inl */
	168	+#define CONFIG_CMD_USB
	169	+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
	170	+#define CONFIG_USB_STORAGE
	171	+#define CONFIG_USB_EHCI
	172	+#define CONFIG_PCI_EHCI_DEVICE 0
	173	+#define CONFIG_USB_EHCI_PCI
	174	+#define CONFIG_PREBOOT "usb start;"
	175	+#endif /* #if defiend(CONFIG_FTPCI100) */
	176	+#endif /* #if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI) */
	177	+
	178	+/*
	179	+ * IDE/ATA stuff
	180	+ */
	181	+#define __io
	182	+#define CONFIG_IDE_AHB
	183	+#define CONFIG_IDE_FTIDE020
	184	+
	185	+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	186	+#undef CONFIG_IDE_LED /* no led for ide supported */
	187	+#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	188	+#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
	189	+
	190	+/* max: 2 IDE busses */
	191	+#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
	192	+/* max: 2 drives per IDE bus */
	193	+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
	194	+
	195	+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
	196	+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	197	+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
	198	+
	199	+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
	200	+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
	201	+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
	202	+
	203	+#define CONFIG_MAC_PARTITION
	204	+#define CONFIG_DOS_PARTITION
	205	+#define CONFIG_SUPPORT_VFAT
	206	+
	207	+/*
	208	+ * Miscellaneous configurable options
	209	+ */
	210	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	211	+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
	212	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	213	+
	214	+/* Print Buffer Size */
	215	+#define CONFIG_SYS_PBSIZE \
	216	+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	217	+
	218	+/* max number of command args */
	219	+#define CONFIG_SYS_MAXARGS 16
	220	+
	221	+/* Boot Argument Buffer Size */
	222	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	223	+
	224	+/*
	225	+ * Stack sizes
	226	+ *
	227	+ * The stack sizes are set up in start.S using the settings below
	228	+ */
	229	+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	230	+
	231	+/*
	232	+ * Size of malloc() pool
	233	+ */
	234	+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
	235	+
	236	+/*
	237	+ * size in bytes reserved for initial data
	238	+*/
	239	+#define CONFIG_SYS_GBL_DATA_SIZE 128
	240	+
	241	+/*
	242	+ * AHB Controller configuration
	243	+ */
	244	+#define CONFIG_FTAHBC020S
	245	+
	246	+#ifdef CONFIG_FTAHBC020S
	247	+#include <faraday/ftahbc020s.h>
	248	+
	249	+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
	250	+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
	251	+
	252	+/*
	253	+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
	254	+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
	255	+ * in C language.
	256	+ */
	257	+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
	258	+ (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) \| \
	259	+ FTAHBC020S_SLAVE_BSR_SIZE(0xb))
	260	+#endif
	261	+
	262	+/*
	263	+ * Watchdog
	264	+ */
	265	+#define CONFIG_FTWDT010_WATCHDOG
	266	+
	267	+/*
	268	+ * PCU Power Control Unit configuration
	269	+ */
	270	+#define CONFIG_ANDES_PCU
	271	+
	272	+#ifdef CONFIG_ANDES_PCU
	273	+#include <andestech/andes_pcu.h>
	274	+
	275	+#endif
	276	+
	277	+/*
	278	+ * DDR DRAM controller configuration
	279	+ */
	280	+#define CONFIG_DWCDDR21MCTL
	281	+
	282	+#ifdef CONFIG_DWCDDR21MCTL
	283	+#include <synopsys/dwcddr21mctl.h>
	284	+/* DCR:
	285	+ * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
	286	+ * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
	287	+ * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
	288	+ * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
	289	+ * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
	290	+ */
	291	+#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
	292	+#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) \| \
	293	+ DWCDDR21MCTL_CCR_DFTLM(0x4) \| \
	294	+ DWCDDR21MCTL_CCR_HOSTEN(0x1))
	295	+
	296	+/* 0x04: 0x000020d4 */
	297	+#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
	298	+
	299	+/* 0x08: 0x0000000f */
	300	+#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
	301	+
	302	+/* 0x10: 0x00034812 */
	303	+#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) \| \
	304	+ DWCDDR21MCTL_DRR_TRFPRD(0x0348))
	305	+/* 0x24 */
	306	+#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
	307	+
	308	+/* 0x4c: 0x00000040 */
	309	+#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
	310	+
	311	+/* 0x5c: 0x000055CF */
	312	+#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
	313	+
	314	+/* 0xa4: 0x00100000 */
	315	+#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) \| \
	316	+ DWCDDR21MCTL_DTAR_DTROW(0x0100) \| \
	317	+ DWCDDR21MCTL_DTAR_DTCOL(0x0))
	318	+/* 0x1f0: 0x00000852 */
	319	+#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) \| \
	320	+ DWCDDR21MCTL_MR_CL(0x5) \| \
	321	+ DWCDDR21MCTL_MR_BL(0x2))
	322	+#endif
	323	+
	324	+/*
	325	+ * Physical Memory Map
	326	+ */
	327	+#if defined(CONFIG_MEM_REMAP) \|\| defined(CONFIG_SKIP_LOWLEVEL_INIT)
	328	+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	329	+#if defined(CONFIG_MEM_REMAP)
	330	+#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
	331	+#endif
	332	+#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
	333	+#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
	334	+#endif
	335	+
	336	+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	337	+#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
	338	+
	339	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	340	+
	341	+#ifdef CONFIG_MEM_REMAP
	342	+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	343	+ GENERATED_GBL_DATA_SIZE)
	344	+#else
	345	+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	346	+ GENERATED_GBL_DATA_SIZE)
	347	+#endif /* CONFIG_MEM_REMAP */
	348	+
	349	+/*
	350	+ * Load address and memory test area should agree with
	351	+ * board/faraday/a320/config.mk
	352	+ * Be careful not to overwrite U-boot itself.
	353	+ */
	354	+#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
	355	+
	356	+/* memtest works on 63 MB in DRAM */
	357	+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
	358	+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
	359	+
	360	+/*
	361	+ * Static memory controller configuration
	362	+ */
	363	+
	364	+/*
	365	+ * FLASH and environment organization
	366	+ */
	367	+#define CONFIG_SYS_NO_FLASH
	368	+
	369	+/*
	370	+ * Env Storage Settings
	371	+ */
	372	+#define CONFIG_ENV_IS_NOWHERE
	373	+#define CONFIG_ENV_SIZE 4096
	374	+
	375	+#endif /* __CONFIG_H */