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Commit b9735cbaebf497209a9cb111bdf02aacdb3b8866

Authored by Scott Wood
1 parent 510ed3b8fd
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c 

There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

Showing 9 changed files with 87 additions and 87 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
View file @ b9735cb
1   -/*
2   - * Copyright 2009 Freescale Semiconductor, Inc.
3   - *
4   - * See file CREDITS for list of people who contributed to this
5   - * project.
6   - *
7   - * This program is free software; you can redistribute it and/or
8   - * modify it under the terms of the GNU General Public License as
9   - * published by the Free Software Foundation; either version 2 of
10   - * the License, or (at your option) any later version.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20   - * MA 02111-1307 USA
21   - */
22   -
23   -#include <common.h>
24   -#include <asm/processor.h>
25   -#include <asm/global_data.h>
26   -#include <asm/fsl_ifc.h>
27   -#include <asm/io.h>
28   -
29   -DECLARE_GLOBAL_DATA_PTR;
30   -
31   -void cpu_init_f(void)
32   -{
33   -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
34   - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
35   -
36   - out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
37   -
38   - /* set MBECCDIS=1, SBECCDIS=1 */
39   - out_be32(&l2cache->l2errdis,
40   - (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
41   -
42   - /* set L2E=1 & L2SRAM=001 */
43   - out_be32(&l2cache->l2ctl,
44   - (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
45   -#endif
46   -}
47   -
48   -#ifndef CONFIG_SYS_FSL_TBCLK_DIV
49   -#define CONFIG_SYS_FSL_TBCLK_DIV 8
50   -#endif
51   -
52   -void udelay(unsigned long usec)
53   -{
54   - u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
55   - u32 ticks = ticks_per_usec * usec;
56   - u32 s = mfspr(SPRN_TBRL);
57   -
58   - while ((mfspr(SPRN_TBRL) - s) < ticks);
59   -}
arch/powerpc/cpu/mpc85xx/spl_minimal.c
Diff comments   View file @ b9735cb
  1 +/*
  2 + * Copyright 2009 Freescale Semiconductor, Inc.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <common.h>
  24 +#include <asm/processor.h>
  25 +#include <asm/global_data.h>
  26 +#include <asm/fsl_ifc.h>
  27 +#include <asm/io.h>
  28 +
  29 +DECLARE_GLOBAL_DATA_PTR;
  30 +
  31 +void cpu_init_f(void)
  32 +{
  33 +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  34 + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  35 +
  36 + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
  37 +
  38 + /* set MBECCDIS=1, SBECCDIS=1 */
  39 + out_be32(&l2cache->l2errdis,
  40 + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
  41 +
  42 + /* set L2E=1 & L2SRAM=001 */
  43 + out_be32(&l2cache->l2ctl,
  44 + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
  45 +#endif
  46 +}
  47 +
  48 +#ifndef CONFIG_SYS_FSL_TBCLK_DIV
  49 +#define CONFIG_SYS_FSL_TBCLK_DIV 8
  50 +#endif
  51 +
  52 +void udelay(unsigned long usec)
  53 +{
  54 + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
  55 + u32 ticks = ticks_per_usec * usec;
  56 + u32 s = mfspr(SPRN_TBRL);
  57 +
  58 + while ((mfspr(SPRN_TBRL) - s) < ticks);
  59 +}
nand_spl/board/freescale/mpc8536ds/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -80,9 +80,9 @@
80 80 @rm -f $(obj)cpu_init_early.c
81 81 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
82 82  
83   -$(obj)cpu_init_nand.c:
84   - @rm -f $(obj)cpu_init_nand.c
85   - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
  83 +$(obj)spl_minimal.c:
  84 + @rm -f $(obj)spl_minimal.c
  85 + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
86 86  
87 87 $(obj)fsl_law.c:
88 88 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/mpc8569mds/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -80,9 +80,9 @@
80 80 @rm -f $(obj)cpu_init_early.c
81 81 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
82 82  
83   -$(obj)cpu_init_nand.c:
84   - @rm -f $(obj)cpu_init_nand.c
85   - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
  83 +$(obj)spl_minimal.c:
  84 + @rm -f $(obj)spl_minimal.c
  85 + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
86 86  
87 87 $(obj)fsl_law.c:
88 88 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/mpc8572ds/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -80,9 +80,9 @@
80 80 @rm -f $(obj)cpu_init_early.c
81 81 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
82 82  
83   -$(obj)cpu_init_nand.c:
84   - @rm -f $(obj)cpu_init_nand.c
85   - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
  83 +$(obj)spl_minimal.c:
  84 + @rm -f $(obj)spl_minimal.c
  85 + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
86 86  
87 87 $(obj)fsl_law.c:
88 88 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/p1010rdb/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o ticks.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -80,9 +80,9 @@
80 80 @rm -f $(obj)cpu_init_early.c
81 81 ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
82 82  
83   -$(obj)cpu_init_nand.c:
84   - @rm -f $(obj)cpu_init_nand.c
85   - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
  83 +$(obj)spl_minimal.c:
  84 + @rm -f $(obj)spl_minimal.c
  85 + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
86 86  
87 87 $(obj)fsl_law.c:
88 88 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/p1023rds/Makefile
Diff comments   View file @ b9735cb
... ... @@ -34,7 +34,7 @@
34 34 CFLAGS += -DCONFIG_NAND_SPL
35 35  
36 36 SOBJS = start.o resetvec.o
37   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  37 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
38 38 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
39 39  
40 40 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -75,9 +75,9 @@
75 75 @rm -f $(obj)cpu_init_early.c
76 76 ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
77 77  
78   -$(obj)cpu_init_nand.c:
79   - @rm -f $(obj)cpu_init_nand.c
80   - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
  78 +$(obj)spl_minimal.c:
  79 + @rm -f $(obj)spl_minimal.c
  80 + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
81 81  
82 82 $(obj)fsl_law.c:
83 83 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/p1_p2_rdb/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -80,9 +80,9 @@
80 80 @rm -f $(obj)cpu_init_early.c
81 81 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
82 82  
83   -$(obj)cpu_init_nand.c:
84   - @rm -f $(obj)cpu_init_nand.c
85   - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
  83 +$(obj)spl_minimal.c:
  84 + @rm -f $(obj)spl_minimal.c
  85 + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
86 86  
87 87 $(obj)fsl_law.c:
88 88 @rm -f $(obj)fsl_law.c
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
Diff comments   View file @ b9735cb
... ... @@ -39,7 +39,7 @@
39 39 CFLAGS += -DCONFIG_NAND_SPL
40 40  
41 41 SOBJS = start.o resetvec.o
42   -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
  42 +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43 43 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44 44  
45 45 SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
... ... @@ -79,9 +79,9 @@
79 79 @rm -f $(obj)cpu_init_early.c
80 80 ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
81 81  
82   -$(obj)cpu_init_nand.c:
83   - @rm -f $(obj)cpu_init_nand.c
84   - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
  82 +$(obj)spl_minimal.c:
  83 + @rm -f $(obj)spl_minimal.c
  84 + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
85 85  
86 86 $(obj)fsl_law.c:
87 87 @rm -f $(obj)fsl_law.c