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Commit b99ed2766ae7bfc28077b8e2ce90ce2402483195

Authored by Nikolay Dimitrov
Committed by Stefano Babic
1 parent 56740fa96f
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

novena: Fix ethernet PHY reset sequence 

This patch fixes conflict between PHY pins becoming outputs after reset and
imx6 still driving the pins. It also fixes the reset timing as recommended by
the PHY datasheet.

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 2 changed files with 46 additions and 21 deletions Side-by-side Diff

board/kosagi/novena/novena.c
Diff comments   View file @ b99ed27
... ... @@ -237,9 +237,6 @@
237 237 setup_display();
238 238 #endif
239 239  
240   - /* Bring Ethernet PHY out of reset. */
241   - gpio_set_value(IMX_GPIO_NR(3, 23), 1);
242   -
243 240 return 0;
244 241 }
245 242  
board/kosagi/novena/novena_spl.c
Diff comments   View file @ b99ed27
... ... @@ -41,6 +41,10 @@
41 41 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
42 42 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43 43  
  44 +#define ENET_PHY_CFG_PAD_CTRL \
  45 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  46 + PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
  47 +
44 48 #define RGMII_PAD_CTRL \
45 49 (PAD_CTL_PKE | PAD_CTL_PUE | \
46 50 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
... ... @@ -98,18 +102,20 @@
98 102 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
99 103 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
100 104 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
101   - /* pin 35 - 1 (PHY_AD2) on reset */
102   - MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
103   - /* pin 32 - 1 - (MODE0) all */
104   - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
105   - /* pin 31 - 1 - (MODE1) all */
106   - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
107   - /* pin 28 - 1 - (MODE2) all */
108   - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
109   - /* pin 27 - 1 - (MODE3) all */
110   - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
111   - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
112   - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  105 +
  106 + /* pin 35, PHY_AD2 */
  107 + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  108 + /* pin 32, MODE0 */
  109 + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  110 + /* pin 31, MODE1 */
  111 + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  112 + /* pin 28, MODE2 */
  113 + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  114 + /* pin 27, MODE3 */
  115 + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  116 + /* pin 33, CLK125_EN */
  117 + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  118 +
113 119 /* pin 42 PHY nRST */
114 120 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 121 };
116 122  
117 123  
118 124  
... ... @@ -127,15 +133,37 @@
127 133 {
128 134 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
129 135  
  136 + /* Assert Ethernet PHY nRST */
130 137 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
131   - gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
132   - gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
133   - gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
134   - gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
135   - gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
136   - gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
137 138  
  139 + /*
  140 + * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
  141 + * de-assertion. The intention is to use weak signal drivers (pull-ups)
  142 + * to prevent the conflict between PHY pins becoming outputs after
  143 + * reset and imx6 still driving the pins. The issue is described in PHY
  144 + * datasheet, p.14
  145 + */
  146 + gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
  147 + gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
  148 + gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
  149 + gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
  150 + gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
  151 + gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
  152 +
  153 + /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
  154 + mdelay(10);
  155 +
  156 + /* De-assert Ethernet PHY nRST */
  157 + gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  158 +
  159 + /* PHY is now configured, connect FEC to the pads */
138 160 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  161 +
  162 + /*
  163 + * PHY datasheet recommends on p.53 to wait at least 100us after reset
  164 + * before using MII, so we enforce the delay here
  165 + */
  166 + udelay(100);
139 167 }
140 168  
141 169 /*