ARMV7: Add support for Samsung ORIGEN board

Origen board is based upon S5PV310 SoC which is similiar to S5PC210 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

ARMV7: Add support for Samsung ORIGEN board
Origen board is based upon S5PV310 SoC which is similiar to S5PC210 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Chander Kashyap · Albert ARIBAUD
1 parent 85776b0214
Showing 8 changed files with 1641 additions and 0 deletions Side-by-side Diff
MAINTAINERS
board/samsung/origen/Makefile
board/samsung/origen/lowlevel_init.S
board/samsung/origen/mem_setup.S
board/samsung/origen/origen.c
board/samsung/origen/origen_setup.h
boards.cfg
include/configs/origen.h
@@ -707,6 +707,7 @@
  
 Chander Kashyap <k.chander@samsung.com>
  
+	origen			ARM ARMV7 (S5PC210 SoC)
 	SMDKV310		ARM ARMV7 (S5PC210 SoC)
  
 Torsten Koschorrek <koschorrek@synertronixx.de>
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= mem_setup.o
+SOBJS	+= lowlevel_init.o
+COBJS	+= origen.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * Lowlevel setup for ORIGEN board based on S5PV310
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include "origen_setup.h"
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	push	{lr}
+
+	/* r5 has always zero */
+	mov	r5, #0
+	ldr	r7, =S5PC210_GPIO_PART1_BASE
+	ldr	r6, =S5PC210_GPIO_PART2_BASE
+
+	/* check reset status */
+	ldr	r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
+	ldr	r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* LPA wakeup reset */
+	ldr	r2, =S5P_CHECK_LPA
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in ram, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp	r1, r2			/* compare r1, r2 */
+	beq	1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl system_clock_init
+
+	/* Memory initialize */
+	bl mem_ctrl_asm_init
+
+1:
+	/* for UART */
+	bl uart_asm_init
+	bl tzpc_init
+	pop	{pc}
+
+wakeup_reset:
+	bl system_clock_init
+	bl mem_ctrl_asm_init
+	bl tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr	r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
+
+	/* r1 = physical address of s5pc210_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel*/
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	push	{lr}
+	ldr	r0, =S5PC210_CLOCK_BASE
+
+	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
+	ldr	r1, =CLK_SRC_CPU_VAL
+	ldr	r2, =CLK_SRC_CPU_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+2:	subs	r1, r1, #1
+	bne	2b
+
+	ldr	r1, =CLK_SRC_TOP0_VAL
+	ldr	r2, =CLK_SRC_TOP0_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =CLK_SRC_TOP1_VAL
+	ldr	r2, =CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* DMC */
+	ldr	r1, =CLK_SRC_DMC_VAL
+	ldr	r2, =CLK_SRC_DMC_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_LEFTBUS */
+	ldr	r1, =CLK_SRC_LEFTBUS_VAL
+	ldr	r2, =CLK_SRC_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_RIGHTBUS */
+	ldr	r1, =CLK_SRC_RIGHTBUS_VAL
+	ldr	r2, =CLK_SRC_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+	ldr	r1, =CLK_SRC_FSYS_VAL
+	ldr	r2, =CLK_SRC_FSYS_OFFSET
+	str	r1, [r0, r2]
+
+	/* UART[0:4] */
+	ldr	r1, =CLK_SRC_PERIL0_VAL
+	ldr	r2, =CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	/* CLK_DIV_CPU0 */
+	ldr	r1, =CLK_DIV_CPU0_VAL
+	ldr	r2, =CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_CPU1 */
+	ldr	r1, =CLK_DIV_CPU1_VAL
+	ldr	r2, =CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_DMC0 */
+	ldr	r1, =CLK_DIV_DMC0_VAL
+	ldr	r2, =CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_DIV_DMC1 */
+	ldr	r1, =CLK_DIV_DMC1_VAL
+	ldr	r2, =CLK_DIV_DMC1_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_LEFTBUS */
+	ldr	r1, =CLK_DIV_LEFTBUS_VAL
+	ldr	r2, =CLK_DIV_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_RIGHTBUS */
+	ldr	r1, =CLK_DIV_RIGHTBUS_VAL
+	ldr	r2, =CLK_DIV_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_TOP */
+	ldr	r1, =CLK_DIV_TOP_VAL
+	ldr	r2, =CLK_DIV_TOP_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[0:1] */
+	ldr	r1, =CLK_DIV_FSYS1_VAL		/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =CLK_DIV_FSYS1_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[2:3] */
+	ldr	r1, =CLK_DIV_FSYS2_VAL		/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =CLK_DIV_FSYS2_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC4 */
+	ldr	r1, =CLK_DIV_FSYS3_VAL		/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =CLK_DIV_FSYS3_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_PERIL0: UART Clock Divisors */
+	ldr	r1, =CLK_DIV_PERIL0_VAL
+	ldr	r2, =CLK_DIV_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* Set PLL locktime */
+	ldr	r1, =PLL_LOCKTIME
+	ldr	r2, =APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =PLL_LOCKTIME
+	ldr	r2, =MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =PLL_LOCKTIME
+	ldr	r2, =EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =PLL_LOCKTIME
+	ldr	r2, =VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	/* APLL_CON1 */
+	ldr	r1, =APLL_CON1_VAL
+	ldr	r2, =APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/* APLL_CON0 */
+	ldr	r1, =APLL_CON0_VAL
+	ldr	r2, =APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MPLL_CON1 */
+	ldr	r1, =MPLL_CON1_VAL
+	ldr	r2, =MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/* MPLL_CON0 */
+	ldr	r1, =MPLL_CON0_VAL
+	ldr	r2, =MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* EPLL */
+	ldr	r1, =EPLL_CON1_VAL
+	ldr	r2, =EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/* EPLL_CON0 */
+	ldr	r1, =EPLL_CON0_VAL
+	ldr	r2, =EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* VPLL_CON1 */
+	ldr	r1, =VPLL_CON1_VAL
+	ldr	r2, =VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/* VPLL_CON0 */
+	ldr	r1, =VPLL_CON0_VAL
+	ldr	r2, =VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+4:	subs	r1, r1, #1
+	bne	4b
+
+	pop	{pc}
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+	.globl uart_asm_init
+uart_asm_init:
+
+	/* setup UART0-UART3 GPIOs (part1) */
+	mov	r0, r7
+	ldr	r1, =S5PC210_GPIO_A0_CON_VAL
+	str	r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
+	ldr	r1, =S5PC210_GPIO_A1_CON_VAL
+	str	r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
+
+	ldr r0, =S5PC210_UART_BASE
+	add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+
+	ldr	r1, =ULCON_VAL
+	str	r1, [r0, #ULCON_OFFSET]
+	ldr	r1, =UCON_VAL
+	str	r1, [r0, #UCON_OFFSET]
+	ldr	r1, =UFCON_VAL
+	str	r1, [r0, #UFCON_OFFSET]
+	ldr	r1, =UBRDIV_VAL
+	str	r1, [r0, #UBRDIV_OFFSET]
+	ldr	r1, =UFRACVAL_VAL
+	str	r1, [r0, #UFRACVAL_OFFSET]
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/* Setting TZPC[TrustZone Protection Controller] */
+tzpc_init:
+	ldr	r0, =TZPC0_BASE
+	mov	r1, #R0SIZE
+	str	r1, [r0]
+	mov	r1, #DECPROTXSET
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC1_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC2_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC3_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC4_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC5_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	mov	pc, lr
+/*
+ * Memory setup for ORIGEN board based on S5PV310
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "origen_setup.h"
+#define SET_MIU
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	/*
+	 * Async bridge configuration at CPU_core:
+	 * 1: half_sync
+	 * 0: full_sync
+	 */
+	ldr r0, =ASYNC_CONFIG
+	mov r1, #1
+	str r1, [r0]
+
+#ifdef SET_MIU
+	ldr	r0, =S5PC210_MIU_BASE
+	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
+	ldr	r1, =0x20001507
+	str	r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
+
+	/* Update MIU Configuration */
+	ldr	r1, =0x00000001
+	str	r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
+#endif
+	/* DREX0 */
+	ldr	r0, =S5PC210_DMC0_BASE
+
+	/*
+	 * DLL Parameter Setting:
+	 * Termination: Enable R/W
+	 * Phase Delay for DQS Cleaning: 180' Shift
+	 */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/*
+	 * ZQ Calibration
+	 * Termination: Disable
+	 * Auto Calibration Start: Enable
+	 */
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #DMC_PHYZQCONTROL]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Reset Force DLL Resyncronization */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Enable Differential DQS, DLL Off*/
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Activate PHY DLL: DLL On */
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Set DLL Parameters */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* DLL Start */
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL2]
+
+	/* Set Clock Ratio of Bus clock to Memory Clock */
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	/*
+	 * Memor Burst length: 8
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: DDR3
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	ldr	r1, =0x00312640
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	/*
+	 * Memory Configuration Chip 0
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	/*
+	 * Memory Configuration Chip 1
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #DMC_MEMCONFIG1]
+
+	/* Config Precharge Policy */
+	ldr	r1, =0xff000000
+	str	r1, [r0, #DMC_PRECHCONFIG]
+
+	/*
+	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	ldr	r1, =0x000000BB
+	str	r1, [r0, #DMC_TIMINGAREF]
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #DMC_TIMINGROW]
+	ldr	r1, =0x46400506
+	str	r1, [r0, #DMC_TIMINGDATA]
+	ldr	r1, =0x52000A3C
+	str	r1, [r0, #DMC_TIMINGPOWER]
+
+	/* Chip0: NOP Command: Assert and Hold CKE to high level */
+	ldr	r1, =0x07000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00020000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00030000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00010002
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00000328
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	/* Chip0: ZQINIT */
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	/* Chip1: NOP Command: Assert and Hold CKE to high level */
+	ldr	r1, =0x07100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00120000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00130000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00110002
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00100328
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	/* Chip1: ZQINIT */
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #DMC_PHYCONTROL1]
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* DREX1 */
+	ldr	r0, =S5PC210_DMC1_BASE	@0x10410000
+
+	/*
+	 * DLL Parameter Setting:
+	 * Termination: Enable R/W
+	 * Phase Delay for DQS Cleaning: 180' Shift
+	 */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/*
+	 * ZQ Calibration:
+	 * Termination: Disable
+	 * Auto Calibration Start: Enable
+	 */
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #DMC_PHYZQCONTROL]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Reset Force DLL Resyncronization */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Enable Differential DQS, DLL Off*/
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Activate PHY DLL: DLL On */
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Set DLL Parameters */
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* DLL Start */
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL2]
+
+	/* Set Clock Ratio of Bus clock to Memory Clock */
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	/*
+	 * Memor Burst length: 8
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: DDR3
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	ldr	r1, =0x00312640
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	/*
+	 * Memory Configuration Chip 0
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	/*
+	 * Memory Configuration Chip 1
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #DMC_MEMCONFIG1]
+
+	/* Config Precharge Policy */
+	ldr	r1, =0xff000000
+	str	r1, [r0, #DMC_PRECHCONFIG]
+
+	/*
+	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	ldr	r1, =0x000000BB
+	str	r1, [r0, #DMC_TIMINGAREF]
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #DMC_TIMINGROW]
+	ldr	r1, =0x46400506
+	str	r1, [r0, #DMC_TIMINGDATA]
+	ldr	r1, =0x52000A3C
+	str	r1, [r0, #DMC_TIMINGPOWER]
+
+	/* Chip0: NOP Command: Assert and Hold CKE to high level */
+	ldr	r1, =0x07000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00020000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00030000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00010002
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00000328
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	/* Chip 0: ZQINIT */
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	/* Chip1: NOP Command: Assert and Hold CKE to high level */
+	ldr	r1, =0x07100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00120000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00130000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00110002
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00100328
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	/* Chip1: ZQINIT */
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #DMC_PHYCONTROL1]
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	/* Wait ?us*/
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* turn on DREX0, DREX1 */
+	ldr	r0, =S5PC210_DMC0_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	ldr	r0, =S5PC210_DMC1_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	mov	pc, lr
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+
+int board_init(void)
+{
+	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+							PHYS_SDRAM_2_SIZE);
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+							PHYS_SDRAM_3_SIZE);
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+							PHYS_SDRAM_4_SIZE);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: ORIGEN\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPK2[0]	SD_2_CLK(2)
+	 * GPK2[1]	SD_2_CMD(2)
+	 * GPK2[2]	SD_2_CDn
+	 * GPK2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		/* GPK2[0:6] special function 2 */
+		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == 0 || i == 1) {
+			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+	}
+
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
+/*
+ * Machine Specific Values for ORIGEN board based on S5PV310
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ORIGEN_SETUP_H
+#define _ORIGEN_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* Offsets of clock registers (sources and dividers) */
+#define CLK_SRC_CPU_OFFSET	0x14200
+#define CLK_DIV_CPU0_OFFSET	0x14500
+#define CLK_DIV_CPU1_OFFSET	0x14504
+
+#define CLK_SRC_DMC_OFFSET	0x10200
+#define CLK_DIV_DMC0_OFFSET	0x10500
+#define CLK_DIV_DMC1_OFFSET	0x10504
+
+#define CLK_SRC_TOP0_OFFSET	0xC210
+#define CLK_SRC_TOP1_OFFSET	0xC214
+#define CLK_DIV_TOP_OFFSET	0xC510
+
+#define CLK_SRC_LEFTBUS_OFFSET	0x4200
+#define CLK_DIV_LEFTBUS_OFFSET	0x4500
+
+#define CLK_SRC_RIGHTBUS_OFFSET	0x8200
+#define CLK_DIV_RIGHTBUS_OFFSET	0x8500
+
+#define CLK_SRC_FSYS_OFFSET	0xC240
+#define CLK_DIV_FSYS1_OFFSET	0xC544
+#define CLK_DIV_FSYS2_OFFSET	0xC548
+#define CLK_DIV_FSYS3_OFFSET	0xC54C
+
+#define CLK_SRC_PERIL0_OFFSET	0xC250
+#define CLK_DIV_PERIL0_OFFSET	0xC550
+
+#define APLL_LOCK_OFFSET	0x14000
+#define MPLL_LOCK_OFFSET	0x14008
+#define APLL_CON0_OFFSET	0x14100
+#define APLL_CON1_OFFSET	0x14104
+#define MPLL_CON0_OFFSET	0x14108
+#define MPLL_CON1_OFFSET	0x1410C
+
+#define EPLL_LOCK_OFFSET	0xC010
+#define VPLL_LOCK_OFFSET	0xC020
+#define EPLL_CON0_OFFSET	0xC110
+#define EPLL_CON1_OFFSET	0xC114
+#define VPLL_CON0_OFFSET	0xC120
+#define VPLL_CON1_OFFSET	0xC124
+
+/* DMC: DRAM Controllor Register offsets */
+#define DMC_CONCONTROL		0x00
+#define DMC_MEMCONTROL		0x04
+#define DMC_MEMCONFIG0		0x08
+#define DMC_MEMCONFIG1		0x0C
+#define DMC_DIRECTCMD		0x10
+#define DMC_PRECHCONFIG		0x14
+#define DMC_PHYCONTROL0		0x18
+#define DMC_PHYCONTROL1		0x1C
+#define DMC_PHYCONTROL2		0x20
+#define DMC_TIMINGAREF		0x30
+#define DMC_TIMINGROW		0x34
+#define DMC_TIMINGDATA		0x38
+#define DMC_TIMINGPOWER		0x3C
+#define DMC_PHYZQCONTROL	0x44
+
+/* Bus Configuration Register Address */
+#define ASYNC_CONFIG		0x10010350
+
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET		0xC00
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+
+/* GPIO Offsets for UART: GPIO Contol Register */
+#define S5PC210_GPIO_A0_CON_OFFSET	0x00
+#define S5PC210_GPIO_A1_CON_OFFSET	0x20
+
+/* UART Register offsets */
+#define ULCON_OFFSET		0x00
+#define UCON_OFFSET		0x04
+#define UFCON_OFFSET		0x08
+#define UBRDIV_OFFSET		0x28
+#define UFRACVAL_OFFSET		0x2C
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE		0x10110000
+#define TZPC1_BASE		0x10120000
+#define TZPC2_BASE		0x10130000
+#define TZPC3_BASE		0x10140000
+#define TZPC4_BASE		0x10150000
+#define TZPC5_BASE		0x10160000
+
+#define TZPC_DECPROT0SET_OFFSET	0x804
+#define TZPC_DECPROT1SET_OFFSET	0x810
+#define TZPC_DECPROT2SET_OFFSET	0x81C
+#define TZPC_DECPROT3SET_OFFSET	0x828
+
+/* CLK_SRC_CPU */
+#define MUX_HPM_SEL_MOUTAPLL		0x0
+#define MUX_HPM_SEL_SCLKMPLL		0x1
+#define MUX_CORE_SEL_MOUTAPLL		0x0
+#define MUX_CORE_SEL_SCLKMPLL		0x1
+#define MUX_MPLL_SEL_FILPLL		0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
+#define MUX_APLL_SEL_FILPLL		0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
+#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
+					| (MUX_CORE_SEL_MOUTAPLL << 16) \
+					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO		0x0
+#define PCLK_DBG_RATIO		0x1
+#define ATB_RATIO		0x3
+#define PERIPH_RATIO		0x3
+#define COREM1_RATIO		0x7
+#define COREM0_RATIO		0x3
+#define CORE_RATIO		0x0
+#define CLK_DIV_CPU0_VAL	((APLL_RATIO << 24) \
+				| (PCLK_DBG_RATIO << 20) \
+				| (ATB_RATIO << 16) \
+				| (PERIPH_RATIO << 12) \
+				| (COREM1_RATIO << 8) \
+				| (COREM0_RATIO << 4) \
+				| (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO		0x0
+#define COPY_RATIO		0x3
+#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_SRC_DMC */
+#define MUX_PWI_SEL_XXTI		0x0
+#define MUX_PWI_SEL_XUSBXTI		0x1
+#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
+#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
+#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
+#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
+#define MUX_PWI_SEL_SCLKMPLL		0x6
+#define MUX_PWI_SEL_SCLKEPLL		0x7
+#define MUX_PWI_SEL_SCLKVPLL		0x8
+#define MUX_DPHY_SEL_SCLKMPLL		0x0
+#define MUX_DPHY_SEL_SCLKAPLL		0x1
+#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
+#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
+#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL_XUSBXTI << 16) \
+					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
+					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO	0x1
+#define COPY2_RATIO		0x3
+#define DMCP_RATIO		0x1
+#define DMCD_RATIO		0x1
+#define DMC_RATIO		0x1
+#define DPHY_RATIO		0x1
+#define ACP_PCLK_RATIO		0x1
+#define ACP_RATIO		0x3
+#define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
+				| (COPY2_RATIO << 24) \
+				| (DMCP_RATIO << 20) \
+				| (DMCD_RATIO << 16) \
+				| (DMC_RATIO << 12) \
+				| (DPHY_RATIO << 8) \
+				| (ACP_PCLK_RATIO << 4)	\
+				| (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO		0x1
+#define DVSEM_RATIO		0x1
+#define PWI_RATIO		0x1
+#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
+				| (DVSEM_RATIO << 16) \
+				| (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133	0x0
+#define MUX_ONENAND_SEL_ACLK_160	0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
+#define MUX_VPLL_SEL_FINPLL		0x0
+#define MUX_VPLL_SEL_FOUTVPLL		0x1
+#define MUX_EPLL_SEL_FINPLL		0x0
+#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
+					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+					| (MUX_VPLL_SEL_FINPLL << 8) \
+					| (MUX_EPLL_SEL_FINPLL << 4)\
+					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_SRC_TOP1 */
+#define VPLLSRC_SEL_FINPLL	0x0
+#define VPLLSRC_SEL_SCLKHDMI24M	0x1
+#define CLK_SRC_TOP1_VAL	(VPLLSRC_SEL_FINPLL)
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO		0x0
+#define ACLK_133_RATIO		0x5
+#define ACLK_160_RATIO		0x4
+#define ACLK_100_RATIO		0x7
+#define ACLK_200_RATIO		0x3
+#define CLK_DIV_TOP_VAL		((ONENAND_RATIO << 16)	\
+				| (ACLK_133_RATIO << 12)\
+				| (ACLK_160_RATIO << 8)	\
+				| (ACLK_100_RATIO << 4)	\
+				| (ACLK_200_RATIO << 0))
+
+/* CLK_SRC_LEFTBUS */
+#define MUX_GDL_SEL_SCLKMPLL	0x0
+#define MUX_GDL_SEL_SCLKAPLL	0x1
+#define CLK_SRC_LEFTBUS_VAL	(MUX_GDL_SEL_SCLKMPLL)
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO		0x1
+#define GDL_RATIO		0x3
+#define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define MUX_GDR_SEL_SCLKMPLL	0x0
+#define MUX_GDR_SEL_SCLKAPLL	0x1
+#define CLK_SRC_RIGHTBUS_VAL	(MUX_GDR_SEL_SCLKMPLL)
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO		0x1
+#define GDR_RATIO		0x3
+#define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL	0
+#define SATA_SEL_SCLKAPLL	1
+
+#define MMC_SEL_XXTI		0
+#define MMC_SEL_XUSBXTI		1
+#define MMC_SEL_SCLK_HDMI24M	2
+#define MMC_SEL_SCLK_USBPHY0	3
+#define MMC_SEL_SCLK_USBPHY1	4
+#define MMC_SEL_SCLK_HDMIPHY	5
+#define MMC_SEL_SCLKMPLL	6
+#define MMC_SEL_SCLKEPLL	7
+#define MMC_SEL_SCLKVPLL	8
+
+#define MMCC0_SEL		MMC_SEL_SCLKMPLL
+#define MMCC1_SEL		MMC_SEL_SCLKMPLL
+#define MMCC2_SEL		MMC_SEL_SCLKMPLL
+#define MMCC3_SEL		MMC_SEL_SCLKMPLL
+#define MMCC4_SEL		MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
+				| (MMCC4_SEL << 16) \
+				| (MMCC3_SEL << 12) \
+				| (MMCC2_SEL << 8) \
+				| (MMCC1_SEL << 4) \
+				| (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO		0xF
+#define MMC0_PRE_RATIO		0x0
+#define MMC1_RATIO		0xF
+#define MMC1_PRE_RATIO		0x0
+#define CLK_DIV_FSYS1_VAL	((MMC1_PRE_RATIO << 24) \
+				| (MMC1_RATIO << 16) \
+				| (MMC0_PRE_RATIO << 8) \
+				| (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO		0xF
+#define MMC2_PRE_RATIO		0x0
+#define MMC3_RATIO		0xF
+#define MMC3_PRE_RATIO		0x0
+#define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
+				| (MMC3_RATIO << 16) \
+				| (MMC2_PRE_RATIO << 8) \
+				| (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO		0xF
+#define MMC4_PRE_RATIO		0x0
+#define CLK_DIV_FSYS3_VAL	((MMC4_PRE_RATIO << 8) \
+				| (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI		0
+#define UART_SEL_XUSBXTI	1
+#define UART_SEL_SCLK_HDMI24M	2
+#define UART_SEL_SCLK_USBPHY0	3
+#define UART_SEL_SCLK_USBPHY1	4
+#define UART_SEL_SCLK_HDMIPHY	5
+#define UART_SEL_SCLKMPLL	6
+#define UART_SEL_SCLKEPLL	7
+#define UART_SEL_SCLKVPLL	8
+
+#define UART0_SEL		UART_SEL_SCLKMPLL
+#define UART1_SEL		UART_SEL_SCLKMPLL
+#define UART2_SEL		UART_SEL_SCLKMPLL
+#define UART3_SEL		UART_SEL_SCLKMPLL
+#define UART4_SEL		UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL	((UART4_SEL << 16) \
+				| (UART3_SEL << 12) \
+				| (UART2_SEL << 8) \
+				| (UART1_SEL << 4) \
+				| (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO		7
+#define UART1_RATIO		7
+#define UART2_RATIO		7
+#define UART3_RATIO		7
+#define UART4_RATIO		7
+#define CLK_DIV_PERIL0_VAL	((UART4_RATIO << 16) \
+				| (UART3_RATIO << 12) \
+				| (UART2_RATIO << 8) \
+				| (UART1_RATIO << 4) \
+				| (UART0_RATIO << 0))
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME		0x1C20
+
+/* PLL Values */
+#define DISABLE			0
+#define ENABLE			1
+#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
+					| (mdiv << 16) \
+					| (pdiv << 8) \
+					| (sdiv << 0))
+
+/* APLL_CON0 */
+#define APLL_MDIV		0xFA
+#define APLL_PDIV		0x6
+#define APLL_SDIV		0x1
+#define APLL_CON0_VAL		SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB		0x1
+#define APLL_AFC		0xC
+#define APLL_CON1_VAL		((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0 */
+#define MPLL_MDIV		0xC8
+#define MPLL_PDIV		0x6
+#define MPLL_SDIV		0x1
+#define MPLL_CON0_VAL		SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB		0x0
+#define MPLL_AFC		0x1C
+#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0 */
+#define EPLL_MDIV		0x30
+#define EPLL_PDIV		0x3
+#define EPLL_SDIV		0x2
+#define EPLL_CON0_VAL		SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K			0x0
+#define EPLL_CON1_VAL		(EPLL_K >> 0)
+
+/* VPLL_CON0 */
+#define VPLL_MDIV		0x35
+#define VPLL_PDIV		0x3
+#define VPLL_SDIV		0x2
+#define VPLL_CON0_VAL		SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN		DISABLE
+#define VPLL_SEL_PF_DN_SPREAD	0x0
+#define VPLL_MRR		0x11
+#define VPLL_MFR		0x0
+#define VPLL_K			0x400
+#define VPLL_CON1_VAL		((VPLL_SSCG_EN << 31)\
+				| (VPLL_SEL_PF_DN_SPREAD << 29) \
+				| (VPLL_MRR << 24) \
+				| (VPLL_MFR << 16) \
+				| (VPLL_K << 0))
+/*
+ * UART GPIO_A0/GPIO_A1 Control Register Value
+ * 0x2: UART Function
+ */
+#define S5PC210_GPIO_A0_CON_VAL	0x22222222
+#define S5PC210_GPIO_A1_CON_VAL	0x222222
+
+/* ULCON: UART Line Control Value 8N1 */
+#define WORD_LEN_5_BIT		0x00
+#define WORD_LEN_6_BIT		0x01
+#define WORD_LEN_7_BIT		0x02
+#define WORD_LEN_8_BIT		0x03
+
+#define STOP_BIT_1		0x00
+#define STOP_BIT_2		0x01
+
+#define NO_PARITY			0x00
+#define ODD_PARITY			0x4
+#define EVEN_PARITY			0x5
+#define FORCED_PARITY_CHECK_AS_1	0x6
+#define FORCED_PARITY_CHECK_AS_0	0x7
+
+#define INFRAMODE_NORMAL		0x00
+#define INFRAMODE_INFRARED		0x01
+
+#define ULCON_VAL		((INFRAMODE_NORMAL << 6) \
+				| (NO_PARITY << 3) \
+				| (STOP_BIT_1 << 2) \
+				| (WORD_LEN_8_BIT << 0))
+
+/*
+ * UCON: UART Control Value
+ * Tx_interrupt Type: Level
+ * Rx_interrupt Type: Level
+ * Rx Timeout Enabled: Yes
+ * Rx-Error Atatus_Int Enable: Yes
+ * Loop_Back: No
+ * Break Signal: No
+ * Transmit mode : Interrupt request/polling
+ * Receive mode : Interrupt request/polling
+ */
+#define TX_PULSE_INTERRUPT	0
+#define TX_LEVEL_INTERRUPT	1
+#define RX_PULSE_INTERRUPT	0
+#define RX_LEVEL_INTERRUPT	1
+
+#define RX_TIME_OUT		ENABLE
+#define RX_ERROR_STATE_INT_ENB	ENABLE
+#define LOOP_BACK		DISABLE
+#define BREAK_SIGNAL		DISABLE
+
+#define TX_MODE_DISABLED	0X00
+#define TX_MODE_IRQ_OR_POLL	0X01
+#define TX_MODE_DMA		0X02
+
+#define RX_MODE_DISABLED	0X00
+#define RX_MODE_IRQ_OR_POLL	0X01
+#define RX_MODE_DMA		0X02
+
+#define UCON_VAL		((TX_LEVEL_INTERRUPT << 9) \
+				| (RX_LEVEL_INTERRUPT << 8) \
+				| (RX_TIME_OUT << 7) \
+				| (RX_ERROR_STATE_INT_ENB << 6) \
+				| (LOOP_BACK << 5) \
+				| (BREAK_SIGNAL << 4) \
+				| (TX_MODE_IRQ_OR_POLL << 2) \
+				| (RX_MODE_IRQ_OR_POLL << 0))
+
+/*
+ * UFCON: UART FIFO Control Value
+ * Tx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Rx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Tx Fifo Reset: No
+ * Rx Fifo Reset: No
+ * FIFO Enable: Yes
+ */
+#define TX_FIFO_TRIGGER_LEVEL_0_BYTES	0x00
+#define TX_FIFO_TRIGGER_LEVEL_2_BYTES	0x1
+#define TX_FIFO_TRIGGER_LEVEL_4_BYTES	0x2
+#define TX_FIFO_TRIGGER_LEVEL_6_BYTES	0x3
+#define TX_FIFO_TRIGGER_LEVEL_8_BYTES	0x4
+#define TX_FIFO_TRIGGER_LEVEL_10_BYTES	0x5
+#define TX_FIFO_TRIGGER_LEVEL_12_BYTES	0x6
+#define TX_FIFO_TRIGGER_LEVEL_14_BYTES	0x7
+
+#define RX_FIFO_TRIGGER_LEVEL_2_BYTES	0x0
+#define RX_FIFO_TRIGGER_LEVEL_4_BYTES	0x1
+#define RX_FIFO_TRIGGER_LEVEL_6_BYTES	0x2
+#define RX_FIFO_TRIGGER_LEVEL_8_BYTES	0x3
+#define RX_FIFO_TRIGGER_LEVEL_10_BYTES	0x4
+#define RX_FIFO_TRIGGER_LEVEL_12_BYTES	0x5
+#define RX_FIFO_TRIGGER_LEVEL_14_BYTES	0x6
+#define RX_FIFO_TRIGGER_LEVEL_16_BYTES	0x7
+
+#define TX_FIFO_TRIGGER_LEVEL		TX_FIFO_TRIGGER_LEVEL_2_BYTES
+#define RX_FIFO_TRIGGER_LEVEL		RX_FIFO_TRIGGER_LEVEL_4_BYTES
+#define TX_FIFO_RESET			DISABLE
+#define RX_FIFO_RESET			DISABLE
+#define FIFO_ENABLE			ENABLE
+#define UFCON_VAL			((TX_FIFO_TRIGGER_LEVEL << 8) \
+					| (RX_FIFO_TRIGGER_LEVEL << 4) \
+					| (TX_FIFO_RESET << 2) \
+					| (RX_FIFO_RESET << 1) \
+					| (FIFO_ENABLE << 0))
+/*
+ * Baud Rate Division Value
+ * 115200 BAUD:
+ * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
+ * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
+ */
+#define UBRDIV_VAL		0x35
+
+/*
+ * Fractional Part of Baud Rate Divisor:
+ * 115200 BAUD:
+ * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
+ * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
+ */
+#define UFRACVAL_VAL		0x4
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+#endif
@@ -186,6 +186,7 @@
 omap4_sdp4430                arm         armv7       sdp4430             ti             omap4
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
+origen			     arm	 armv7	     origen		 samsung	s5pc2xx
 s5pc210_universal            arm         armv7       universal_c210      samsung        s5pc2xx
 smdkv310		     arm	 armv7	     smdkv310		 samsung	s5pc2xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG ORIGEN (S5PV310) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			1	/* SAMSUNG core */
+#define CONFIG_S5P			1	/* S5P Family */
+#define CONFIG_S5PC210			1	/* which is in a S5PC210 SoC */
+#define CONFIG_ORIGEN			1	/* working with ORIGEN*/
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF			1
+#define CONFIG_SYS_DCACHE_OFF		1
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: ORIGEN has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */
+#define MACH_TYPE_ORIGEN		3455
+#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_SERIAL2			1	/* use SERIAL 2 */
+#define CONFIG_BAUDRATE			115200
+#define S5PC210_DEFAULT_UART_OFFSET	0x020000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_S5P_MMC			1
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
+
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	4
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH		1
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for ORIGEN"
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
+
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+#endif	/* __CONFIG_H */
...	...	@@ -707,6 +707,7 @@
707	707
708	708	Chander Kashyap <k.chander@samsung.com>
709	709
	710	+ origen ARM ARMV7 (S5PC210 SoC)
710	711	SMDKV310 ARM ARMV7 (S5PC210 SoC)
711	712
712	713	Torsten Koschorrek <koschorrek@synertronixx.de>
	1	+#
	2	+# Copyright (C) 2011 Samsung Electronics
	3	+#
	4	+# See file CREDITS for list of people who contributed to this
	5	+# project.
	6	+#
	7	+# This program is free software; you can redistribute it and/or
	8	+# modify it under the terms of the GNU General Public License as
	9	+# published by the Free Software Foundation; either version 2 of
	10	+# the License, or (at your option) any later version.
	11	+#
	12	+# This program is distributed in the hope that it will be useful,
	13	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+# GNU General Public License for more details.
	16	+#
	17	+# You should have received a copy of the GNU General Public License
	18	+# along with this program; if not, write to the Free Software
	19	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+# MA 02111-1307 USA
	21	+#
	22	+
	23	+include $(TOPDIR)/config.mk
	24	+
	25	+LIB = $(obj)lib$(BOARD).o
	26	+
	27	+SOBJS := mem_setup.o
	28	+SOBJS += lowlevel_init.o
	29	+COBJS += origen.o
	30	+
	31	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	32	+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
	33	+
	34	+all: $(obj).depend $(LIB)
	35	+
	36	+$(LIB): $(OBJS)
	37	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	38	+
	39	+#########################################################################
	40	+
	41	+# defines $(obj).depend target
	42	+include $(SRCTREE)/rules.mk
	43	+
	44	+sinclude $(obj).depend
	45	+
	46	+#########################################################################
	1	+/*
	2	+ * Lowlevel setup for ORIGEN board based on S5PV310
	3	+ *
	4	+ * Copyright (C) 2011 Samsung Electronics
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <config.h>
	26	+#include <version.h>
	27	+#include <asm/arch/cpu.h>
	28	+#include "origen_setup.h"
	29	+/*
	30	+ * Register usages:
	31	+ *
	32	+ * r5 has zero always
	33	+ * r7 has GPIO part1 base 0x11400000
	34	+ * r6 has GPIO part2 base 0x11000000
	35	+ */
	36	+
	37	+_TEXT_BASE:
	38	+ .word CONFIG_SYS_TEXT_BASE
	39	+
	40	+ .globl lowlevel_init
	41	+lowlevel_init:
	42	+ push {lr}
	43	+
	44	+ /* r5 has always zero */
	45	+ mov r5, #0
	46	+ ldr r7, =S5PC210_GPIO_PART1_BASE
	47	+ ldr r6, =S5PC210_GPIO_PART2_BASE
	48	+
	49	+ /* check reset status */
	50	+ ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
	51	+ ldr r1, [r0]
	52	+
	53	+ /* AFTR wakeup reset */
	54	+ ldr r2, =S5P_CHECK_DIDLE
	55	+ cmp r1, r2
	56	+ beq exit_wakeup
	57	+
	58	+ /* LPA wakeup reset */
	59	+ ldr r2, =S5P_CHECK_LPA
	60	+ cmp r1, r2
	61	+ beq exit_wakeup
	62	+
	63	+ /* Sleep wakeup reset */
	64	+ ldr r2, =S5P_CHECK_SLEEP
	65	+ cmp r1, r2
	66	+ beq wakeup_reset
	67	+
	68	+ /*
	69	+ * If U-boot is already running in ram, no need to relocate U-Boot.
	70	+ * Memory controller must be configured before relocating U-Boot
	71	+ * in ram.
	72	+ */
	73	+ ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
	74	+ bic r1, pc, r0 /* pc <- current addr of code */
	75	+ /* r1 <- unmasked bits of pc */
	76	+ ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
	77	+ bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
	78	+ cmp r1, r2 /* compare r1, r2 */
	79	+ beq 1f /* r0 == r1 then skip sdram init */
	80	+
	81	+ /* init system clock */
	82	+ bl system_clock_init
	83	+
	84	+ /* Memory initialize */
	85	+ bl mem_ctrl_asm_init
	86	+
	87	+1:
	88	+ /* for UART */
	89	+ bl uart_asm_init
	90	+ bl tzpc_init
	91	+ pop {pc}
	92	+
	93	+wakeup_reset:
	94	+ bl system_clock_init
	95	+ bl mem_ctrl_asm_init
	96	+ bl tzpc_init
	97	+
	98	+exit_wakeup:
	99	+ /* Load return address and jump to kernel */
	100	+ ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
	101	+
	102	+ /* r1 = physical address of s5pc210_cpu_resume function */
	103	+ ldr r1, [r0]
	104	+
	105	+ /* Jump to kernel*/
	106	+ mov pc, r1
	107	+ nop
	108	+ nop
	109	+
	110	+/*
	111	+ * system_clock_init: Initialize core clock and bus clock.
	112	+ * void system_clock_init(void)
	113	+ */
	114	+system_clock_init:
	115	+ push {lr}
	116	+ ldr r0, =S5PC210_CLOCK_BASE
	117	+
	118	+ /* APLL(1), MPLL(1), CORE(0), HPM(0) */
	119	+ ldr r1, =CLK_SRC_CPU_VAL
	120	+ ldr r2, =CLK_SRC_CPU_OFFSET
	121	+ str r1, [r0, r2]
	122	+
	123	+ /* wait ?us */
	124	+ mov r1, #0x10000
	125	+2: subs r1, r1, #1
	126	+ bne 2b
	127	+
	128	+ ldr r1, =CLK_SRC_TOP0_VAL
	129	+ ldr r2, =CLK_SRC_TOP0_OFFSET
	130	+ str r1, [r0, r2]
	131	+
	132	+ ldr r1, =CLK_SRC_TOP1_VAL
	133	+ ldr r2, =CLK_SRC_TOP1_OFFSET
	134	+ str r1, [r0, r2]
	135	+
	136	+ /* DMC */
	137	+ ldr r1, =CLK_SRC_DMC_VAL
	138	+ ldr r2, =CLK_SRC_DMC_OFFSET
	139	+ str r1, [r0, r2]
	140	+
	141	+ /CLK_SRC_LEFTBUS /
	142	+ ldr r1, =CLK_SRC_LEFTBUS_VAL
	143	+ ldr r2, =CLK_SRC_LEFTBUS_OFFSET
	144	+ str r1, [r0, r2]
	145	+
	146	+ /CLK_SRC_RIGHTBUS /
	147	+ ldr r1, =CLK_SRC_RIGHTBUS_VAL
	148	+ ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
	149	+ str r1, [r0, r2]
	150	+
	151	+ /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
	152	+ ldr r1, =CLK_SRC_FSYS_VAL
	153	+ ldr r2, =CLK_SRC_FSYS_OFFSET
	154	+ str r1, [r0, r2]
	155	+
	156	+ /* UART[0:4] */
	157	+ ldr r1, =CLK_SRC_PERIL0_VAL
	158	+ ldr r2, =CLK_SRC_PERIL0_OFFSET
	159	+ str r1, [r0, r2]
	160	+
	161	+ /* wait ?us */
	162	+ mov r1, #0x10000
	163	+3: subs r1, r1, #1
	164	+ bne 3b
	165	+
	166	+ /* CLK_DIV_CPU0 */
	167	+ ldr r1, =CLK_DIV_CPU0_VAL
	168	+ ldr r2, =CLK_DIV_CPU0_OFFSET
	169	+ str r1, [r0, r2]
	170	+
	171	+ /* CLK_DIV_CPU1 */
	172	+ ldr r1, =CLK_DIV_CPU1_VAL
	173	+ ldr r2, =CLK_DIV_CPU1_OFFSET
	174	+ str r1, [r0, r2]
	175	+
	176	+ /* CLK_DIV_DMC0 */
	177	+ ldr r1, =CLK_DIV_DMC0_VAL
	178	+ ldr r2, =CLK_DIV_DMC0_OFFSET
	179	+ str r1, [r0, r2]
	180	+
	181	+ /CLK_DIV_DMC1 /
	182	+ ldr r1, =CLK_DIV_DMC1_VAL
	183	+ ldr r2, =CLK_DIV_DMC1_OFFSET
	184	+ str r1, [r0, r2]
	185	+
	186	+ /* CLK_DIV_LEFTBUS */
	187	+ ldr r1, =CLK_DIV_LEFTBUS_VAL
	188	+ ldr r2, =CLK_DIV_LEFTBUS_OFFSET
	189	+ str r1, [r0, r2]
	190	+
	191	+ /* CLK_DIV_RIGHTBUS */
	192	+ ldr r1, =CLK_DIV_RIGHTBUS_VAL
	193	+ ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
	194	+ str r1, [r0, r2]
	195	+
	196	+ /* CLK_DIV_TOP */
	197	+ ldr r1, =CLK_DIV_TOP_VAL
	198	+ ldr r2, =CLK_DIV_TOP_OFFSET
	199	+ str r1, [r0, r2]
	200	+
	201	+ /* MMC[0:1] */
	202	+ ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
	203	+ ldr r2, =CLK_DIV_FSYS1_OFFSET
	204	+ str r1, [r0, r2]
	205	+
	206	+ /* MMC[2:3] */
	207	+ ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
	208	+ ldr r2, =CLK_DIV_FSYS2_OFFSET
	209	+ str r1, [r0, r2]
	210	+
	211	+ /* MMC4 */
	212	+ ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
	213	+ ldr r2, =CLK_DIV_FSYS3_OFFSET
	214	+ str r1, [r0, r2]
	215	+
	216	+ /* CLK_DIV_PERIL0: UART Clock Divisors */
	217	+ ldr r1, =CLK_DIV_PERIL0_VAL
	218	+ ldr r2, =CLK_DIV_PERIL0_OFFSET
	219	+ str r1, [r0, r2]
	220	+
	221	+ /* Set PLL locktime */
	222	+ ldr r1, =PLL_LOCKTIME
	223	+ ldr r2, =APLL_LOCK_OFFSET
	224	+ str r1, [r0, r2]
	225	+
	226	+ ldr r1, =PLL_LOCKTIME
	227	+ ldr r2, =MPLL_LOCK_OFFSET
	228	+ str r1, [r0, r2]
	229	+
	230	+ ldr r1, =PLL_LOCKTIME
	231	+ ldr r2, =EPLL_LOCK_OFFSET
	232	+ str r1, [r0, r2]
	233	+
	234	+ ldr r1, =PLL_LOCKTIME
	235	+ ldr r2, =VPLL_LOCK_OFFSET
	236	+ str r1, [r0, r2]
	237	+
	238	+ /* APLL_CON1 */
	239	+ ldr r1, =APLL_CON1_VAL
	240	+ ldr r2, =APLL_CON1_OFFSET
	241	+ str r1, [r0, r2]
	242	+
	243	+ /* APLL_CON0 */
	244	+ ldr r1, =APLL_CON0_VAL
	245	+ ldr r2, =APLL_CON0_OFFSET
	246	+ str r1, [r0, r2]
	247	+
	248	+ /* MPLL_CON1 */
	249	+ ldr r1, =MPLL_CON1_VAL
	250	+ ldr r2, =MPLL_CON1_OFFSET
	251	+ str r1, [r0, r2]
	252	+
	253	+ /* MPLL_CON0 */
	254	+ ldr r1, =MPLL_CON0_VAL
	255	+ ldr r2, =MPLL_CON0_OFFSET
	256	+ str r1, [r0, r2]
	257	+
	258	+ /* EPLL */
	259	+ ldr r1, =EPLL_CON1_VAL
	260	+ ldr r2, =EPLL_CON1_OFFSET
	261	+ str r1, [r0, r2]
	262	+
	263	+ /* EPLL_CON0 */
	264	+ ldr r1, =EPLL_CON0_VAL
	265	+ ldr r2, =EPLL_CON0_OFFSET
	266	+ str r1, [r0, r2]
	267	+
	268	+ /* VPLL_CON1 */
	269	+ ldr r1, =VPLL_CON1_VAL
	270	+ ldr r2, =VPLL_CON1_OFFSET
	271	+ str r1, [r0, r2]
	272	+
	273	+ /* VPLL_CON0 */
	274	+ ldr r1, =VPLL_CON0_VAL
	275	+ ldr r2, =VPLL_CON0_OFFSET
	276	+ str r1, [r0, r2]
	277	+
	278	+ /* wait ?us */
	279	+ mov r1, #0x30000
	280	+4: subs r1, r1, #1
	281	+ bne 4b
	282	+
	283	+ pop {pc}
	284	+/*
	285	+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
	286	+ * void uart_asm_init(void)
	287	+ */
	288	+ .globl uart_asm_init
	289	+uart_asm_init:
	290	+
	291	+ /* setup UART0-UART3 GPIOs (part1) */
	292	+ mov r0, r7
	293	+ ldr r1, =S5PC210_GPIO_A0_CON_VAL
	294	+ str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
	295	+ ldr r1, =S5PC210_GPIO_A1_CON_VAL
	296	+ str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
	297	+
	298	+ ldr r0, =S5PC210_UART_BASE
	299	+ add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
	300	+
	301	+ ldr r1, =ULCON_VAL
	302	+ str r1, [r0, #ULCON_OFFSET]
	303	+ ldr r1, =UCON_VAL
	304	+ str r1, [r0, #UCON_OFFSET]
	305	+ ldr r1, =UFCON_VAL
	306	+ str r1, [r0, #UFCON_OFFSET]
	307	+ ldr r1, =UBRDIV_VAL
	308	+ str r1, [r0, #UBRDIV_OFFSET]
	309	+ ldr r1, =UFRACVAL_VAL
	310	+ str r1, [r0, #UFRACVAL_OFFSET]
	311	+ mov pc, lr
	312	+ nop
	313	+ nop
	314	+ nop
	315	+
	316	+/* Setting TZPC[TrustZone Protection Controller] */
	317	+tzpc_init:
	318	+ ldr r0, =TZPC0_BASE
	319	+ mov r1, #R0SIZE
	320	+ str r1, [r0]
	321	+ mov r1, #DECPROTXSET
	322	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	323	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	324	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	325	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	326	+
	327	+ ldr r0, =TZPC1_BASE
	328	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	329	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	330	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	331	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	332	+
	333	+ ldr r0, =TZPC2_BASE
	334	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	335	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	336	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	337	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	338	+
	339	+ ldr r0, =TZPC3_BASE
	340	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	341	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	342	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	343	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	344	+
	345	+ ldr r0, =TZPC4_BASE
	346	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	347	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	348	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	349	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	350	+
	351	+ ldr r0, =TZPC5_BASE
	352	+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
	353	+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
	354	+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
	355	+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
	356	+
	357	+ mov pc, lr
	1	+/*
	2	+ * Memory setup for ORIGEN board based on S5PV310
	3	+ *
	4	+ * Copyright (C) 2011 Samsung Electronics
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <config.h>
	26	+#include "origen_setup.h"
	27	+#define SET_MIU
	28	+
	29	+ .globl mem_ctrl_asm_init
	30	+mem_ctrl_asm_init:
	31	+ /*
	32	+ * Async bridge configuration at CPU_core:
	33	+ * 1: half_sync
	34	+ * 0: full_sync
	35	+ */
	36	+ ldr r0, =ASYNC_CONFIG
	37	+ mov r1, #1
	38	+ str r1, [r0]
	39	+
	40	+#ifdef SET_MIU
	41	+ ldr r0, =S5PC210_MIU_BASE
	42	+ /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
	43	+ ldr r1, =0x20001507
	44	+ str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
	45	+
	46	+ /* Update MIU Configuration */
	47	+ ldr r1, =0x00000001
	48	+ str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
	49	+#endif
	50	+ /* DREX0 */
	51	+ ldr r0, =S5PC210_DMC0_BASE
	52	+
	53	+ /*
	54	+ * DLL Parameter Setting:
	55	+ * Termination: Enable R/W
	56	+ * Phase Delay for DQS Cleaning: 180' Shift
	57	+ */
	58	+ ldr r1, =0xe0000086
	59	+ str r1, [r0, #DMC_PHYCONTROL1]
	60	+
	61	+ /*
	62	+ * ZQ Calibration
	63	+ * Termination: Disable
	64	+ * Auto Calibration Start: Enable
	65	+ */
	66	+ ldr r1, =0xE3855703
	67	+ str r1, [r0, #DMC_PHYZQCONTROL]
	68	+
	69	+ /* Wait ?us*/
	70	+ mov r2, #0x100000
	71	+1: subs r2, r2, #1
	72	+ bne 1b
	73	+
	74	+ /*
	75	+ * Update DLL Information:
	76	+ * Force DLL Resyncronization
	77	+ */
	78	+ ldr r1, =0xe000008e
	79	+ str r1, [r0, #DMC_PHYCONTROL1]
	80	+
	81	+ /* Reset Force DLL Resyncronization */
	82	+ ldr r1, =0xe0000086
	83	+ str r1, [r0, #DMC_PHYCONTROL1]
	84	+
	85	+ /* Enable Differential DQS, DLL Off*/
	86	+ ldr r1, =0x71101008
	87	+ str r1, [r0, #DMC_PHYCONTROL0]
	88	+
	89	+ /* Activate PHY DLL: DLL On */
	90	+ ldr r1, =0x7110100A
	91	+ str r1, [r0, #DMC_PHYCONTROL0]
	92	+
	93	+ /* Set DLL Parameters */
	94	+ ldr r1, =0xe0000086
	95	+ str r1, [r0, #DMC_PHYCONTROL1]
	96	+
	97	+ /* DLL Start */
	98	+ ldr r1, =0x7110100B
	99	+ str r1, [r0, #DMC_PHYCONTROL0]
	100	+
	101	+ ldr r1, =0x00000000
	102	+ str r1, [r0, #DMC_PHYCONTROL2]
	103	+
	104	+ /* Set Clock Ratio of Bus clock to Memory Clock */
	105	+ ldr r1, =0x0FFF301a
	106	+ str r1, [r0, #DMC_CONCONTROL]
	107	+
	108	+ /*
	109	+ * Memor Burst length: 8
	110	+ * Number of chips: 2
	111	+ * Memory Bus width: 32 bit
	112	+ * Memory Type: DDR3
	113	+ * Additional Latancy for PLL: 1 Cycle
	114	+ */
	115	+ ldr r1, =0x00312640
	116	+ str r1, [r0, #DMC_MEMCONTROL]
	117	+
	118	+ /*
	119	+ * Memory Configuration Chip 0
	120	+ * Address Mapping: Interleaved
	121	+ * Number of Column address Bits: 10 bits
	122	+ * Number of Rows Address Bits: 14
	123	+ * Number of Banks: 8
	124	+ */
	125	+ ldr r1, =0x20e01323
	126	+ str r1, [r0, #DMC_MEMCONFIG0]
	127	+
	128	+ /*
	129	+ * Memory Configuration Chip 1
	130	+ * Address Mapping: Interleaved
	131	+ * Number of Column address Bits: 10 bits
	132	+ * Number of Rows Address Bits: 14
	133	+ * Number of Banks: 8
	134	+ */
	135	+ ldr r1, =0x40e01323
	136	+ str r1, [r0, #DMC_MEMCONFIG1]
	137	+
	138	+ /* Config Precharge Policy */
	139	+ ldr r1, =0xff000000
	140	+ str r1, [r0, #DMC_PRECHCONFIG]
	141	+
	142	+ /*
	143	+ * TimingAref, TimingRow, TimingData, TimingPower Setting:
	144	+ * Values as per Memory AC Parameters
	145	+ */
	146	+ ldr r1, =0x000000BB
	147	+ str r1, [r0, #DMC_TIMINGAREF]
	148	+ ldr r1, =0x4046654f
	149	+ str r1, [r0, #DMC_TIMINGROW]
	150	+ ldr r1, =0x46400506
	151	+ str r1, [r0, #DMC_TIMINGDATA]
	152	+ ldr r1, =0x52000A3C
	153	+ str r1, [r0, #DMC_TIMINGPOWER]
	154	+
	155	+ /* Chip0: NOP Command: Assert and Hold CKE to high level */
	156	+ ldr r1, =0x07000000
	157	+ str r1, [r0, #DMC_DIRECTCMD]
	158	+
	159	+ /* Wait ?us*/
	160	+ mov r2, #0x100000
	161	+2: subs r2, r2, #1
	162	+ bne 2b
	163	+
	164	+ /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	165	+ ldr r1, =0x00020000
	166	+ str r1, [r0, #DMC_DIRECTCMD]
	167	+ ldr r1, =0x00030000
	168	+ str r1, [r0, #DMC_DIRECTCMD]
	169	+ ldr r1, =0x00010002
	170	+ str r1, [r0, #DMC_DIRECTCMD]
	171	+ ldr r1, =0x00000328
	172	+ str r1, [r0, #DMC_DIRECTCMD]
	173	+
	174	+ /* Wait ?us*/
	175	+ mov r2, #0x100000
	176	+3: subs r2, r2, #1
	177	+ bne 3b
	178	+
	179	+ /* Chip0: ZQINIT */
	180	+ ldr r1, =0x0a000000
	181	+ str r1, [r0, #DMC_DIRECTCMD]
	182	+
	183	+ /* Wait ?us*/
	184	+ mov r2, #0x100000
	185	+4: subs r2, r2, #1
	186	+ bne 4b
	187	+
	188	+ /* Chip1: NOP Command: Assert and Hold CKE to high level */
	189	+ ldr r1, =0x07100000
	190	+ str r1, [r0, #DMC_DIRECTCMD]
	191	+
	192	+ /* Wait ?us*/
	193	+ mov r2, #0x100000
	194	+5: subs r2, r2, #1
	195	+ bne 5b
	196	+
	197	+ /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	198	+ ldr r1, =0x00120000
	199	+ str r1, [r0, #DMC_DIRECTCMD]
	200	+ ldr r1, =0x00130000
	201	+ str r1, [r0, #DMC_DIRECTCMD]
	202	+ ldr r1, =0x00110002
	203	+ str r1, [r0, #DMC_DIRECTCMD]
	204	+ ldr r1, =0x00100328
	205	+ str r1, [r0, #DMC_DIRECTCMD]
	206	+
	207	+ /* Wait ?us*/
	208	+ mov r2, #0x100000
	209	+6: subs r2, r2, #1
	210	+ bne 6b
	211	+
	212	+ /* Chip1: ZQINIT */
	213	+ ldr r1, =0x0a100000
	214	+ str r1, [r0, #DMC_DIRECTCMD]
	215	+
	216	+ /* Wait ?us*/
	217	+ mov r2, #0x100000
	218	+7: subs r2, r2, #1
	219	+ bne 7b
	220	+
	221	+ ldr r1, =0xe000008e
	222	+ str r1, [r0, #DMC_PHYCONTROL1]
	223	+ ldr r1, =0xe0000086
	224	+ str r1, [r0, #DMC_PHYCONTROL1]
	225	+
	226	+ /* Wait ?us*/
	227	+ mov r2, #0x100000
	228	+8: subs r2, r2, #1
	229	+ bne 8b
	230	+
	231	+ /* DREX1 */
	232	+ ldr r0, =S5PC210_DMC1_BASE @0x10410000
	233	+
	234	+ /*
	235	+ * DLL Parameter Setting:
	236	+ * Termination: Enable R/W
	237	+ * Phase Delay for DQS Cleaning: 180' Shift
	238	+ */
	239	+ ldr r1, =0xe0000086
	240	+ str r1, [r0, #DMC_PHYCONTROL1]
	241	+
	242	+ /*
	243	+ * ZQ Calibration:
	244	+ * Termination: Disable
	245	+ * Auto Calibration Start: Enable
	246	+ */
	247	+ ldr r1, =0xE3855703
	248	+ str r1, [r0, #DMC_PHYZQCONTROL]
	249	+
	250	+ /* Wait ?us*/
	251	+ mov r2, #0x100000
	252	+1: subs r2, r2, #1
	253	+ bne 1b
	254	+
	255	+ /*
	256	+ * Update DLL Information:
	257	+ * Force DLL Resyncronization
	258	+ */
	259	+ ldr r1, =0xe000008e
	260	+ str r1, [r0, #DMC_PHYCONTROL1]
	261	+
	262	+ /* Reset Force DLL Resyncronization */
	263	+ ldr r1, =0xe0000086
	264	+ str r1, [r0, #DMC_PHYCONTROL1]
	265	+
	266	+ /* Enable Differential DQS, DLL Off*/
	267	+ ldr r1, =0x71101008
	268	+ str r1, [r0, #DMC_PHYCONTROL0]
	269	+
	270	+ /* Activate PHY DLL: DLL On */
	271	+ ldr r1, =0x7110100A
	272	+ str r1, [r0, #DMC_PHYCONTROL0]
	273	+
	274	+ /* Set DLL Parameters */
	275	+ ldr r1, =0xe0000086
	276	+ str r1, [r0, #DMC_PHYCONTROL1]
	277	+
	278	+ /* DLL Start */
	279	+ ldr r1, =0x7110100B
	280	+ str r1, [r0, #DMC_PHYCONTROL0]
	281	+
	282	+ ldr r1, =0x00000000
	283	+ str r1, [r0, #DMC_PHYCONTROL2]
	284	+
	285	+ /* Set Clock Ratio of Bus clock to Memory Clock */
	286	+ ldr r1, =0x0FFF301a
	287	+ str r1, [r0, #DMC_CONCONTROL]
	288	+
	289	+ /*
	290	+ * Memor Burst length: 8
	291	+ * Number of chips: 2
	292	+ * Memory Bus width: 32 bit
	293	+ * Memory Type: DDR3
	294	+ * Additional Latancy for PLL: 1 Cycle
	295	+ */
	296	+ ldr r1, =0x00312640
	297	+ str r1, [r0, #DMC_MEMCONTROL]
	298	+
	299	+ /*
	300	+ * Memory Configuration Chip 0
	301	+ * Address Mapping: Interleaved
	302	+ * Number of Column address Bits: 10 bits
	303	+ * Number of Rows Address Bits: 14
	304	+ * Number of Banks: 8
	305	+ */
	306	+ ldr r1, =0x20e01323
	307	+ str r1, [r0, #DMC_MEMCONFIG0]
	308	+
	309	+ /*
	310	+ * Memory Configuration Chip 1
	311	+ * Address Mapping: Interleaved
	312	+ * Number of Column address Bits: 10 bits
	313	+ * Number of Rows Address Bits: 14
	314	+ * Number of Banks: 8
	315	+ */
	316	+ ldr r1, =0x40e01323
	317	+ str r1, [r0, #DMC_MEMCONFIG1]
	318	+
	319	+ /* Config Precharge Policy */
	320	+ ldr r1, =0xff000000
	321	+ str r1, [r0, #DMC_PRECHCONFIG]
	322	+
	323	+ /*
	324	+ * TimingAref, TimingRow, TimingData, TimingPower Setting:
	325	+ * Values as per Memory AC Parameters
	326	+ */
	327	+ ldr r1, =0x000000BB
	328	+ str r1, [r0, #DMC_TIMINGAREF]
	329	+ ldr r1, =0x4046654f
	330	+ str r1, [r0, #DMC_TIMINGROW]
	331	+ ldr r1, =0x46400506
	332	+ str r1, [r0, #DMC_TIMINGDATA]
	333	+ ldr r1, =0x52000A3C
	334	+ str r1, [r0, #DMC_TIMINGPOWER]
	335	+
	336	+ /* Chip0: NOP Command: Assert and Hold CKE to high level */
	337	+ ldr r1, =0x07000000
	338	+ str r1, [r0, #DMC_DIRECTCMD]
	339	+
	340	+ /* Wait ?us*/
	341	+ mov r2, #0x100000
	342	+2: subs r2, r2, #1
	343	+ bne 2b
	344	+
	345	+ /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	346	+ ldr r1, =0x00020000
	347	+ str r1, [r0, #DMC_DIRECTCMD]
	348	+ ldr r1, =0x00030000
	349	+ str r1, [r0, #DMC_DIRECTCMD]
	350	+ ldr r1, =0x00010002
	351	+ str r1, [r0, #DMC_DIRECTCMD]
	352	+ ldr r1, =0x00000328
	353	+ str r1, [r0, #DMC_DIRECTCMD]
	354	+
	355	+ /* Wait ?us*/
	356	+ mov r2, #0x100000
	357	+3: subs r2, r2, #1
	358	+ bne 3b
	359	+
	360	+ /* Chip 0: ZQINIT */
	361	+ ldr r1, =0x0a000000
	362	+ str r1, [r0, #DMC_DIRECTCMD]
	363	+
	364	+ /* Wait ?us*/
	365	+ mov r2, #0x100000
	366	+4: subs r2, r2, #1
	367	+ bne 4b
	368	+
	369	+ /* Chip1: NOP Command: Assert and Hold CKE to high level */
	370	+ ldr r1, =0x07100000
	371	+ str r1, [r0, #DMC_DIRECTCMD]
	372	+
	373	+ /* Wait ?us*/
	374	+ mov r2, #0x100000
	375	+5: subs r2, r2, #1
	376	+ bne 5b
	377	+
	378	+ /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	379	+ ldr r1, =0x00120000
	380	+ str r1, [r0, #DMC_DIRECTCMD]
	381	+ ldr r1, =0x00130000
	382	+ str r1, [r0, #DMC_DIRECTCMD]
	383	+ ldr r1, =0x00110002
	384	+ str r1, [r0, #DMC_DIRECTCMD]
	385	+ ldr r1, =0x00100328
	386	+ str r1, [r0, #DMC_DIRECTCMD]
	387	+
	388	+ /* Wait ?us*/
	389	+ mov r2, #0x100000
	390	+6: subs r2, r2, #1
	391	+ bne 6b
	392	+
	393	+ /* Chip1: ZQINIT */
	394	+ ldr r1, =0x0a100000
	395	+ str r1, [r0, #DMC_DIRECTCMD]
	396	+
	397	+ /* Wait ?us*/
	398	+ mov r2, #0x100000
	399	+7: subs r2, r2, #1
	400	+ bne 7b
	401	+
	402	+ ldr r1, =0xe000008e
	403	+ str r1, [r0, #DMC_PHYCONTROL1]
	404	+ ldr r1, =0xe0000086
	405	+ str r1, [r0, #DMC_PHYCONTROL1]
	406	+
	407	+ /* Wait ?us*/
	408	+ mov r2, #0x100000
	409	+8: subs r2, r2, #1
	410	+ bne 8b
	411	+
	412	+ /* turn on DREX0, DREX1 */
	413	+ ldr r0, =S5PC210_DMC0_BASE
	414	+ ldr r1, =0x0FFF303a
	415	+ str r1, [r0, #DMC_CONCONTROL]
	416	+
	417	+ ldr r0, =S5PC210_DMC1_BASE
	418	+ ldr r1, =0x0FFF303a
	419	+ str r1, [r0, #DMC_CONCONTROL]
	420	+
	421	+ mov pc, lr
	1	+/*
	2	+ * Machine Specific Values for ORIGEN board based on S5PV310
	3	+ *
	4	+ * Copyright (C) 2011 Samsung Electronics
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#ifndef _ORIGEN_SETUP_H
	26	+#define _ORIGEN_SETUP_H
	27	+
	28	+#include <config.h>
	29	+#include <version.h>
	30	+#include <asm/arch/cpu.h>
	31	+
	32	+/* Offsets of clock registers (sources and dividers) */
	33	+#define CLK_SRC_CPU_OFFSET 0x14200
	34	+#define CLK_DIV_CPU0_OFFSET 0x14500
	35	+#define CLK_DIV_CPU1_OFFSET 0x14504
	36	+
	37	+#define CLK_SRC_DMC_OFFSET 0x10200
	38	+#define CLK_DIV_DMC0_OFFSET 0x10500
	39	+#define CLK_DIV_DMC1_OFFSET 0x10504
	40	+
	41	+#define CLK_SRC_TOP0_OFFSET 0xC210
	42	+#define CLK_SRC_TOP1_OFFSET 0xC214
	43	+#define CLK_DIV_TOP_OFFSET 0xC510
	44	+
	45	+#define CLK_SRC_LEFTBUS_OFFSET 0x4200
	46	+#define CLK_DIV_LEFTBUS_OFFSET 0x4500
	47	+
	48	+#define CLK_SRC_RIGHTBUS_OFFSET 0x8200
	49	+#define CLK_DIV_RIGHTBUS_OFFSET 0x8500
	50	+
	51	+#define CLK_SRC_FSYS_OFFSET 0xC240
	52	+#define CLK_DIV_FSYS1_OFFSET 0xC544
	53	+#define CLK_DIV_FSYS2_OFFSET 0xC548
	54	+#define CLK_DIV_FSYS3_OFFSET 0xC54C
	55	+
	56	+#define CLK_SRC_PERIL0_OFFSET 0xC250
	57	+#define CLK_DIV_PERIL0_OFFSET 0xC550
	58	+
	59	+#define APLL_LOCK_OFFSET 0x14000
	60	+#define MPLL_LOCK_OFFSET 0x14008
	61	+#define APLL_CON0_OFFSET 0x14100
	62	+#define APLL_CON1_OFFSET 0x14104
	63	+#define MPLL_CON0_OFFSET 0x14108
	64	+#define MPLL_CON1_OFFSET 0x1410C
	65	+
	66	+#define EPLL_LOCK_OFFSET 0xC010
	67	+#define VPLL_LOCK_OFFSET 0xC020
	68	+#define EPLL_CON0_OFFSET 0xC110
	69	+#define EPLL_CON1_OFFSET 0xC114
	70	+#define VPLL_CON0_OFFSET 0xC120
	71	+#define VPLL_CON1_OFFSET 0xC124
	72	+
	73	+/* DMC: DRAM Controllor Register offsets */
	74	+#define DMC_CONCONTROL 0x00
	75	+#define DMC_MEMCONTROL 0x04
	76	+#define DMC_MEMCONFIG0 0x08
	77	+#define DMC_MEMCONFIG1 0x0C
	78	+#define DMC_DIRECTCMD 0x10
	79	+#define DMC_PRECHCONFIG 0x14
	80	+#define DMC_PHYCONTROL0 0x18
	81	+#define DMC_PHYCONTROL1 0x1C
	82	+#define DMC_PHYCONTROL2 0x20
	83	+#define DMC_TIMINGAREF 0x30
	84	+#define DMC_TIMINGROW 0x34
	85	+#define DMC_TIMINGDATA 0x38
	86	+#define DMC_TIMINGPOWER 0x3C
	87	+#define DMC_PHYZQCONTROL 0x44
	88	+
	89	+/* Bus Configuration Register Address */
	90	+#define ASYNC_CONFIG 0x10010350
	91	+
	92	+/* MIU Config Register Offsets*/
	93	+#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
	94	+#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
	95	+
	96	+/* Offset for inform registers */
	97	+#define INFORM0_OFFSET 0x800
	98	+#define INFORM1_OFFSET 0x804
	99	+
	100	+/* GPIO Offsets for UART: GPIO Contol Register */
	101	+#define S5PC210_GPIO_A0_CON_OFFSET 0x00
	102	+#define S5PC210_GPIO_A1_CON_OFFSET 0x20
	103	+
	104	+/* UART Register offsets */
	105	+#define ULCON_OFFSET 0x00
	106	+#define UCON_OFFSET 0x04
	107	+#define UFCON_OFFSET 0x08
	108	+#define UBRDIV_OFFSET 0x28
	109	+#define UFRACVAL_OFFSET 0x2C
	110	+
	111	+/* TZPC : Register Offsets */
	112	+#define TZPC0_BASE 0x10110000
	113	+#define TZPC1_BASE 0x10120000
	114	+#define TZPC2_BASE 0x10130000
	115	+#define TZPC3_BASE 0x10140000
	116	+#define TZPC4_BASE 0x10150000
	117	+#define TZPC5_BASE 0x10160000
	118	+
	119	+#define TZPC_DECPROT0SET_OFFSET 0x804
	120	+#define TZPC_DECPROT1SET_OFFSET 0x810
	121	+#define TZPC_DECPROT2SET_OFFSET 0x81C
	122	+#define TZPC_DECPROT3SET_OFFSET 0x828
	123	+
	124	+/* CLK_SRC_CPU */
	125	+#define MUX_HPM_SEL_MOUTAPLL 0x0
	126	+#define MUX_HPM_SEL_SCLKMPLL 0x1
	127	+#define MUX_CORE_SEL_MOUTAPLL 0x0
	128	+#define MUX_CORE_SEL_SCLKMPLL 0x1
	129	+#define MUX_MPLL_SEL_FILPLL 0x0
	130	+#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
	131	+#define MUX_APLL_SEL_FILPLL 0x0
	132	+#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
	133	+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
	134	+ \| (MUX_CORE_SEL_MOUTAPLL << 16) \
	135	+ \| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
	136	+ \| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
	137	+
	138	+/* CLK_DIV_CPU0 */
	139	+#define APLL_RATIO 0x0
	140	+#define PCLK_DBG_RATIO 0x1
	141	+#define ATB_RATIO 0x3
	142	+#define PERIPH_RATIO 0x3
	143	+#define COREM1_RATIO 0x7
	144	+#define COREM0_RATIO 0x3
	145	+#define CORE_RATIO 0x0
	146	+#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
	147	+ \| (PCLK_DBG_RATIO << 20) \
	148	+ \| (ATB_RATIO << 16) \
	149	+ \| (PERIPH_RATIO << 12) \
	150	+ \| (COREM1_RATIO << 8) \
	151	+ \| (COREM0_RATIO << 4) \
	152	+ \| (CORE_RATIO << 0))
	153	+
	154	+/* CLK_DIV_CPU1 */
	155	+#define HPM_RATIO 0x0
	156	+#define COPY_RATIO 0x3
	157	+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \| (COPY_RATIO))
	158	+
	159	+/* CLK_SRC_DMC */
	160	+#define MUX_PWI_SEL_XXTI 0x0
	161	+#define MUX_PWI_SEL_XUSBXTI 0x1
	162	+#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
	163	+#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
	164	+#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
	165	+#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
	166	+#define MUX_PWI_SEL_SCLKMPLL 0x6
	167	+#define MUX_PWI_SEL_SCLKEPLL 0x7
	168	+#define MUX_PWI_SEL_SCLKVPLL 0x8
	169	+#define MUX_DPHY_SEL_SCLKMPLL 0x0
	170	+#define MUX_DPHY_SEL_SCLKAPLL 0x1
	171	+#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
	172	+#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
	173	+#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
	174	+ \| (MUX_DPHY_SEL_SCLKMPLL << 8) \
	175	+ \| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
	176	+
	177	+/* CLK_DIV_DMC0 */
	178	+#define CORE_TIMERS_RATIO 0x1
	179	+#define COPY2_RATIO 0x3
	180	+#define DMCP_RATIO 0x1
	181	+#define DMCD_RATIO 0x1
	182	+#define DMC_RATIO 0x1
	183	+#define DPHY_RATIO 0x1
	184	+#define ACP_PCLK_RATIO 0x1
	185	+#define ACP_RATIO 0x3
	186	+#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
	187	+ \| (COPY2_RATIO << 24) \
	188	+ \| (DMCP_RATIO << 20) \
	189	+ \| (DMCD_RATIO << 16) \
	190	+ \| (DMC_RATIO << 12) \
	191	+ \| (DPHY_RATIO << 8) \
	192	+ \| (ACP_PCLK_RATIO << 4) \
	193	+ \| (ACP_RATIO << 0))
	194	+
	195	+/* CLK_DIV_DMC1 */
	196	+#define DPM_RATIO 0x1
	197	+#define DVSEM_RATIO 0x1
	198	+#define PWI_RATIO 0x1
	199	+#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
	200	+ \| (DVSEM_RATIO << 16) \
	201	+ \| (PWI_RATIO << 8))
	202	+
	203	+/* CLK_SRC_TOP0 */
	204	+#define MUX_ONENAND_SEL_ACLK_133 0x0
	205	+#define MUX_ONENAND_SEL_ACLK_160 0x1
	206	+#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
	207	+#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
	208	+#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
	209	+#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
	210	+#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
	211	+#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
	212	+#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
	213	+#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
	214	+#define MUX_VPLL_SEL_FINPLL 0x0
	215	+#define MUX_VPLL_SEL_FOUTVPLL 0x1
	216	+#define MUX_EPLL_SEL_FINPLL 0x0
	217	+#define MUX_EPLL_SEL_FOUTEPLL 0x1
	218	+#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
	219	+#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
	220	+#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
	221	+ \| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
	222	+ \| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
	223	+ \| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
	224	+ \| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
	225	+ \| (MUX_VPLL_SEL_FINPLL << 8) \
	226	+ \| (MUX_EPLL_SEL_FINPLL << 4)\
	227	+ \| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
	228	+
	229	+/* CLK_SRC_TOP1 */
	230	+#define VPLLSRC_SEL_FINPLL 0x0
	231	+#define VPLLSRC_SEL_SCLKHDMI24M 0x1
	232	+#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
	233	+
	234	+/* CLK_DIV_TOP */
	235	+#define ONENAND_RATIO 0x0
	236	+#define ACLK_133_RATIO 0x5
	237	+#define ACLK_160_RATIO 0x4
	238	+#define ACLK_100_RATIO 0x7
	239	+#define ACLK_200_RATIO 0x3
	240	+#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
	241	+ \| (ACLK_133_RATIO << 12)\
	242	+ \| (ACLK_160_RATIO << 8) \
	243	+ \| (ACLK_100_RATIO << 4) \
	244	+ \| (ACLK_200_RATIO << 0))
	245	+
	246	+/* CLK_SRC_LEFTBUS */
	247	+#define MUX_GDL_SEL_SCLKMPLL 0x0
	248	+#define MUX_GDL_SEL_SCLKAPLL 0x1
	249	+#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
	250	+
	251	+/* CLK_DIV_LEFTBUS */
	252	+#define GPL_RATIO 0x1
	253	+#define GDL_RATIO 0x3
	254	+#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) \| (GDL_RATIO))
	255	+
	256	+/* CLK_SRC_RIGHTBUS */
	257	+#define MUX_GDR_SEL_SCLKMPLL 0x0
	258	+#define MUX_GDR_SEL_SCLKAPLL 0x1
	259	+#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
	260	+
	261	+/* CLK_DIV_RIGHTBUS */
	262	+#define GPR_RATIO 0x1
	263	+#define GDR_RATIO 0x3
	264	+#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) \| (GDR_RATIO))
	265	+
	266	+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
	267	+#define SATA_SEL_SCLKMPLL 0
	268	+#define SATA_SEL_SCLKAPLL 1
	269	+
	270	+#define MMC_SEL_XXTI 0
	271	+#define MMC_SEL_XUSBXTI 1
	272	+#define MMC_SEL_SCLK_HDMI24M 2
	273	+#define MMC_SEL_SCLK_USBPHY0 3
	274	+#define MMC_SEL_SCLK_USBPHY1 4
	275	+#define MMC_SEL_SCLK_HDMIPHY 5
	276	+#define MMC_SEL_SCLKMPLL 6
	277	+#define MMC_SEL_SCLKEPLL 7
	278	+#define MMC_SEL_SCLKVPLL 8
	279	+
	280	+#define MMCC0_SEL MMC_SEL_SCLKMPLL
	281	+#define MMCC1_SEL MMC_SEL_SCLKMPLL
	282	+#define MMCC2_SEL MMC_SEL_SCLKMPLL
	283	+#define MMCC3_SEL MMC_SEL_SCLKMPLL
	284	+#define MMCC4_SEL MMC_SEL_SCLKMPLL
	285	+#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
	286	+ \| (MMCC4_SEL << 16) \
	287	+ \| (MMCC3_SEL << 12) \
	288	+ \| (MMCC2_SEL << 8) \
	289	+ \| (MMCC1_SEL << 4) \
	290	+ \| (MMCC0_SEL << 0))
	291	+
	292	+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
	293	+/* CLK_DIV_FSYS1 */
	294	+#define MMC0_RATIO 0xF
	295	+#define MMC0_PRE_RATIO 0x0
	296	+#define MMC1_RATIO 0xF
	297	+#define MMC1_PRE_RATIO 0x0
	298	+#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
	299	+ \| (MMC1_RATIO << 16) \
	300	+ \| (MMC0_PRE_RATIO << 8) \
	301	+ \| (MMC0_RATIO << 0))
	302	+
	303	+/* CLK_DIV_FSYS2 */
	304	+#define MMC2_RATIO 0xF
	305	+#define MMC2_PRE_RATIO 0x0
	306	+#define MMC3_RATIO 0xF
	307	+#define MMC3_PRE_RATIO 0x0
	308	+#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
	309	+ \| (MMC3_RATIO << 16) \
	310	+ \| (MMC2_PRE_RATIO << 8) \
	311	+ \| (MMC2_RATIO << 0))
	312	+
	313	+/* CLK_DIV_FSYS3 */
	314	+#define MMC4_RATIO 0xF
	315	+#define MMC4_PRE_RATIO 0x0
	316	+#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
	317	+ \| (MMC4_RATIO << 0))
	318	+
	319	+/* CLK_SRC_PERIL0 */
	320	+#define UART_SEL_XXTI 0
	321	+#define UART_SEL_XUSBXTI 1
	322	+#define UART_SEL_SCLK_HDMI24M 2
	323	+#define UART_SEL_SCLK_USBPHY0 3
	324	+#define UART_SEL_SCLK_USBPHY1 4
	325	+#define UART_SEL_SCLK_HDMIPHY 5
	326	+#define UART_SEL_SCLKMPLL 6
	327	+#define UART_SEL_SCLKEPLL 7
	328	+#define UART_SEL_SCLKVPLL 8
	329	+
	330	+#define UART0_SEL UART_SEL_SCLKMPLL
	331	+#define UART1_SEL UART_SEL_SCLKMPLL
	332	+#define UART2_SEL UART_SEL_SCLKMPLL
	333	+#define UART3_SEL UART_SEL_SCLKMPLL
	334	+#define UART4_SEL UART_SEL_SCLKMPLL
	335	+#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
	336	+ \| (UART3_SEL << 12) \
	337	+ \| (UART2_SEL << 8) \
	338	+ \| (UART1_SEL << 4) \
	339	+ \| (UART0_SEL << 0))
	340	+
	341	+/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
	342	+/* CLK_DIV_PERIL0 */
	343	+#define UART0_RATIO 7
	344	+#define UART1_RATIO 7
	345	+#define UART2_RATIO 7
	346	+#define UART3_RATIO 7
	347	+#define UART4_RATIO 7
	348	+#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
	349	+ \| (UART3_RATIO << 12) \
	350	+ \| (UART2_RATIO << 8) \
	351	+ \| (UART1_RATIO << 4) \
	352	+ \| (UART0_RATIO << 0))
	353	+
	354	+/* Required period to generate a stable clock output */
	355	+/* PLL_LOCK_TIME */
	356	+#define PLL_LOCKTIME 0x1C20
	357	+
	358	+/* PLL Values */
	359	+#define DISABLE 0
	360	+#define ENABLE 1
	361	+#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
	362	+ \| (mdiv << 16) \
	363	+ \| (pdiv << 8) \
	364	+ \| (sdiv << 0))
	365	+
	366	+/* APLL_CON0 */
	367	+#define APLL_MDIV 0xFA
	368	+#define APLL_PDIV 0x6
	369	+#define APLL_SDIV 0x1
	370	+#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
	371	+
	372	+/* APLL_CON1 */
	373	+#define APLL_AFC_ENB 0x1
	374	+#define APLL_AFC 0xC
	375	+#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) \| (APLL_AFC << 0))
	376	+
	377	+/* MPLL_CON0 */
	378	+#define MPLL_MDIV 0xC8
	379	+#define MPLL_PDIV 0x6
	380	+#define MPLL_SDIV 0x1
	381	+#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
	382	+
	383	+/* MPLL_CON1 */
	384	+#define MPLL_AFC_ENB 0x0
	385	+#define MPLL_AFC 0x1C
	386	+#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) \| (MPLL_AFC << 0))
	387	+
	388	+/* EPLL_CON0 */
	389	+#define EPLL_MDIV 0x30
	390	+#define EPLL_PDIV 0x3
	391	+#define EPLL_SDIV 0x2
	392	+#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
	393	+
	394	+/* EPLL_CON1 */
	395	+#define EPLL_K 0x0
	396	+#define EPLL_CON1_VAL (EPLL_K >> 0)
	397	+
	398	+/* VPLL_CON0 */
	399	+#define VPLL_MDIV 0x35
	400	+#define VPLL_PDIV 0x3
	401	+#define VPLL_SDIV 0x2
	402	+#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
	403	+
	404	+/* VPLL_CON1 */
	405	+#define VPLL_SSCG_EN DISABLE
	406	+#define VPLL_SEL_PF_DN_SPREAD 0x0
	407	+#define VPLL_MRR 0x11
	408	+#define VPLL_MFR 0x0
	409	+#define VPLL_K 0x400
	410	+#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
	411	+ \| (VPLL_SEL_PF_DN_SPREAD << 29) \
	412	+ \| (VPLL_MRR << 24) \
	413	+ \| (VPLL_MFR << 16) \
	414	+ \| (VPLL_K << 0))
	415	+/*
	416	+ * UART GPIO_A0/GPIO_A1 Control Register Value
	417	+ * 0x2: UART Function
	418	+ */
	419	+#define S5PC210_GPIO_A0_CON_VAL 0x22222222
	420	+#define S5PC210_GPIO_A1_CON_VAL 0x222222
	421	+
	422	+/* ULCON: UART Line Control Value 8N1 */
	423	+#define WORD_LEN_5_BIT 0x00
	424	+#define WORD_LEN_6_BIT 0x01
	425	+#define WORD_LEN_7_BIT 0x02
	426	+#define WORD_LEN_8_BIT 0x03
	427	+
	428	+#define STOP_BIT_1 0x00
	429	+#define STOP_BIT_2 0x01
	430	+
	431	+#define NO_PARITY 0x00
	432	+#define ODD_PARITY 0x4
	433	+#define EVEN_PARITY 0x5
	434	+#define FORCED_PARITY_CHECK_AS_1 0x6
	435	+#define FORCED_PARITY_CHECK_AS_0 0x7
	436	+
	437	+#define INFRAMODE_NORMAL 0x00
	438	+#define INFRAMODE_INFRARED 0x01
	439	+
	440	+#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
	441	+ \| (NO_PARITY << 3) \
	442	+ \| (STOP_BIT_1 << 2) \
	443	+ \| (WORD_LEN_8_BIT << 0))
	444	+
	445	+/*
	446	+ * UCON: UART Control Value
	447	+ * Tx_interrupt Type: Level
	448	+ * Rx_interrupt Type: Level
	449	+ * Rx Timeout Enabled: Yes
	450	+ * Rx-Error Atatus_Int Enable: Yes
	451	+ * Loop_Back: No
	452	+ * Break Signal: No
	453	+ * Transmit mode : Interrupt request/polling
	454	+ * Receive mode : Interrupt request/polling
	455	+ */
	456	+#define TX_PULSE_INTERRUPT 0
	457	+#define TX_LEVEL_INTERRUPT 1
	458	+#define RX_PULSE_INTERRUPT 0
	459	+#define RX_LEVEL_INTERRUPT 1
	460	+
	461	+#define RX_TIME_OUT ENABLE
	462	+#define RX_ERROR_STATE_INT_ENB ENABLE
	463	+#define LOOP_BACK DISABLE
	464	+#define BREAK_SIGNAL DISABLE
	465	+
	466	+#define TX_MODE_DISABLED 0X00
	467	+#define TX_MODE_IRQ_OR_POLL 0X01
	468	+#define TX_MODE_DMA 0X02
	469	+
	470	+#define RX_MODE_DISABLED 0X00
	471	+#define RX_MODE_IRQ_OR_POLL 0X01
	472	+#define RX_MODE_DMA 0X02
	473	+
	474	+#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
	475	+ \| (RX_LEVEL_INTERRUPT << 8) \
	476	+ \| (RX_TIME_OUT << 7) \
	477	+ \| (RX_ERROR_STATE_INT_ENB << 6) \
	478	+ \| (LOOP_BACK << 5) \
	479	+ \| (BREAK_SIGNAL << 4) \
	480	+ \| (TX_MODE_IRQ_OR_POLL << 2) \
	481	+ \| (RX_MODE_IRQ_OR_POLL << 0))
	482	+
	483	+/*
	484	+ * UFCON: UART FIFO Control Value
	485	+ * Tx FIFO Trigger LEVEL: 2 Bytes (001)
	486	+ * Rx FIFO Trigger LEVEL: 2 Bytes (001)
	487	+ * Tx Fifo Reset: No
	488	+ * Rx Fifo Reset: No
	489	+ * FIFO Enable: Yes
	490	+ */
	491	+#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
	492	+#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
	493	+#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
	494	+#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
	495	+#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
	496	+#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
	497	+#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
	498	+#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
	499	+
	500	+#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
	501	+#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
	502	+#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
	503	+#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
	504	+#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
	505	+#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
	506	+#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
	507	+#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
	508	+
	509	+#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
	510	+#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
	511	+#define TX_FIFO_RESET DISABLE
	512	+#define RX_FIFO_RESET DISABLE
	513	+#define FIFO_ENABLE ENABLE
	514	+#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
	515	+ \| (RX_FIFO_TRIGGER_LEVEL << 4) \
	516	+ \| (TX_FIFO_RESET << 2) \
	517	+ \| (RX_FIFO_RESET << 1) \
	518	+ \| (FIFO_ENABLE << 0))
	519	+/*
	520	+ * Baud Rate Division Value
	521	+ * 115200 BAUD:
	522	+ * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
	523	+ * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
	524	+ */
	525	+#define UBRDIV_VAL 0x35
	526	+
	527	+/*
	528	+ * Fractional Part of Baud Rate Divisor:
	529	+ * 115200 BAUD:
	530	+ * UBRFRACVAL = ((((SCLK_UART10/(11520016) -10))%10)*16/10)
	531	+ * UBRFRACVAL = ((((800MHz10/(11520016) -10))%10)*16/10)
	532	+ */
	533	+#define UFRACVAL_VAL 0x4
	534	+
	535	+/*
	536	+ * TZPC Register Value :
	537	+ * R0SIZE: 0x0 : Size of secured ram
	538	+ */
	539	+#define R0SIZE 0x0
	540	+
	541	+/*
	542	+ * TZPC Decode Protection Register Value :
	543	+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
	544	+ */
	545	+#define DECPROTXSET 0xFF
	546	+#endif
...	...	@@ -186,6 +186,7 @@
186	186	omap4_sdp4430 arm armv7 sdp4430 ti omap4
187	187	s5p_goni arm armv7 goni samsung s5pc1xx
188	188	smdkc100 arm armv7 smdkc100 samsung s5pc1xx
	189	+origen arm armv7 origen samsung s5pc2xx
189	190	s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
190	191	smdkv310 arm armv7 smdkv310 samsung s5pc2xx
191	192	harmony arm armv7 harmony nvidia tegra2
	1	+/*
	2	+ * Copyright (C) 2011 Samsung Electronics
	3	+ *
	4	+ * Configuration settings for the SAMSUNG ORIGEN (S5PV310) board.
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#ifndef __CONFIG_H
	26	+#define __CONFIG_H
	27	+
	28	+/* High Level Configuration Options */
	29	+#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
	30	+#define CONFIG_S5P 1 /* S5P Family */
	31	+#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
	32	+#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
	33	+
	34	+#include <asm/arch/cpu.h> /* get chip and board defs */
	35	+
	36	+#define CONFIG_ARCH_CPU_INIT
	37	+#define CONFIG_DISPLAY_CPUINFO
	38	+#define CONFIG_DISPLAY_BOARDINFO
	39	+
	40	+/* Keep L2 Cache Disabled */
	41	+#define CONFIG_L2_OFF 1
	42	+#define CONFIG_SYS_DCACHE_OFF 1
	43	+
	44	+#define CONFIG_SYS_SDRAM_BASE 0x40000000
	45	+#define CONFIG_SYS_TEXT_BASE 0x43E00000
	46	+
	47	+/* input clock of PLL: ORIGEN has 24MHz input clock */
	48	+#define CONFIG_SYS_CLK_FREQ 24000000
	49	+
	50	+#define CONFIG_SETUP_MEMORY_TAGS
	51	+#define CONFIG_CMDLINE_TAG
	52	+#define CONFIG_INITRD_TAG
	53	+#define CONFIG_CMDLINE_EDITING
	54	+
	55	+/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */
	56	+#define MACH_TYPE_ORIGEN 3455
	57	+#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
	58	+
	59	+/* Power Down Modes */
	60	+#define S5P_CHECK_SLEEP 0x00000BAD
	61	+#define S5P_CHECK_DIDLE 0xBAD00000
	62	+#define S5P_CHECK_LPA 0xABAD0000
	63	+
	64	+/* Size of malloc() pool */
	65	+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	66	+
	67	+/* select serial console configuration */
	68	+#define CONFIG_SERIAL_MULTI 1
	69	+#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
	70	+#define CONFIG_BAUDRATE 115200
	71	+#define S5PC210_DEFAULT_UART_OFFSET 0x020000
	72	+
	73	+/* SD/MMC configuration */
	74	+#define CONFIG_GENERIC_MMC 1
	75	+#define CONFIG_MMC 1
	76	+#define CONFIG_S5P_MMC 1
	77	+
	78	+/* PWM */
	79	+#define CONFIG_PWM 1
	80	+
	81	+/* allow to overwrite serial and ethaddr */
	82	+#define CONFIG_ENV_OVERWRITE
	83	+
	84	+/* Command definition*/
	85	+#include <config_cmd_default.h>
	86	+
	87	+#define CONFIG_CMD_PING
	88	+#define CONFIG_CMD_ELF
	89	+#define CONFIG_CMD_DHCP
	90	+#define CONFIG_CMD_MMC
	91	+#define CONFIG_CMD_FAT
	92	+#undef CONFIG_CMD_NET
	93	+#undef CONFIG_CMD_NFS
	94	+
	95	+#define CONFIG_BOOTDELAY 3
	96	+#define CONFIG_ZERO_BOOTDELAY_CHECK
	97	+
	98	+#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
	99	+
	100	+/* Miscellaneous configurable options */
	101	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	102	+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	103	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	104	+#define CONFIG_SYS_PROMPT "ORIGEN # "
	105	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
	106	+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	107	+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	108	+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
	109	+/* Boot Argument Buffer Size */
	110	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	111	+/* memtest works on */
	112	+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	113	+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
	114	+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
	115	+
	116	+#define CONFIG_SYS_HZ 1000
	117	+
	118	+/* valid baudrates */
	119	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	120	+
	121	+/* Stack sizes */
	122	+#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
	123	+
	124	+/* ORIGEN has 4 bank of DRAM */
	125	+#define CONFIG_NR_DRAM_BANKS 4
	126	+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
	127	+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	128	+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
	129	+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
	130	+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
	131	+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
	132	+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
	133	+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
	134	+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
	135	+
	136	+/* FLASH and environment organization */
	137	+#define CONFIG_SYS_NO_FLASH 1
	138	+#undef CONFIG_CMD_IMLS
	139	+#define CONFIG_IDENT_STRING " for ORIGEN"
	140	+
	141	+#ifdef CONFIG_USE_IRQ
	142	+#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	143	+#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	144	+#endif
	145	+
	146	+#define CONFIG_CLK_1000_400_200
	147	+
	148	+/* MIU (Memory Interleaving Unit) */
	149	+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
	150	+
	151	+#define CONFIG_ENV_IS_IN_MMC 1
	152	+#define CONFIG_SYS_MMC_ENV_DEV 0
	153	+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
	154	+#define RESERVE_BLOCK_SIZE (512)
	155	+#define BL1_SIZE (16 << 10) /16 K reserved for BL1/
	156	+#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
	157	+#define CONFIG_DOS_PARTITION 1
	158	+
	159	+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
	160	+#endif /* __CONFIG_H */