Commit b9ae6415b6a099478c71fc3d410fc9a3776d7afa
Committed by
Tom Warren
Tom Warren
1 parent
6db8e17892
Exists in
v2017.01-smarct4x
and in
25 other branches
ARM: tegra: translate __asm_flush_l3_cache to assembly
When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Showing 2 changed files with 25 additions and 23 deletions Side-by-side Diff
arch/arm/mach-tegra/tegra186/cache.S
| 1 | +/* | |
| 2 | + * Copyright (c) 2016, NVIDIA CORPORATION. | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0 | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <config.h> | |
| 8 | +#include <linux/linkage.h> | |
| 9 | + | |
| 10 | +#define SMC_SIP_INVOKE_MCE 0x82FFFF00 | |
| 11 | +#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) | |
| 12 | + | |
| 13 | +ENTRY(__asm_flush_l3_cache) | |
| 14 | + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) | |
| 15 | + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 | |
| 16 | + mov x1, #0 | |
| 17 | + mov x2, #0 | |
| 18 | + mov x3, #0 | |
| 19 | + mov x4, #0 | |
| 20 | + mov x5, #0 | |
| 21 | + mov x6, #0 | |
| 22 | + smc #0 | |
| 23 | + mov x0, #0 | |
| 24 | + ret | |
| 25 | +ENDPROC(__asm_flush_l3_cache) |
arch/arm/mach-tegra/tegra186/cache.c
| 1 | -/* | |
| 2 | - * Copyright (c) 2016, NVIDIA CORPORATION. | |
| 3 | - * | |
| 4 | - * SPDX-License-Identifier: GPL-2.0 | |
| 5 | - */ | |
| 6 | - | |
| 7 | -#include <common.h> | |
| 8 | -#include <asm/system.h> | |
| 9 | - | |
| 10 | -#define SMC_SIP_INVOKE_MCE 0x82FFFF00 | |
| 11 | -#define MCE_SMC_ROC_FLUSH_CACHE 11 | |
| 12 | - | |
| 13 | -int __asm_flush_l3_cache(void) | |
| 14 | -{ | |
| 15 | - struct pt_regs regs = {0}; | |
| 16 | - | |
| 17 | - isb(); | |
| 18 | - | |
| 19 | - regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE; | |
| 20 | - smc_call(®s); | |
| 21 | - | |
| 22 | - return 0; | |
| 23 | -} |