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Commit b9e186fc31683a4f1b6880c086950b2270e62e24

Authored by Sandeep Gopalpet
Committed by Kumar Gala
1 parent bcad21fda1
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

NET: Move MDIO regs out of TSEC Space 

Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.

This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.

Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 5 changed files with 52 additions and 35 deletions Side-by-side Diff

... ... @@ -5,7 +5,7 @@
5 5 * terms of the GNU Public License, Version 2, incorporated
6 6 * herein by reference.
7 7 *
8   - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  8 + * Copyright 2004-2009 Freescale Semiconductor, Inc.
9 9 * (C) Copyright 2003, Motorola, Inc.
10 10 * author Andy Fleming
11 11 *
... ... @@ -80,7 +80,7 @@
80 80 #ifdef CONFIG_MPC85XX_FEC
81 81 {
82 82 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
83   - .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
  83 + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
84 84 .devname = CONFIG_MPC85XX_FEC_NAME,
85 85 .phyaddr = FEC_PHY_ADDR,
86 86 .flags = FEC_FLAGS
... ... @@ -133,6 +133,7 @@
133 133 privlist[num_tsecs++] = priv;
134 134 priv->regs = tsec_info->regs;
135 135 priv->phyregs = tsec_info->miiregs;
  136 + priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
136 137  
137 138 priv->phyaddr = tsec_info->phyaddr;
138 139 priv->flags = tsec_info->flags;
... ... @@ -219,7 +220,7 @@
219 220 }
220 221  
221 222 /* Writes the given phy's reg with value, using the specified MDIO regs */
222   -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
  223 +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
223 224 uint reg, uint value)
224 225 {
225 226 int timeout = 1000000;
... ... @@ -242,7 +243,7 @@
242 243 * notvalid bit cleared), and the bus to cease activity (miimind
243 244 * busy bit cleared), and then returns the value
244 245 */
245   -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
  246 +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum)
246 247 {
247 248 uint value;
248 249  
249 250  
250 251  
... ... @@ -287,11 +288,11 @@
287 288 {
288 289 /* Access TBI PHY registers at given TSEC register offset as opposed to the
289 290 * register offset used for external PHY accesses */
290   - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
  291 + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
291 292 TBIANA_SETTINGS);
292   - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
  293 + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
293 294 TBICON_CLK_SELECT);
294   - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
  295 + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
295 296 TBICR_SETTINGS);
296 297 }
297 298  
298 299  
... ... @@ -303,12 +304,10 @@
303 304 {
304 305 struct tsec_private *priv = (struct tsec_private *)dev->priv;
305 306 struct phy_info *curphy;
306   - volatile tsec_t *phyregs = priv->phyregs;
307 307 volatile tsec_t *regs = priv->regs;
308 308  
309 309 /* Assign a Physical address to the TBI */
310 310 regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
311   - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
312 311 asm("sync");
313 312  
314 313 /* Reset MII (due to new addresses) */
... ... @@ -733,7 +732,7 @@
733 732 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
734 733 {
735 734 uint phyid;
736   - volatile tsec_t *regbase = priv->phyregs;
  735 + volatile tsec_mdio_t *regbase = priv->phyregs;
737 736 int timeout = 1000000;
738 737  
739 738 for (phyid = 0; phyid < 4; phyid++) {
... ... @@ -1766,7 +1765,7 @@
1766 1765 {
1767 1766 int i;
1768 1767 uint result;
1769   - volatile tsec_t *phyregs = priv->phyregs;
  1768 + volatile tsec_mdio_t *phyregs = priv->phyregs;
1770 1769  
1771 1770 phyregs->miimcfg = MIIMCFG_RESET;
1772 1771  
include/asm-ppc/immap_83xx.h
Diff comments   View file @ b9e186f
1 1 /*
2   - * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
  2 + * Copyright 2004-2009 Freescale Semiconductor, Inc.
3 3 *
4 4 * MPC83xx Internal Memory Map
5 5 *
... ... @@ -868,5 +868,11 @@
868 868 #endif
869 869 #define CONFIG_SYS_MPC83xx_USB_ADDR \
870 870 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
  871 +
  872 +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
  873 +#define CONFIG_SYS_MDIO1_OFFSET 0x24520
  874 +
  875 +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  876 +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
871 877 #endif /* __IMMAP_83xx__ */
include/asm-ppc/immap_85xx.h
Diff comments   View file @ b9e186f
... ... @@ -1959,6 +1959,8 @@
1959 1959 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
1960 1960 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
1961 1961 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
  1962 +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
  1963 +#define CONFIG_SYS_MDIO1_OFFSET 0x24520
1962 1964 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
1963 1965 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
1964 1966 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
... ... @@ -2018,6 +2020,9 @@
2018 2020 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
2019 2021 #define CONFIG_SYS_MPC85xx_USB_ADDR \
2020 2022 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
  2023 +
  2024 +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  2025 +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
2021 2026  
2022 2027 #endif /*__IMMAP_85xx__*/
include/asm-ppc/immap_86xx.h
Diff comments   View file @ b9e186f
1 1 /*
2 2 * MPC86xx Internal Memory Map
3 3 *
4   - * Copyright(c) 2004 Freescale Semiconductor
  4 + * Copyright 2004 Freescale Semiconductor
5 5 * Jeff Brown (Jeffrey@freescale.com)
6 6 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
7 7 *
... ... @@ -1297,6 +1297,12 @@
1297 1297 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
1298 1298 #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
1299 1299 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
  1300 +
  1301 +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
  1302 +#define CONFIG_SYS_MDIO1_OFFSET 0x24520
  1303 +
  1304 +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  1305 +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
1300 1306  
1301 1307 #endif /*__IMMAP_86xx__*/
... ... @@ -7,7 +7,7 @@
7 7 * terms of the GNU Public License, Version 2, incorporated
8 8 * herein by reference.
9 9 *
10   - * Copyright 2004, 2007 Freescale Semiconductor, Inc.
  10 + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
11 11 * (C) Copyright 2003, Motorola, Inc.
12 12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
13 13 * author Andy Fleming
14 14  
15 15  
... ... @@ -20,22 +20,15 @@
20 20 #include <net.h>
21 21 #include <config.h>
22 22  
23   -#ifndef CONFIG_SYS_TSEC1_OFFSET
24   - #define CONFIG_SYS_TSEC1_OFFSET (0x24000)
25   -#endif
  23 +#define TSEC_SIZE 0x01000
  24 +#define TSEC_MDIO_OFFSET 0x01000
26 25  
27   -#define TSEC_SIZE 0x01000
28   -
29   -/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30   -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
31   - || defined(CONFIG_MPC83xx)
32   - #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
33   -#endif
34   -
35 26 #define STD_TSEC_INFO(num) \
36 27 { \
37 28 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
38   - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \
  29 + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
  30 + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  31 + + (num - 1) * TSEC_MDIO_OFFSET), \
39 32 .devname = CONFIG_TSEC##num##_NAME, \
40 33 .phyaddr = TSEC##num##_PHY_ADDR, \
41 34 .flags = TSEC##num##_FLAGS \
... ... @@ -44,7 +37,9 @@
44 37 #define SET_STD_TSEC_INFO(x, num) \
45 38 { \
46 39 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
47   - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \
  40 + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
  41 + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  42 + + (num - 1) * TSEC_MDIO_OFFSET); \
48 43 x.devname = CONFIG_TSEC##num##_NAME; \
49 44 x.phyaddr = TSEC##num##_PHY_ADDR; \
50 45 x.flags = TSEC##num##_FLAGS;\
... ... @@ -461,6 +456,15 @@
461 456 uint res2[24];
462 457 } tsec_hash_t;
463 458  
  459 +typedef struct tsec_mdio {
  460 + uint miimcfg; /* MII Management: Configuration */
  461 + uint miimcom; /* MII Management: Command */
  462 + uint miimadd; /* MII Management: Address */
  463 + uint miimcon; /* MII Management: Control */
  464 + uint miimstat; /* MII Management: Status */
  465 + uint miimind; /* MII Management: Indicators */
  466 +} tsec_mdio_t;
  467 +
464 468 typedef struct tsec
465 469 {
466 470 /* General Control and Status Registers (0x2_n000) */
... ... @@ -526,12 +530,7 @@
526 530  
527 531 uint res51c;
528 532  
529   - uint miimcfg; /* MII Management: Configuration */
530   - uint miimcom; /* MII Management: Command */
531   - uint miimadd; /* MII Management: Address */
532   - uint miimcon; /* MII Management: Control */
533   - uint miimstat; /* MII Management: Status */
534   - uint miimind; /* MII Management: Indicators */
  533 + uint resmdio[6];
535 534  
536 535 uint res538;
537 536  
... ... @@ -571,7 +570,8 @@
571 570  
572 571 struct tsec_private {
573 572 volatile tsec_t *regs;
574   - volatile tsec_t *phyregs;
  573 + volatile tsec_mdio_t *phyregs;
  574 + volatile tsec_mdio_t *phyregs_sgmii;
575 575 struct phy_info *phyinfo;
576 576 uint phyaddr;
577 577 u32 flags;
... ... @@ -630,7 +630,8 @@
630 630  
631 631 struct tsec_info_struct {
632 632 tsec_t *regs;
633   - tsec_t *miiregs;
  633 + tsec_mdio_t *miiregs;
  634 + tsec_mdio_t *miiregs_sgmii;
634 635 char *devname;
635 636 unsigned int phyaddr;
636 637 u32 flags;