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Commit b9e745bbe2562fda710d668dc9cef46e0b23049f

Authored by Shengzhou Liu
Committed by York Sun
1 parent 93a6d3284c
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a 

This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.

Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 11 changed files with 262 additions and 409 deletions Side-by-side Diff

... ... @@ -655,6 +655,7 @@
655 655 libs-y += drivers/spi/
656 656 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
657 657 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
  658 +libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
658 659 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
659 660 libs-y += drivers/serial/
660 661 libs-y += drivers/usb/dwc3/
arch/arm/include/asm/arch-fsl-layerscape/config.h
Diff comments   View file @ b9e745b
... ... @@ -15,7 +15,9 @@
15 15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
16 16 #endif
17 17  
18   -#ifndef CONFIG_LS1012A
  18 +#ifdef CONFIG_LS1012A
  19 +#define CONFIG_SYS_FSL_MMDC /* Freescale MMDC driver */
  20 +#else
19 21 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
20 22 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
21 23 #endif
board/freescale/ls1012afrdm/ls1012afrdm.c
Diff comments   View file @ b9e745b
... ... @@ -17,127 +17,11 @@
17 17  
18 18 DECLARE_GLOBAL_DATA_PTR;
19 19  
20   -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
21   -{
22   - int timeout = 1000;
23   -
24   - out_be32(ptr, value);
25   -
26   - while (in_be32(ptr) & bits) {
27   - udelay(100);
28   - timeout--;
29   - }
30   - if (timeout <= 0)
31   - puts("Error: wait for clear timeout.\n");
32   -}
33   -
34 20 int checkboard(void)
35 21 {
36 22 puts("Board: LS1012AFRDM ");
37 23  
38 24 return 0;
39   -}
40   -
41   -void mmdc_init(void)
42   -{
43   - struct mmdc_p_regs *mmdc =
44   - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
45   -
46   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
47   -
48   - /* configure timing parms */
49   - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
50   - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
51   - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
52   - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
53   -
54   - /* other parms */
55   - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
56   - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
57   - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
58   - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
59   -
60   - /* out of reset delays */
61   - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
62   -
63   - /* physical parms */
64   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
65   - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
66   -
67   - /* Enable MMDC */
68   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
69   -
70   - /* dram init sequence: update MRs */
71   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
72   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
73   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
74   - CMD_BANK_ADDR_3));
75   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
76   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
77   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
78   - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
79   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
80   -
81   - /* dram init sequence: ZQCL */
82   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
83   - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
84   - set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
85   - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
86   - FORCE_ZQ_AUTO_CALIBRATION);
87   -
88   - /* Calibrations now: wr lvl */
89   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
90   - CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
91   - CMD_BANK_ADDR_1));
92   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
93   - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
94   -
95   - mdelay(1);
96   -
97   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
98   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
99   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
100   -
101   - mdelay(1);
102   -
103   - /* Calibrations now: Read DQS gating calibration */
104   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
105   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
106   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
107   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
108   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
109   - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
110   - set_wait_for_bits_clear(&mmdc->mpdgctrl0,
111   - AUTO_RD_DQS_GATING_CALIBRATION_EN,
112   - AUTO_RD_DQS_GATING_CALIBRATION_EN);
113   -
114   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
115   - CMD_BANK_ADDR_3));
116   -
117   - /* Calibrations now: Read calibration */
118   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
119   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
120   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
121   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
122   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
123   - set_wait_for_bits_clear(&mmdc->mprddlhwctl,
124   - AUTO_RD_CALIBRATION_EN,
125   - AUTO_RD_CALIBRATION_EN);
126   -
127   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
128   - CMD_BANK_ADDR_3));
129   -
130   - /* PD, SR */
131   - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
132   - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
133   -
134   - /* refresh scheme */
135   - set_wait_for_bits_clear(&mmdc->mdref,
136   - CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
137   - START_REFRESH);
138   -
139   - /* disable CON_REQ */
140   - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
141 25 }
142 26  
143 27 int dram_init(void)
board/freescale/ls1012aqds/ls1012aqds.c
Diff comments   View file @ b9e745b
... ... @@ -27,20 +27,6 @@
27 27  
28 28 DECLARE_GLOBAL_DATA_PTR;
29 29  
30   -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
31   -{
32   - int timeout = 1000;
33   -
34   - out_be32(ptr, value);
35   -
36   - while (in_be32(ptr) & bits) {
37   - udelay(100);
38   - timeout--;
39   - }
40   - if (timeout <= 0)
41   - puts("Error: wait for clear timeout.\n");
42   -}
43   -
44 30 int checkboard(void)
45 31 {
46 32 char buf[64];
... ... @@ -64,108 +50,6 @@
64 50 /* the timestamp string contains "\n" at the end */
65 51 printf(" on %s", qixis_read_time(buf));
66 52 return 0;
67   -}
68   -
69   -void mmdc_init(void)
70   -{
71   - struct mmdc_p_regs *mmdc =
72   - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
73   -
74   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
75   -
76   - /* configure timing parms */
77   - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
78   - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
79   - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
80   - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
81   -
82   - /* other parms */
83   - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
84   - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
85   - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
86   - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
87   -
88   - /* out of reset delays */
89   - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
90   -
91   - /* physical parms */
92   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
93   - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
94   -
95   - /* Enable MMDC */
96   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
97   -
98   - /* dram init sequence: update MRs */
99   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
100   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
101   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
102   - CMD_BANK_ADDR_3));
103   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
104   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
105   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
106   - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
107   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
108   -
109   - /* dram init sequence: ZQCL */
110   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
111   - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
112   - set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
113   - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
114   - FORCE_ZQ_AUTO_CALIBRATION);
115   -
116   - /* Calibrations now: wr lvl */
117   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
118   - CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
119   - CMD_BANK_ADDR_1));
120   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
121   - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
122   -
123   - mdelay(1);
124   -
125   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
126   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
127   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
128   -
129   - mdelay(1);
130   -
131   - /* Calibrations now: Read DQS gating calibration */
132   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
133   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
134   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
135   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
136   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
137   - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
138   - set_wait_for_bits_clear(&mmdc->mpdgctrl0,
139   - AUTO_RD_DQS_GATING_CALIBRATION_EN,
140   - AUTO_RD_DQS_GATING_CALIBRATION_EN);
141   -
142   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
143   - CMD_BANK_ADDR_3));
144   -
145   - /* Calibrations now: Read calibration */
146   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
147   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
148   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
149   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
150   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
151   - set_wait_for_bits_clear(&mmdc->mprddlhwctl,
152   - AUTO_RD_CALIBRATION_EN,
153   - AUTO_RD_CALIBRATION_EN);
154   -
155   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
156   - CMD_BANK_ADDR_3));
157   -
158   - /* PD, SR */
159   - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
160   - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
161   -
162   - /* refresh scheme */
163   - set_wait_for_bits_clear(&mmdc->mdref,
164   - CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
165   - START_REFRESH);
166   -
167   - /* disable CON_REQ */
168   - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
169 53 }
170 54  
171 55 int dram_init(void)
board/freescale/ls1012ardb/ls1012ardb.c
Diff comments   View file @ b9e745b
... ... @@ -21,20 +21,6 @@
21 21  
22 22 DECLARE_GLOBAL_DATA_PTR;
23 23  
24   -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
25   -{
26   - int timeout = 1000;
27   -
28   - out_be32(ptr, value);
29   -
30   - while (in_be32(ptr) & bits) {
31   - udelay(100);
32   - timeout--;
33   - }
34   - if (timeout <= 0)
35   - puts("Error: wait for clear timeout.\n");
36   -}
37   -
38 24 int checkboard(void)
39 25 {
40 26 u8 in1;
... ... @@ -68,108 +54,6 @@
68 54 puts("unknown\n");
69 55  
70 56 return 0;
71   -}
72   -
73   -void mmdc_init(void)
74   -{
75   - struct mmdc_p_regs *mmdc =
76   - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
77   -
78   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
79   -
80   - /* configure timing parms */
81   - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
82   - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
83   - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
84   - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
85   -
86   - /* other parms */
87   - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
88   - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
89   - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
90   - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
91   -
92   - /* out of reset delays */
93   - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
94   -
95   - /* physical parms */
96   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
97   - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
98   -
99   - /* Enable MMDC */
100   - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
101   -
102   - /* dram init sequence: update MRs */
103   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
104   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
105   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
106   - CMD_BANK_ADDR_3));
107   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
108   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
109   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
110   - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
111   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
112   -
113   - /* dram init sequence: ZQCL */
114   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
115   - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
116   - set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
117   - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
118   - FORCE_ZQ_AUTO_CALIBRATION);
119   -
120   - /* Calibrations now: wr lvl */
121   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
122   - CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
123   - CMD_BANK_ADDR_1));
124   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
125   - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
126   -
127   - mdelay(1);
128   -
129   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
130   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
131   - out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
132   -
133   - mdelay(1);
134   -
135   - /* Calibrations now: Read DQS gating calibration */
136   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
137   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
138   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
139   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
140   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
141   - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
142   - set_wait_for_bits_clear(&mmdc->mpdgctrl0,
143   - AUTO_RD_DQS_GATING_CALIBRATION_EN,
144   - AUTO_RD_DQS_GATING_CALIBRATION_EN);
145   -
146   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
147   - CMD_BANK_ADDR_3));
148   -
149   - /* Calibrations now: Read calibration */
150   - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
151   - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
152   - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
153   - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
154   - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
155   - set_wait_for_bits_clear(&mmdc->mprddlhwctl,
156   - AUTO_RD_CALIBRATION_EN,
157   - AUTO_RD_CALIBRATION_EN);
158   -
159   - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
160   - CMD_BANK_ADDR_3));
161   -
162   - /* PD, SR */
163   - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
164   - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
165   -
166   - /* refresh scheme */
167   - set_wait_for_bits_clear(&mmdc->mdref,
168   - CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
169   - START_REFRESH);
170   -
171   - /* disable CON_REQ */
172   - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
173 57 }
174 58  
175 59 int dram_init(void)
drivers/ddr/fsl/Makefile
Diff comments   View file @ b9e745b
... ... @@ -33,4 +33,5 @@
33 33 obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
34 34 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
35 35 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
  36 +obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
drivers/ddr/fsl/fsl_mmdc.c
Diff comments   View file @ b9e745b
  1 +/*
  2 + * Copyright 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <fsl_mmdc.h>
  13 +#include <asm/io.h>
  14 +
  15 +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  16 +{
  17 + int timeout = 1000;
  18 +
  19 + out_be32(ptr, value);
  20 +
  21 + while (in_be32(ptr) & bits) {
  22 + udelay(100);
  23 + timeout--;
  24 + }
  25 + if (timeout <= 0)
  26 + printf("Error: %p wait for clear timeout.\n", ptr);
  27 +}
  28 +
  29 +void mmdc_init(void)
  30 +{
  31 + struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
  32 + unsigned int tmp;
  33 +
  34 + /* 1. set configuration request */
  35 + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
  36 +
  37 + /* 2. configure the desired timing parameters */
  38 + out_be32(&mmdc->mdotc, CONFIG_MMDC_MDOTC);
  39 + out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0);
  40 + out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1);
  41 + out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2);
  42 +
  43 + /* 3. configure DDR type and other miscellaneous parameters */
  44 + out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC);
  45 + out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
  46 + out_be32(&mmdc->mdrwd, CONFIG_MMDC_MDRWD);
  47 + out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL);
  48 +
  49 + /* 4. configure the required delay while leaving reset */
  50 + out_be32(&mmdc->mdor, CONFIG_MMDC_MDOR);
  51 +
  52 + /* 5. configure DDR physical parameters */
  53 + /* set row/column address width, burst length, data bus width */
  54 + tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1);
  55 + out_be32(&mmdc->mdctl, tmp);
  56 + /* configure address space partition */
  57 + out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP);
  58 +
  59 + /* 6. perform a ZQ calibration - not needed here, doing in #8b */
  60 +
  61 + /* 7. enable MMDC with the desired chip select */
  62 +#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
  63 + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
  64 +#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
  65 + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
  66 +#endif
  67 +
  68 + /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
  69 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
  70 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
  71 +
  72 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
  73 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
  74 +
  75 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
  76 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
  77 +
  78 + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
  79 + CMD_ADDR_LSB_MR_ADDR(0x30) |
  80 + MDSCR_ENABLE_CON_REQ |
  81 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
  82 +
  83 + /* 8b. ZQ calibration */
  84 + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
  85 + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
  86 +
  87 + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, CONFIG_MMDC_MPZQHWCTRL,
  88 + MPZQHWCTRL_ZQ_HW_FORCE);
  89 +
  90 + /* 9a. calibrations now, wr lvl */
  91 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
  92 + MDSCR_ENABLE_CON_REQ |
  93 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
  94 +
  95 + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
  96 + CMD_NORMAL);
  97 +
  98 + set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
  99 + MPWLGCR_HW_WL_EN);
  100 +
  101 + mdelay(1);
  102 +
  103 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
  104 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
  105 + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
  106 +
  107 + mdelay(1);
  108 +
  109 + /* 9b. read DQS gating calibration */
  110 + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
  111 + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
  112 +
  113 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
  114 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
  115 +
  116 + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
  117 +
  118 + /* set absolute read delay offset */
  119 +#if defined(CONFIG_MMDC_MPRDDLCTL)
  120 + out_be32(&mmdc->mprddlctl, CONFIG_MMDC_MPRDDLCTL);
  121 +#else
  122 + out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
  123 +#endif
  124 + set_wait_for_bits_clear(&mmdc->mpdgctrl0,
  125 + AUTO_RD_DQS_GATING_CALIBRATION_EN,
  126 + AUTO_RD_DQS_GATING_CALIBRATION_EN);
  127 +
  128 + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
  129 + CMD_BANK_ADDR_3);
  130 +
  131 + /* 9c. read calibration */
  132 + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
  133 + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
  134 + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
  135 + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
  136 + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
  137 + set_wait_for_bits_clear(&mmdc->mprddlhwctl,
  138 + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
  139 + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
  140 +
  141 + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
  142 + CMD_BANK_ADDR_3);
  143 +
  144 + /* 10. configure power-down, self-refresh entry, exit parameters */
  145 + out_be32(&mmdc->mdpdc, CONFIG_MMDC_MDPDC);
  146 + out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
  147 +
  148 + /* 11. ZQ config again? do nothing here */
  149 +
  150 + /* 12. refresh scheme */
  151 + set_wait_for_bits_clear(&mmdc->mdref, CONFIG_MMDC_MDREF,
  152 + MDREF_START_REFRESH);
  153 +
  154 + /* 13. disable CON_REQ */
  155 + out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
  156 +}
include/configs/ls1012afrdm.h
Diff comments   View file @ b9e745b
... ... @@ -9,18 +9,32 @@
9 9  
10 10 #include "ls1012a_common.h"
11 11  
  12 +/* DDR */
12 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
13 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
14 15 #define CONFIG_NR_DRAM_BANKS 2
15 16 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
16   -
17   -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
18   -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
19   -
  17 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
20 18 #define CONFIG_CMD_MEMINFO
21 19 #define CONFIG_CMD_MEMTEST
22 20 #define CONFIG_SYS_MEMTEST_START 0x80000000
23 21 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  22 +
  23 +/* DDR board-specific timing parameters */
  24 +#define CONFIG_MMDC_MDCTL 0x04180000
  25 +#define CONFIG_MMDC_MDPDC 0x00030035
  26 +#define CONFIG_MMDC_MDOTC 0x12554000
  27 +#define CONFIG_MMDC_MDCFG0 0xbabf7954
  28 +#define CONFIG_MMDC_MDCFG1 0xdb328f64
  29 +#define CONFIG_MMDC_MDCFG2 0x01ff00db
  30 +#define CONFIG_MMDC_MDMISC 0x00001680
  31 +#define CONFIG_MMDC_MDREF 0x0f3c8000
  32 +#define CONFIG_MMDC_MDRWD 0x00002000
  33 +#define CONFIG_MMDC_MDOR 0x00bf1023
  34 +#define CONFIG_MMDC_MDASP 0x0000003f
  35 +#define CONFIG_MMDC_MPODTCTRL 0x0000022a
  36 +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
  37 +
24 38  
25 39 /*
26 40 * USB
include/configs/ls1012aqds.h
Diff comments   View file @ b9e745b
... ... @@ -9,14 +9,31 @@
9 9  
10 10 #include "ls1012a_common.h"
11 11  
12   -
  12 +/* DDR */
13 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 15 #define CONFIG_NR_DRAM_BANKS 2
16 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
  17 +#define CONFIG_CMD_MEMINFO
  18 +#define CONFIG_CMD_MEMTEST
  19 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  20 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
17 21  
18   -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
19   -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
  22 +/* DDR board-specific timing parameters */
  23 +#define CONFIG_MMDC_MDCTL 0x05180000
  24 +#define CONFIG_MMDC_MDPDC 0x00030035
  25 +#define CONFIG_MMDC_MDOTC 0x12554000
  26 +#define CONFIG_MMDC_MDCFG0 0xbabf7954
  27 +#define CONFIG_MMDC_MDCFG1 0xdb328f64
  28 +#define CONFIG_MMDC_MDCFG2 0x01ff00db
  29 +#define CONFIG_MMDC_MDMISC 0x00001680
  30 +#define CONFIG_MMDC_MDREF 0x0f3c8000
  31 +#define CONFIG_MMDC_MDRWD 0x00002000
  32 +#define CONFIG_MMDC_MDOR 0x00bf1023
  33 +#define CONFIG_MMDC_MDASP 0x0000003f
  34 +#define CONFIG_MMDC_MPODTCTRL 0x0000022a
  35 +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
  36 +
20 37  
21 38 /*
22 39 * QIXIS Definitions
include/configs/ls1012ardb.h
Diff comments   View file @ b9e745b
... ... @@ -9,19 +9,30 @@
9 9  
10 10 #include "ls1012a_common.h"
11 11  
12   -
  12 +/* DDR */
13 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 15 #define CONFIG_NR_DRAM_BANKS 2
16 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
17   -
18   -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
19   -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
20   -
21 17 #define CONFIG_CMD_MEMINFO
22 18 #define CONFIG_CMD_MEMTEST
23 19 #define CONFIG_SYS_MEMTEST_START 0x80000000
24 20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  21 +
  22 +/* DDR board-specific timing parameters */
  23 +#define CONFIG_MMDC_MDCTL 0x05180000
  24 +#define CONFIG_MMDC_MDPDC 0x00030035
  25 +#define CONFIG_MMDC_MDOTC 0x12554000
  26 +#define CONFIG_MMDC_MDCFG0 0xbabf7954
  27 +#define CONFIG_MMDC_MDCFG1 0xdb328f64
  28 +#define CONFIG_MMDC_MDCFG2 0x01ff00db
  29 +#define CONFIG_MMDC_MDMISC 0x00001680
  30 +#define CONFIG_MMDC_MDREF 0x0f3c8000
  31 +#define CONFIG_MMDC_MDRWD 0x00002000
  32 +#define CONFIG_MMDC_MDOR 0x00bf1023
  33 +#define CONFIG_MMDC_MDASP 0x0000003f
  34 +#define CONFIG_MMDC_MPODTCTRL 0x0000022a
  35 +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
25 36  
26 37 /*
27 38 * USB
... ... @@ -7,63 +7,39 @@
7 7 #ifndef FSL_MMDC_H
8 8 #define FSL_MMDC_H
9 9  
10   -#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
11   -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
12   -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
13   -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
  10 +/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
  11 +#define MPWLGCR_HW_WL_EN (1 << 0)
14 12  
15   -#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
16   -#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
17   -#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
18   -#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
19   -
20   -#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
21   -
22   -#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
23   -
24   -#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
25   -
26   -#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
27   -
28   -/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
29   -#define WR_LVL_HW_EN 0x00000001
30   -
31 13 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
32   -#define MPR_COMPARE_EN 0x00000001
  14 +#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
33 15  
34   -#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
35 16  
36 17 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
37   -#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
  18 +#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
38 19  
39 20 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
40   -#define AUTO_RD_CALIBRATION_EN 0x00000010
  21 +#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
41 22  
42   -#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
  23 +/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
  24 +#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
43 25  
44   -#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
  26 +/* MMDC Core Refresh Control Register (MMDC_MDREF) */
  27 +#define MDREF_START_REFRESH (1 << 0)
45 28  
46   -#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
47   -
48   -#define START_REFRESH 0x00000001
49   -
50 29 /* MMDC Core Special Command Register (MDSCR) */
51   -#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
52   -
53   -#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
54   -
55   -#define DISABLE_CFG_REQ 0x0
56   -#define CONFIGURATION_REQ (0x1 << 15)
57   -#define WL_EN (0x1 << 9)
58   -
59   -#define CMD_NORMAL (0x0 << 4)
60   -#define CMD_PRECHARGE (0x1 << 4)
61   -#define CMD_AUTO_REFRESH (0x2 << 4)
62   -#define CMD_LOAD_MODE_REG (0x3 << 4)
63   -#define CMD_ZQ_CALIBRATION (0x4 << 4)
64   -#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
65   -#define CMD_MRR (0x6 << 4)
66   -
  30 +#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
  31 +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
  32 +#define MDSCR_DISABLE_CFG_REQ (0 << 15)
  33 +#define MDSCR_ENABLE_CON_REQ (1 << 15)
  34 +#define MDSCR_CON_ACK (1 << 14)
  35 +#define MDSCR_WL_EN (1 << 9)
  36 +#define CMD_NORMAL (0 << 4)
  37 +#define CMD_PRECHARGE (1 << 4)
  38 +#define CMD_AUTO_REFRESH (2 << 4)
  39 +#define CMD_LOAD_MODE_REG (3 << 4)
  40 +#define CMD_ZQ_CALIBRATION (4 << 4)
  41 +#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
  42 +#define CMD_MRR (6 << 4)
67 43 #define CMD_BANK_ADDR_0 0x0
68 44 #define CMD_BANK_ADDR_1 0x1
69 45 #define CMD_BANK_ADDR_2 0x2
70 46  
... ... @@ -73,8 +49,22 @@
73 49 #define CMD_BANK_ADDR_6 0x6
74 50 #define CMD_BANK_ADDR_7 0x7
75 51  
  52 +/* MMDC Core Control Register (MDCTL) */
  53 +#define MDCTL_SDE0 (1 << 31)
  54 +#define MDCTL_SDE1 (1 << 30)
  55 +
  56 +/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
  57 +#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
  58 +
  59 +/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
  60 +#define MMDC_MPMUR0_FRC_MSR (1 << 11)
  61 +
  62 +/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
  63 +/* default 64 for a quarter cycle delay */
  64 +#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
  65 +
76 66 /* MMDC Registers */
77   -struct mmdc_p_regs {
  67 +struct mmdc_regs {
78 68 u32 mdctl;
79 69 u32 mdpdc;
80 70 u32 mdotc;
... ... @@ -120,7 +110,10 @@
120 110 u32 mprddqby1dl;
121 111 u32 mprddqby2dl;
122 112 u32 mprddqby3dl;
123   - u32 res5[4];
  113 + u32 mpwrdqby0dl;
  114 + u32 mpwrdqby1dl;
  115 + u32 mpwrdqby2dl;
  116 + u32 mpwrdqby3dl;
124 117 u32 mpdgctrl0;
125 118 u32 mpdgctrl1;
126 119 u32 mpdgdlst0;
... ... @@ -156,6 +149,12 @@
156 149 u32 mpwrcadl;
157 150 u32 mpdccr;
158 151 };
  152 +
  153 +void mmdc_init(void);
  154 +
  155 +#if !defined(CONFIG_MMDC_MDCTL)
  156 +#error Must configure board-specific timing CONFIG_MMDC_* in <board>.h for MMDC
  157 +#endif
159 158  
160 159 #endif /* FSL_MMDC_H */