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Commit ba932bc846e8f44b7b61fcaac41e0be907d1303e

Authored by Chris Brandt
Committed by Marek Vasut
1 parent 3529596442
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: dts: renesas: Add RZ/A1 GR-Peach board 

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 11 changed files with 513 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ ba932bc
... ... @@ -603,6 +603,9 @@
603 603 r8a77990-ebisu-u-boot.dtb \
604 604 r8a77995-draak-u-boot.dtb
605 605  
  606 +dtb-$(CONFIG_RZA1) += \
  607 + r7s72100-gr-peach-u-boot.dtb
  608 +
606 609 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
607 610 keystone-k2l-evm.dtb \
608 611 keystone-k2e-evm.dtb \
arch/arm/dts/r7s72100-gr-peach-u-boot.dts
Diff comments   View file @ ba932bc
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Device Tree Source extras for U-Boot for the GR Peach board
  4 + *
  5 + * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
  6 + */
  7 +
  8 +#include "r7s72100-gr-peach.dts"
  9 +
  10 +/ {
  11 + aliases {
  12 + spi0 = &rpc;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +
  19 + leds {
  20 + led1 {
  21 + label = "peach:bottom:red";
  22 + };
  23 +
  24 + led-red {
  25 + label = "peach:tri:red";
  26 + gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
  27 + };
  28 +
  29 + led-green {
  30 + label = "peach:tri:green";
  31 + gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
  32 + };
  33 +
  34 + led-blue {
  35 + label = "peach:tri:blue";
  36 + gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
  37 + };
  38 + };
  39 +
  40 + rpc: rpc@0xee200000 {
  41 + compatible = "renesas,rpc-r7s72100", "renesas,rpc";
  42 + reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
  43 + bank-width = <2>;
  44 + num-cs = <1>;
  45 + status = "okay";
  46 + spi-max-frequency = <50000000>;
  47 + #address-cells = <1>;
  48 + #size-cells = <0>;
  49 +
  50 + flash0: spi-flash@0 {
  51 + #address-cells = <1>;
  52 + #size-cells = <1>;
  53 + compatible = "jedec,spi-nor";
  54 + spi-max-frequency = <50000000>;
  55 + spi-tx-bus-width = <1>;
  56 + spi-rx-bus-width = <1>;
  57 + reg = <0>;
  58 + status = "okay";
  59 + };
  60 + };
  61 +};
  62 +
  63 +&ostm0 {
  64 + u-boot,dm-pre-reloc;
  65 +};
  66 +
  67 +&pinctrl {
  68 + u-boot,dm-pre-reloc;
  69 +};
  70 +
  71 +&scif2 {
  72 + u-boot,dm-pre-reloc;
  73 + clock = <66666666>; /* ToDo: Replace by DM clock driver */
  74 +};
  75 +
  76 +&scif2_pins {
  77 + u-boot,dm-pre-reloc;
  78 +};
arch/arm/dts/r7s72100-gr-peach.dts
Diff comments   View file @ ba932bc
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Device Tree Source for the GR-Peach board
  4 + *
  5 + * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
  6 + * Copyright (C) 2016 Renesas Electronics
  7 + */
  8 +
  9 +/dts-v1/;
  10 +#include "r7s72100.dtsi"
  11 +#include <dt-bindings/gpio/gpio.h>
  12 +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
  13 +
  14 +/ {
  15 + model = "GR-Peach";
  16 + compatible = "renesas,gr-peach", "renesas,r7s72100";
  17 +
  18 + aliases {
  19 + serial0 = &scif2;
  20 + };
  21 +
  22 + chosen {
  23 + bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
  24 + stdout-path = "serial0:115200n8";
  25 + };
  26 +
  27 + memory@20000000 {
  28 + device_type = "memory";
  29 + reg = <0x20000000 0x00a00000>;
  30 + };
  31 +
  32 + lbsc {
  33 + #address-cells = <1>;
  34 + #size-cells = <1>;
  35 + };
  36 +
  37 + flash@18000000 {
  38 + compatible = "mtd-rom";
  39 + probe-type = "map_rom";
  40 + reg = <0x18000000 0x00800000>;
  41 + bank-width = <4>;
  42 + device-width = <1>;
  43 +
  44 + #address-cells = <1>;
  45 + #size-cells = <1>;
  46 +
  47 + rootfs@600000 {
  48 + label = "rootfs";
  49 + reg = <0x00600000 0x00200000>;
  50 + };
  51 + };
  52 +
  53 + leds {
  54 + status = "okay";
  55 + compatible = "gpio-leds";
  56 +
  57 + led1 {
  58 + gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
  59 + };
  60 + };
  61 +};
  62 +
  63 +&pinctrl {
  64 + scif2_pins: serial2 {
  65 + /* P6_2 as RxD2; P6_3 as TxD2 */
  66 + pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
  67 + };
  68 +
  69 + ether_pins: ether {
  70 + /* Ethernet on Ports 1,3,5,10 */
  71 + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
  72 + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
  73 + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
  74 + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
  75 + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
  76 + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
  77 + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
  78 + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
  79 + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
  80 + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
  81 + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
  82 + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
  83 + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
  84 + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
  85 + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
  86 + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
  87 + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
  88 + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
  89 + };
  90 +};
  91 +
  92 +&extal_clk {
  93 + clock-frequency = <13333000>;
  94 +};
  95 +
  96 +&usb_x1_clk {
  97 + clock-frequency = <48000000>;
  98 +};
  99 +
  100 +&mtu2 {
  101 + status = "okay";
  102 +};
  103 +
  104 +&ostm0 {
  105 + status = "okay";
  106 +};
  107 +
  108 +&ostm1 {
  109 + status = "okay";
  110 +};
  111 +
  112 +&scif2 {
  113 + pinctrl-names = "default";
  114 + pinctrl-0 = <&scif2_pins>;
  115 +
  116 + status = "okay";
  117 +};
  118 +
  119 +&ether {
  120 + pinctrl-names = "default";
  121 + pinctrl-0 = <&ether_pins>;
  122 +
  123 + status = "okay";
  124 +
  125 + renesas,no-ether-link;
  126 + phy-handle = <&phy0>;
  127 +
  128 + phy0: ethernet-phy@0 {
  129 + reg = <0>;
  130 +
  131 + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
  132 + reset-delay-us = <5>;
  133 + };
  134 +};
arch/arm/mach-rmobile/Kconfig.rza1
Diff comments   View file @ ba932bc
... ... @@ -13,10 +13,17 @@
13 13 choice
14 14 prompt "Renesas RZ/A1 board select"
15 15  
  16 +# Renesas Supported Boards
  17 +config TARGET_GRPEACH
  18 + bool "GR-PEACH board"
  19 +
16 20 endchoice
17 21  
18 22 config SYS_SOC
19 23 default "rmobile"
  24 +
  25 +# Renesas Supported Boards
  26 +source "board/renesas/grpeach/Kconfig"
20 27  
21 28 endif
board/renesas/grpeach/Kconfig
Diff comments   View file @ ba932bc
  1 +if TARGET_GRPEACH
  2 +
  3 +config SYS_BOARD
  4 + default "grpeach"
  5 +
  6 +config SYS_VENDOR
  7 + default "renesas"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "grpeach"
  11 +
  12 +endif
board/renesas/grpeach/MAINTAINERS
Diff comments   View file @ ba932bc
  1 +GRPEACH BOARD
  2 +M: Marek Vasut <marek.vasut@gmail.com>
  3 +S: Maintained
  4 +F: board/renesas/grpeach/
  5 +F: include/configs/grpeach.h
  6 +F: configs/grpeach_defconfig
board/renesas/grpeach/Makefile
Diff comments   View file @ ba932bc
  1 +#
  2 +# Copyright (C) 2017 Renesas Electronics
  3 +# Copyright (C) 2017 Chris Brandt
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +
  7 +obj-y := grpeach.o
  8 +obj-y += lowlevel_init.o
board/renesas/grpeach/grpeach.c
Diff comments   View file @ ba932bc
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright (C) 2017 Renesas Electronics
  4 + * Copyright (C) Chris Brandt
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/sys_proto.h>
  10 +
  11 +#define RZA1_WDT_BASE 0xfcfe0000
  12 +#define WTCSR 0x00
  13 +#define WTCNT 0x02
  14 +#define WRCSR 0x04
  15 +
  16 +DECLARE_GLOBAL_DATA_PTR;
  17 +
  18 +int board_init(void)
  19 +{
  20 + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  21 +
  22 + return 0;
  23 +}
  24 +
  25 +int dram_init(void)
  26 +{
  27 + if (fdtdec_setup_mem_size_base() != 0)
  28 + return -EINVAL;
  29 +
  30 + return 0;
  31 +}
  32 +
  33 +int dram_init_banksize(void)
  34 +{
  35 + fdtdec_setup_memory_banksize();
  36 +
  37 + return 0;
  38 +}
  39 +
  40 +void reset_cpu(ulong addr)
  41 +{
  42 + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */
  43 + readb(RZA1_WDT_BASE + WRCSR);
  44 +
  45 + writew(0xa500, RZA1_WDT_BASE + WRCSR);
  46 + writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
  47 + writew(0x5a00, RZA1_WDT_BASE + WTCNT);
  48 + writew(0xa578, RZA1_WDT_BASE + WTCSR);
  49 +
  50 + for (;;)
  51 + asm volatile("wfi");
  52 +}
board/renesas/grpeach/lowlevel_init.S
Diff comments   View file @ ba932bc
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright (C) 2017 Renesas Electronics
  4 + * Copyright (C) 2017 Chris Brandt
  5 + */
  6 +#include <config.h>
  7 +#include <version.h>
  8 +#include <asm/macro.h>
  9 +
  10 +/* Watchdog Registers */
  11 +#define RZA1_WDT_BASE 0xFCFE0000
  12 +#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
  13 +#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
  14 +#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
  15 +
  16 +/* Standby controller registers (chapter 55) */
  17 +#define RZA1_STBCR_BASE 0xFCFE0020
  18 +#define STBCR1 (RZA1_STBCR_BASE + 0x00)
  19 +#define STBCR2 (RZA1_STBCR_BASE + 0x04)
  20 +#define STBCR3 (RZA1_STBCR_BASE + 0x400)
  21 +#define STBCR4 (RZA1_STBCR_BASE + 0x404)
  22 +#define STBCR5 (RZA1_STBCR_BASE + 0x408)
  23 +#define STBCR6 (RZA1_STBCR_BASE + 0x40c)
  24 +#define STBCR7 (RZA1_STBCR_BASE + 0x410)
  25 +#define STBCR8 (RZA1_STBCR_BASE + 0x414)
  26 +#define STBCR9 (RZA1_STBCR_BASE + 0x418)
  27 +#define STBCR10 (RZA1_STBCR_BASE + 0x41c)
  28 +#define STBCR11 (RZA1_STBCR_BASE + 0x420)
  29 +#define STBCR12 (RZA1_STBCR_BASE + 0x424)
  30 +#define STBCR13 (RZA1_STBCR_BASE + 0x450)
  31 +
  32 +/* Clock Registers */
  33 +#define RZA1_FRQCR_BASE 0xFCFE0010
  34 +#define FRQCR (RZA1_FRQCR_BASE + 0x00)
  35 +#define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
  36 +
  37 +#define SYSCR1 0xFCFE0400 /* System control register 1 */
  38 +#define SYSCR2 0xFCFE0404 /* System control register 2 */
  39 +#define SYSCR3 0xFCFE0408 /* System control register 3 */
  40 +
  41 +/* Disable WDT */
  42 +#define WTCSR_D 0xA518
  43 +#define WTCNT_D 0x5A00
  44 +
  45 +/* Enable all peripheral clocks */
  46 +#define STBCR3_D 0x00000000
  47 +#define STBCR4_D 0x00000000
  48 +#define STBCR5_D 0x00000000
  49 +#define STBCR6_D 0x00000000
  50 +#define STBCR7_D 0x00000024
  51 +#define STBCR8_D 0x00000005
  52 +#define STBCR9_D 0x00000000
  53 +#define STBCR10_D 0x00000000
  54 +#define STBCR11_D 0x000000c0
  55 +#define STBCR12_D 0x000000f0
  56 +
  57 +/*
  58 + * Set all system clocks to full speed.
  59 + * On reset, the CPU will be running at 1/2 speed.
  60 + * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
  61 + */
  62 +#define FRQCR_D 0x0035
  63 +#define FRQCR2_D 0x0001
  64 +
  65 + .global lowlevel_init
  66 +
  67 + .text
  68 + .align 2
  69 +
  70 +lowlevel_init:
  71 + /* PL310 init */
  72 + write32 0x3fffff80, 0x00000001
  73 +
  74 + /* Disable WDT */
  75 + write16 WTCSR, WTCSR_D
  76 + write16 WTCNT, WTCNT_D
  77 +
  78 + /* Set clocks */
  79 + write16 FRQCR, FRQCR_D
  80 + write16 FRQCR2, FRQCR2_D
  81 +
  82 + /* Enable all peripherals(Standby Control) */
  83 + write8 STBCR3, STBCR3_D
  84 + write8 STBCR4, STBCR4_D
  85 + write8 STBCR5, STBCR5_D
  86 + write8 STBCR6, STBCR6_D
  87 + write8 STBCR7, STBCR7_D
  88 + write8 STBCR8, STBCR8_D
  89 + write8 STBCR9, STBCR9_D
  90 + write8 STBCR10, STBCR10_D
  91 + write8 STBCR11, STBCR11_D
  92 + write8 STBCR12, STBCR12_D
  93 +
  94 + /* For serial booting, enable read ahead caching to speed things up */
  95 +#define DRCR_0 0x3FEFA00C
  96 + write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
  97 +
  98 + /* Enable all internal RAM */
  99 + write8 SYSCR1, 0xFF
  100 + write8 SYSCR2, 0xFF
  101 + write8 SYSCR3, 0xFF
  102 +
  103 + nop
  104 + /* back to arch calling code */
  105 + mov pc, lr
  106 +
  107 + .align 4
configs/grpeach_defconfig
Diff comments   View file @ ba932bc
  1 +CONFIG_ARM=y
  2 +# CONFIG_SPL_SYS_THUMB_BUILD is not set
  3 +CONFIG_ARCH_RMOBILE=y
  4 +CONFIG_SYS_TEXT_BASE=0x18000000
  5 +CONFIG_RZA1=y
  6 +CONFIG_NR_DRAM_BANKS=1
  7 +CONFIG_BOOTDELAY=3
  8 +# CONFIG_DISPLAY_CPUINFO is not set
  9 +CONFIG_HUSH_PARSER=y
  10 +# CONFIG_CMD_ELF is not set
  11 +CONFIG_CMD_GPIO=y
  12 +CONFIG_CMD_SF=y
  13 +CONFIG_CMD_DHCP=y
  14 +CONFIG_CMD_MII=y
  15 +CONFIG_CMD_PING=y
  16 +CONFIG_CMD_SNTP=y
  17 +CONFIG_CMD_CACHE=y
  18 +CONFIG_CMD_FAT=y
  19 +CONFIG_CMD_FS_GENERIC=y
  20 +CONFIG_MAC_PARTITION=y
  21 +CONFIG_OF_CONTROL=y
  22 +CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
  23 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  24 +CONFIG_USE_ENV_SPI_BUS=y
  25 +CONFIG_ENV_SPI_BUS=0
  26 +CONFIG_USE_ENV_SPI_CS=y
  27 +CONFIG_ENV_SPI_CS=0
  28 +CONFIG_USE_ENV_SPI_MAX_HZ=y
  29 +CONFIG_ENV_SPI_MAX_HZ=50000000
  30 +CONFIG_USE_ENV_SPI_MODE=y
  31 +CONFIG_ENV_SPI_MODE=0x0
  32 +CONFIG_NET_RANDOM_ETHADDR=y
  33 +CONFIG_HAVE_BLOCK_DEVICE=y
  34 +CONFIG_DM_GPIO=y
  35 +CONFIG_RZA1_GPIO=y
  36 +CONFIG_LED=y
  37 +CONFIG_LED_GPIO=y
  38 +# CONFIG_MMC is not set
  39 +CONFIG_DM_SPI_FLASH=y
  40 +CONFIG_SPI_FLASH=y
  41 +CONFIG_SPI_FLASH_MACRONIX=y
  42 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  43 +CONFIG_DM_ETH=y
  44 +CONFIG_SH_ETHER=y
  45 +CONFIG_PINCTRL=y
  46 +CONFIG_SCIF_CONSOLE=y
  47 +CONFIG_SPI=y
  48 +CONFIG_DM_SPI=y
  49 +CONFIG_RENESAS_RPC_SPI=y
  50 +CONFIG_TIMER=y
  51 +CONFIG_RENESAS_OSTM_TIMER=y
  52 +CONFIG_OF_LIBFDT_OVERLAY=y
  53 +# CONFIG_EFI_LOADER is not set
include/configs/grpeach.h
Diff comments   View file @ ba932bc
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Configuration settings for the Renesas GRPEACH board
  4 + *
  5 + * Copyright (C) 2017-2019 Renesas Electronics
  6 + */
  7 +
  8 +#ifndef __GRPEACH_H
  9 +#define __GRPEACH_H
  10 +
  11 +/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
  12 +#define CONFIG_SYS_CLK_FREQ 66666666
  13 +
  14 +/* Serial Console */
  15 +#define CONFIG_BAUDRATE 115200
  16 +
  17 +/* Miscellaneous */
  18 +#define CONFIG_SYS_PBSIZE 256
  19 +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
  20 +#define CONFIG_CMDLINE_TAG
  21 +#define CONFIG_ARCH_CPU_INIT
  22 +
  23 +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
  24 +#define CONFIG_SYS_SDRAM_BASE 0x20000000
  25 +#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
  26 +#define CONFIG_SYS_INIT_SP_ADDR \
  27 + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
  28 +#define CONFIG_SYS_LOAD_ADDR \
  29 + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
  30 +
  31 +#define CONFIG_ENV_OVERWRITE 1
  32 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  33 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  34 +#define CONFIG_ENV_OFFSET 0xc0000
  35 +
  36 +/* Malloc */
  37 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  38 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  39 +
  40 +/* Kernel Boot */
  41 +#define CONFIG_BOOTARGS "ignore_loglevel"
  42 +
  43 +/* Network interface */
  44 +#define CONFIG_SH_ETHER_USE_PORT 0
  45 +#define CONFIG_SH_ETHER_PHY_ADDR 0
  46 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  47 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK
  48 +#define CONFIG_SH_ETHER_CACHE_INVALIDATE
  49 +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
  50 +#define CONFIG_BITBANGMII
  51 +#define CONFIG_BITBANGMII_MULTI
  52 +
  53 +#endif /* __GRPEACH_H */