Eric Lee / smarc-uboot

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Commit bafcf2db4176940953a96339025d7b06e96cb22e

Authored by Wadim Egorov
Committed by Philipp Tomsich
1 parent ad98f882e8
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board 

The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Showing 11 changed files with 981 additions and 0 deletions Inline Diff

arch/arm/dts/Makefile
Diff comments   View file @ bafcf2d
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ 5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
6 at91sam9g20-taurus.dtb \ 6 at91sam9g20-taurus.dtb \
7 at91sam9g45-corvus.dtb \ 7 at91sam9g45-corvus.dtb \
8 at91sam9g45-gurnard.dtb 8 at91sam9g45-gurnard.dtb
9 9
10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb 10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb 11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ 12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
13 exynos4210-smdkv310.dtb \ 13 exynos4210-smdkv310.dtb \
14 exynos4210-universal_c210.dtb \ 14 exynos4210-universal_c210.dtb \
15 exynos4210-trats.dtb \ 15 exynos4210-trats.dtb \
16 exynos4412-trats2.dtb \ 16 exynos4412-trats2.dtb \
17 exynos4412-odroid.dtb 17 exynos4412-odroid.dtb
18 18
19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb 19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
20 20
21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ 21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
22 exynos5250-snow.dtb \ 22 exynos5250-snow.dtb \
23 exynos5250-spring.dtb \ 23 exynos5250-spring.dtb \
24 exynos5250-smdk5250.dtb \ 24 exynos5250-smdk5250.dtb \
25 exynos5420-smdk5420.dtb \ 25 exynos5420-smdk5420.dtb \
26 exynos5420-peach-pit.dtb \ 26 exynos5420-peach-pit.dtb \
27 exynos5800-peach-pi.dtb \ 27 exynos5800-peach-pi.dtb \
28 exynos5422-odroidxu3.dtb 28 exynos5422-odroidxu3.dtb
29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb 29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
31 rk3036-sdk.dtb \ 31 rk3036-sdk.dtb \
32 rk3188-radxarock.dtb \ 32 rk3188-radxarock.dtb \
33 rk3288-evb.dtb \ 33 rk3288-evb.dtb \
34 rk3288-fennec.dtb \ 34 rk3288-fennec.dtb \
35 rk3288-firefly.dtb \ 35 rk3288-firefly.dtb \
36 rk3288-miqi.dtb \ 36 rk3288-miqi.dtb \
37 rk3288-phycore-rdk.dtb \
37 rk3288-popmetal.dtb \ 38 rk3288-popmetal.dtb \
38 rk3288-rock2-square.dtb \ 39 rk3288-rock2-square.dtb \
39 rk3288-tinker.dtb \ 40 rk3288-tinker.dtb \
40 rk3288-veyron-jerry.dtb \ 41 rk3288-veyron-jerry.dtb \
41 rk3288-veyron-mickey.dtb \ 42 rk3288-veyron-mickey.dtb \
42 rk3288-veyron-minnie.dtb \ 43 rk3288-veyron-minnie.dtb \
43 rk3328-evb.dtb \ 44 rk3328-evb.dtb \
44 rk3368-sheep.dtb \ 45 rk3368-sheep.dtb \
45 rk3368-geekbox.dtb \ 46 rk3368-geekbox.dtb \
46 rk3368-px5-evb.dtb \ 47 rk3368-px5-evb.dtb \
47 rk3399-evb.dtb \ 48 rk3399-evb.dtb \
48 rk3399-firefly.dtb \ 49 rk3399-firefly.dtb \
49 rk3399-puma-ddr1333.dtb \ 50 rk3399-puma-ddr1333.dtb \
50 rk3399-puma-ddr1600.dtb \ 51 rk3399-puma-ddr1600.dtb \
51 rk3399-puma-ddr1866.dtb \ 52 rk3399-puma-ddr1866.dtb \
52 rv1108-evb.dtb 53 rv1108-evb.dtb
53 dtb-$(CONFIG_ARCH_MESON) += \ 54 dtb-$(CONFIG_ARCH_MESON) += \
54 meson-gxbb-odroidc2.dtb 55 meson-gxbb-odroidc2.dtb
55 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ 56 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
56 tegra20-medcom-wide.dtb \ 57 tegra20-medcom-wide.dtb \
57 tegra20-paz00.dtb \ 58 tegra20-paz00.dtb \
58 tegra20-plutux.dtb \ 59 tegra20-plutux.dtb \
59 tegra20-seaboard.dtb \ 60 tegra20-seaboard.dtb \
60 tegra20-tec.dtb \ 61 tegra20-tec.dtb \
61 tegra20-trimslice.dtb \ 62 tegra20-trimslice.dtb \
62 tegra20-ventana.dtb \ 63 tegra20-ventana.dtb \
63 tegra20-colibri.dtb \ 64 tegra20-colibri.dtb \
64 tegra30-apalis.dtb \ 65 tegra30-apalis.dtb \
65 tegra30-beaver.dtb \ 66 tegra30-beaver.dtb \
66 tegra30-cardhu.dtb \ 67 tegra30-cardhu.dtb \
67 tegra30-colibri.dtb \ 68 tegra30-colibri.dtb \
68 tegra30-tec-ng.dtb \ 69 tegra30-tec-ng.dtb \
69 tegra114-dalmore.dtb \ 70 tegra114-dalmore.dtb \
70 tegra124-apalis.dtb \ 71 tegra124-apalis.dtb \
71 tegra124-jetson-tk1.dtb \ 72 tegra124-jetson-tk1.dtb \
72 tegra124-nyan-big.dtb \ 73 tegra124-nyan-big.dtb \
73 tegra124-cei-tk1-som.dtb \ 74 tegra124-cei-tk1-som.dtb \
74 tegra124-venice2.dtb \ 75 tegra124-venice2.dtb \
75 tegra186-p2771-0000-000.dtb \ 76 tegra186-p2771-0000-000.dtb \
76 tegra186-p2771-0000-500.dtb \ 77 tegra186-p2771-0000-500.dtb \
77 tegra210-e2220-1170.dtb \ 78 tegra210-e2220-1170.dtb \
78 tegra210-p2371-0000.dtb \ 79 tegra210-p2371-0000.dtb \
79 tegra210-p2371-2180.dtb \ 80 tegra210-p2371-2180.dtb \
80 tegra210-p2571.dtb 81 tegra210-p2571.dtb
81 82
82 dtb-$(CONFIG_ARCH_MVEBU) += \ 83 dtb-$(CONFIG_ARCH_MVEBU) += \
83 armada-3720-db.dtb \ 84 armada-3720-db.dtb \
84 armada-3720-espressobin.dtb \ 85 armada-3720-espressobin.dtb \
85 armada-375-db.dtb \ 86 armada-375-db.dtb \
86 armada-388-clearfog.dtb \ 87 armada-388-clearfog.dtb \
87 armada-388-gp.dtb \ 88 armada-388-gp.dtb \
88 armada-385-amc.dtb \ 89 armada-385-amc.dtb \
89 armada-7040-db.dtb \ 90 armada-7040-db.dtb \
90 armada-7040-db-nand.dtb \ 91 armada-7040-db-nand.dtb \
91 armada-8040-db.dtb \ 92 armada-8040-db.dtb \
92 armada-8040-mcbin.dtb \ 93 armada-8040-mcbin.dtb \
93 armada-xp-gp.dtb \ 94 armada-xp-gp.dtb \
94 armada-xp-maxbcm.dtb \ 95 armada-xp-maxbcm.dtb \
95 armada-xp-synology-ds414.dtb \ 96 armada-xp-synology-ds414.dtb \
96 armada-xp-theadorable.dtb \ 97 armada-xp-theadorable.dtb \
97 armada-38x-controlcenterdc.dtb 98 armada-38x-controlcenterdc.dtb
98 99
99 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ 100 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
100 uniphier-ld11-global.dtb \ 101 uniphier-ld11-global.dtb \
101 uniphier-ld11-ref.dtb 102 uniphier-ld11-ref.dtb
102 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ 103 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
103 uniphier-ld20-global.dtb \ 104 uniphier-ld20-global.dtb \
104 uniphier-ld20-ref.dtb 105 uniphier-ld20-ref.dtb
105 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ 106 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
106 uniphier-ld4-ref.dtb 107 uniphier-ld4-ref.dtb
107 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \ 108 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \
108 uniphier-ld6b-ref.dtb 109 uniphier-ld6b-ref.dtb
109 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \ 110 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \
110 uniphier-pro4-ace.dtb \ 111 uniphier-pro4-ace.dtb \
111 uniphier-pro4-ref.dtb \ 112 uniphier-pro4-ref.dtb \
112 uniphier-pro4-sanji.dtb 113 uniphier-pro4-sanji.dtb
113 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \ 114 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \
114 uniphier-pro5-4kbox.dtb 115 uniphier-pro5-4kbox.dtb
115 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ 116 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
116 uniphier-pxs2-gentil.dtb \ 117 uniphier-pxs2-gentil.dtb \
117 uniphier-pxs2-vodka.dtb 118 uniphier-pxs2-vodka.dtb
118 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ 119 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
119 uniphier-pxs3-ref.dtb 120 uniphier-pxs3-ref.dtb
120 dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \ 121 dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
121 uniphier-sld3-ref.dtb 122 uniphier-sld3-ref.dtb
122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ 123 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
123 uniphier-sld8-ref.dtb 124 uniphier-sld8-ref.dtb
124 125
125 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ 126 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
126 zynq-zc706.dtb \ 127 zynq-zc706.dtb \
127 zynq-zed.dtb \ 128 zynq-zed.dtb \
128 zynq-zybo.dtb \ 129 zynq-zybo.dtb \
129 zynq-microzed.dtb \ 130 zynq-microzed.dtb \
130 zynq-picozed.dtb \ 131 zynq-picozed.dtb \
131 zynq-topic-miami.dtb \ 132 zynq-topic-miami.dtb \
132 zynq-topic-miamilite.dtb \ 133 zynq-topic-miamilite.dtb \
133 zynq-topic-miamiplus.dtb \ 134 zynq-topic-miamiplus.dtb \
134 zynq-zc770-xm010.dtb \ 135 zynq-zc770-xm010.dtb \
135 zynq-zc770-xm011.dtb \ 136 zynq-zc770-xm011.dtb \
136 zynq-zc770-xm012.dtb \ 137 zynq-zc770-xm012.dtb \
137 zynq-zc770-xm013.dtb 138 zynq-zc770-xm013.dtb
138 dtb-$(CONFIG_ARCH_ZYNQMP) += \ 139 dtb-$(CONFIG_ARCH_ZYNQMP) += \
139 zynqmp-ep108.dtb \ 140 zynqmp-ep108.dtb \
140 zynqmp-zcu102.dtb \ 141 zynqmp-zcu102.dtb \
141 zynqmp-zcu102-revB.dtb \ 142 zynqmp-zcu102-revB.dtb \
142 zynqmp-zc1751-xm015-dc1.dtb \ 143 zynqmp-zc1751-xm015-dc1.dtb \
143 zynqmp-zc1751-xm016-dc2.dtb \ 144 zynqmp-zc1751-xm016-dc2.dtb \
144 zynqmp-zc1751-xm018-dc4.dtb \ 145 zynqmp-zc1751-xm018-dc4.dtb \
145 zynqmp-zc1751-xm019-dc5.dtb 146 zynqmp-zc1751-xm019-dc5.dtb
146 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ 147 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
147 am335x-draco.dtb \ 148 am335x-draco.dtb \
148 am335x-evm.dtb \ 149 am335x-evm.dtb \
149 am335x-evmsk.dtb \ 150 am335x-evmsk.dtb \
150 am335x-bonegreen.dtb \ 151 am335x-bonegreen.dtb \
151 am335x-icev2.dtb \ 152 am335x-icev2.dtb \
152 am335x-pxm50.dtb \ 153 am335x-pxm50.dtb \
153 am335x-rut.dtb 154 am335x-rut.dtb
154 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ 155 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
155 am43x-epos-evm.dtb \ 156 am43x-epos-evm.dtb \
156 am437x-idk-evm.dtb 157 am437x-idk-evm.dtb
157 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb 158 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
158 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb 159 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
159 160
160 dtb-$(CONFIG_ARCH_SOCFPGA) += \ 161 dtb-$(CONFIG_ARCH_SOCFPGA) += \
161 socfpga_arria10_socdk_sdmmc.dtb \ 162 socfpga_arria10_socdk_sdmmc.dtb \
162 socfpga_arria5_socdk.dtb \ 163 socfpga_arria5_socdk.dtb \
163 socfpga_cyclone5_is1.dtb \ 164 socfpga_cyclone5_is1.dtb \
164 socfpga_cyclone5_mcvevk.dtb \ 165 socfpga_cyclone5_mcvevk.dtb \
165 socfpga_cyclone5_socdk.dtb \ 166 socfpga_cyclone5_socdk.dtb \
166 socfpga_cyclone5_de0_nano_soc.dtb \ 167 socfpga_cyclone5_de0_nano_soc.dtb \
167 socfpga_cyclone5_de1_soc.dtb \ 168 socfpga_cyclone5_de1_soc.dtb \
168 socfpga_cyclone5_de10_nano.dtb \ 169 socfpga_cyclone5_de10_nano.dtb \
169 socfpga_cyclone5_sockit.dtb \ 170 socfpga_cyclone5_sockit.dtb \
170 socfpga_cyclone5_socrates.dtb \ 171 socfpga_cyclone5_socrates.dtb \
171 socfpga_cyclone5_sr1500.dtb \ 172 socfpga_cyclone5_sr1500.dtb \
172 socfpga_cyclone5_vining_fpga.dtb 173 socfpga_cyclone5_vining_fpga.dtb
173 174
174 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 175 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
175 dra72-evm-revc.dtb dra71-evm.dtb 176 dra72-evm-revc.dtb dra71-evm.dtb
176 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 177 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
177 am57xx-beagle-x15-revb1.dtb \ 178 am57xx-beagle-x15-revb1.dtb \
178 am572x-idk.dtb \ 179 am572x-idk.dtb \
179 am571x-idk.dtb 180 am571x-idk.dtb
180 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb 181 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
181 182
182 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ 183 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
183 ls1021a-qds-lpuart.dtb \ 184 ls1021a-qds-lpuart.dtb \
184 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ 185 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
185 ls1021a-iot-duart.dtb 186 ls1021a-iot-duart.dtb
186 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ 187 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
187 fsl-ls2080a-rdb.dtb \ 188 fsl-ls2080a-rdb.dtb \
188 fsl-ls2081a-rdb.dtb \ 189 fsl-ls2081a-rdb.dtb \
189 fsl-ls2088a-rdb-qspi.dtb 190 fsl-ls2088a-rdb-qspi.dtb
190 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ 191 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
191 fsl-ls1043a-qds-lpuart.dtb \ 192 fsl-ls1043a-qds-lpuart.dtb \
192 fsl-ls1043a-rdb.dtb \ 193 fsl-ls1043a-rdb.dtb \
193 fsl-ls1046a-qds-duart.dtb \ 194 fsl-ls1046a-qds-duart.dtb \
194 fsl-ls1046a-qds-lpuart.dtb \ 195 fsl-ls1046a-qds-lpuart.dtb \
195 fsl-ls1046a-rdb.dtb \ 196 fsl-ls1046a-rdb.dtb \
196 fsl-ls1012a-qds.dtb \ 197 fsl-ls1012a-qds.dtb \
197 fsl-ls1012a-rdb.dtb \ 198 fsl-ls1012a-rdb.dtb \
198 fsl-ls1012a-frdm.dtb 199 fsl-ls1012a-frdm.dtb
199 200
200 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb 201 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
201 202
202 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ 203 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
203 stm32f769-disco.dtb 204 stm32f769-disco.dtb
204 205
205 dtb-$(CONFIG_MACH_SUN4I) += \ 206 dtb-$(CONFIG_MACH_SUN4I) += \
206 sun4i-a10-a1000.dtb \ 207 sun4i-a10-a1000.dtb \
207 sun4i-a10-ba10-tvbox.dtb \ 208 sun4i-a10-ba10-tvbox.dtb \
208 sun4i-a10-chuwi-v7-cw0825.dtb \ 209 sun4i-a10-chuwi-v7-cw0825.dtb \
209 sun4i-a10-cubieboard.dtb \ 210 sun4i-a10-cubieboard.dtb \
210 sun4i-a10-dserve-dsrv9703c.dtb \ 211 sun4i-a10-dserve-dsrv9703c.dtb \
211 sun4i-a10-gemei-g9.dtb \ 212 sun4i-a10-gemei-g9.dtb \
212 sun4i-a10-hackberry.dtb \ 213 sun4i-a10-hackberry.dtb \
213 sun4i-a10-hyundai-a7hd.dtb \ 214 sun4i-a10-hyundai-a7hd.dtb \
214 sun4i-a10-inet1.dtb \ 215 sun4i-a10-inet1.dtb \
215 sun4i-a10-inet-3f.dtb \ 216 sun4i-a10-inet-3f.dtb \
216 sun4i-a10-inet-3w.dtb \ 217 sun4i-a10-inet-3w.dtb \
217 sun4i-a10-inet97fv2.dtb \ 218 sun4i-a10-inet97fv2.dtb \
218 sun4i-a10-inet9f-rev03.dtb \ 219 sun4i-a10-inet9f-rev03.dtb \
219 sun4i-a10-itead-iteaduino-plus.dtb \ 220 sun4i-a10-itead-iteaduino-plus.dtb \
220 sun4i-a10-jesurun-q5.dtb \ 221 sun4i-a10-jesurun-q5.dtb \
221 sun4i-a10-marsboard.dtb \ 222 sun4i-a10-marsboard.dtb \
222 sun4i-a10-mini-xplus.dtb \ 223 sun4i-a10-mini-xplus.dtb \
223 sun4i-a10-mk802.dtb \ 224 sun4i-a10-mk802.dtb \
224 sun4i-a10-mk802ii.dtb \ 225 sun4i-a10-mk802ii.dtb \
225 sun4i-a10-olinuxino-lime.dtb \ 226 sun4i-a10-olinuxino-lime.dtb \
226 sun4i-a10-pcduino.dtb \ 227 sun4i-a10-pcduino.dtb \
227 sun4i-a10-pcduino2.dtb \ 228 sun4i-a10-pcduino2.dtb \
228 sun4i-a10-pov-protab2-ips9.dtb 229 sun4i-a10-pov-protab2-ips9.dtb
229 dtb-$(CONFIG_MACH_SUN5I) += \ 230 dtb-$(CONFIG_MACH_SUN5I) += \
230 sun5i-a10s-auxtek-t003.dtb \ 231 sun5i-a10s-auxtek-t003.dtb \
231 sun5i-a10s-auxtek-t004.dtb \ 232 sun5i-a10s-auxtek-t004.dtb \
232 sun5i-a10s-mk802.dtb \ 233 sun5i-a10s-mk802.dtb \
233 sun5i-a10s-olinuxino-micro.dtb \ 234 sun5i-a10s-olinuxino-micro.dtb \
234 sun5i-a10s-r7-tv-dongle.dtb \ 235 sun5i-a10s-r7-tv-dongle.dtb \
235 sun5i-a10s-wobo-i5.dtb \ 236 sun5i-a10s-wobo-i5.dtb \
236 sun5i-a13-ampe-a76.dtb \ 237 sun5i-a13-ampe-a76.dtb \
237 sun5i-a13-difrnce-dit4350.dtb \ 238 sun5i-a13-difrnce-dit4350.dtb \
238 sun5i-a13-empire-electronix-d709.dtb \ 239 sun5i-a13-empire-electronix-d709.dtb \
239 sun5i-a13-empire-electronix-m712.dtb \ 240 sun5i-a13-empire-electronix-m712.dtb \
240 sun5i-a13-hsg-h702.dtb \ 241 sun5i-a13-hsg-h702.dtb \
241 sun5i-a13-inet-86vs.dtb \ 242 sun5i-a13-inet-86vs.dtb \
242 sun5i-a13-inet-98v-rev2.dtb \ 243 sun5i-a13-inet-98v-rev2.dtb \
243 sun5i-a13-olinuxino.dtb \ 244 sun5i-a13-olinuxino.dtb \
244 sun5i-a13-olinuxino-micro.dtb \ 245 sun5i-a13-olinuxino-micro.dtb \
245 sun5i-a13-q8-tablet.dtb \ 246 sun5i-a13-q8-tablet.dtb \
246 sun5i-a13-utoo-p66.dtb \ 247 sun5i-a13-utoo-p66.dtb \
247 sun5i-gr8-chip-pro.dtb \ 248 sun5i-gr8-chip-pro.dtb \
248 sun5i-r8-chip.dtb 249 sun5i-r8-chip.dtb
249 dtb-$(CONFIG_MACH_SUN6I) += \ 250 dtb-$(CONFIG_MACH_SUN6I) += \
250 sun6i-a31-app4-evb1.dtb \ 251 sun6i-a31-app4-evb1.dtb \
251 sun6i-a31-colombus.dtb \ 252 sun6i-a31-colombus.dtb \
252 sun6i-a31-hummingbird.dtb \ 253 sun6i-a31-hummingbird.dtb \
253 sun6i-a31-i7.dtb \ 254 sun6i-a31-i7.dtb \
254 sun6i-a31-m9.dtb \ 255 sun6i-a31-m9.dtb \
255 sun6i-a31-mele-a1000g-quad.dtb \ 256 sun6i-a31-mele-a1000g-quad.dtb \
256 sun6i-a31-mixtile-loftq.dtb \ 257 sun6i-a31-mixtile-loftq.dtb \
257 sun6i-a31s-colorfly-e708-q1.dtb \ 258 sun6i-a31s-colorfly-e708-q1.dtb \
258 sun6i-a31s-cs908.dtb \ 259 sun6i-a31s-cs908.dtb \
259 sun6i-a31s-inet-q972.dtb \ 260 sun6i-a31s-inet-q972.dtb \
260 sun6i-a31s-primo81.dtb \ 261 sun6i-a31s-primo81.dtb \
261 sun6i-a31s-sina31s.dtb \ 262 sun6i-a31s-sina31s.dtb \
262 sun6i-a31s-sinovoip-bpi-m2.dtb \ 263 sun6i-a31s-sinovoip-bpi-m2.dtb \
263 sun6i-a31s-yones-toptech-bs1078-v2.dtb 264 sun6i-a31s-yones-toptech-bs1078-v2.dtb
264 dtb-$(CONFIG_MACH_SUN7I) += \ 265 dtb-$(CONFIG_MACH_SUN7I) += \
265 sun7i-a20-ainol-aw1.dtb \ 266 sun7i-a20-ainol-aw1.dtb \
266 sun7i-a20-bananapi.dtb \ 267 sun7i-a20-bananapi.dtb \
267 sun7i-a20-bananapi-m1-plus.dtb \ 268 sun7i-a20-bananapi-m1-plus.dtb \
268 sun7i-a20-bananapro.dtb \ 269 sun7i-a20-bananapro.dtb \
269 sun7i-a20-cubieboard2.dtb \ 270 sun7i-a20-cubieboard2.dtb \
270 sun7i-a20-cubietruck.dtb \ 271 sun7i-a20-cubietruck.dtb \
271 sun7i-a20-hummingbird.dtb \ 272 sun7i-a20-hummingbird.dtb \
272 sun7i-a20-i12-tvbox.dtb \ 273 sun7i-a20-i12-tvbox.dtb \
273 sun7i-a20-icnova-swac.dtb \ 274 sun7i-a20-icnova-swac.dtb \
274 sun7i-a20-itead-ibox.dtb \ 275 sun7i-a20-itead-ibox.dtb \
275 sun7i-a20-lamobo-r1.dtb \ 276 sun7i-a20-lamobo-r1.dtb \
276 sun7i-a20-m3.dtb \ 277 sun7i-a20-m3.dtb \
277 sun7i-a20-m5.dtb \ 278 sun7i-a20-m5.dtb \
278 sun7i-a20-mk808c.dtb \ 279 sun7i-a20-mk808c.dtb \
279 sun7i-a20-olimex-som-evb.dtb \ 280 sun7i-a20-olimex-som-evb.dtb \
280 sun7i-a20-olinuxino-lime.dtb \ 281 sun7i-a20-olinuxino-lime.dtb \
281 sun7i-a20-olinuxino-lime2.dtb \ 282 sun7i-a20-olinuxino-lime2.dtb \
282 sun7i-a20-olinuxino-lime2-emmc.dtb \ 283 sun7i-a20-olinuxino-lime2-emmc.dtb \
283 sun7i-a20-olinuxino-micro.dtb \ 284 sun7i-a20-olinuxino-micro.dtb \
284 sun7i-a20-orangepi.dtb \ 285 sun7i-a20-orangepi.dtb \
285 sun7i-a20-orangepi-mini.dtb \ 286 sun7i-a20-orangepi-mini.dtb \
286 sun7i-a20-pcduino3.dtb \ 287 sun7i-a20-pcduino3.dtb \
287 sun7i-a20-pcduino3-nano.dtb \ 288 sun7i-a20-pcduino3-nano.dtb \
288 sun7i-a20-primo73.dtb \ 289 sun7i-a20-primo73.dtb \
289 sun7i-a20-wexler-tab7200.dtb \ 290 sun7i-a20-wexler-tab7200.dtb \
290 sun7i-a20-wits-pro-a20-dkt.dtb \ 291 sun7i-a20-wits-pro-a20-dkt.dtb \
291 sun7i-a20-yones-toptech-bd1078.dtb 292 sun7i-a20-yones-toptech-bd1078.dtb
292 dtb-$(CONFIG_MACH_SUN8I_A23) += \ 293 dtb-$(CONFIG_MACH_SUN8I_A23) += \
293 sun8i-a23-evb.dtb \ 294 sun8i-a23-evb.dtb \
294 sun8i-a23-gt90h-v4.dtb \ 295 sun8i-a23-gt90h-v4.dtb \
295 sun8i-a23-inet86dz.dtb \ 296 sun8i-a23-inet86dz.dtb \
296 sun8i-a23-polaroid-mid2407pxe03.dtb \ 297 sun8i-a23-polaroid-mid2407pxe03.dtb \
297 sun8i-a23-polaroid-mid2809pxe04.dtb \ 298 sun8i-a23-polaroid-mid2809pxe04.dtb \
298 sun8i-a23-q8-tablet.dtb 299 sun8i-a23-q8-tablet.dtb
299 dtb-$(CONFIG_MACH_SUN8I_A33) += \ 300 dtb-$(CONFIG_MACH_SUN8I_A33) += \
300 sun8i-a33-ga10h-v1.1.dtb \ 301 sun8i-a33-ga10h-v1.1.dtb \
301 sun8i-a33-inet-d978-rev2.dtb \ 302 sun8i-a33-inet-d978-rev2.dtb \
302 sun8i-a33-olinuxino.dtb \ 303 sun8i-a33-olinuxino.dtb \
303 sun8i-a33-q8-tablet.dtb \ 304 sun8i-a33-q8-tablet.dtb \
304 sun8i-a33-sinlinx-sina33.dtb \ 305 sun8i-a33-sinlinx-sina33.dtb \
305 sun8i-r16-nintendo-nes-classic-edition.dtb \ 306 sun8i-r16-nintendo-nes-classic-edition.dtb \
306 sun8i-r16-parrot.dtb 307 sun8i-r16-parrot.dtb
307 dtb-$(CONFIG_MACH_SUN8I_A83T) += \ 308 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
308 sun8i-a83t-allwinner-h8homlet-v2.dtb \ 309 sun8i-a83t-allwinner-h8homlet-v2.dtb \
309 sun8i-a83t-cubietruck-plus.dtb \ 310 sun8i-a83t-cubietruck-plus.dtb \
310 sun8i-a83t-sinovoip-bpi-m3.dtb 311 sun8i-a83t-sinovoip-bpi-m3.dtb
311 dtb-$(CONFIG_MACH_SUN8I_H3) += \ 312 dtb-$(CONFIG_MACH_SUN8I_H3) += \
312 sun8i-h2-plus-orangepi-zero.dtb \ 313 sun8i-h2-plus-orangepi-zero.dtb \
313 sun8i-h3-bananapi-m2-plus.dtb \ 314 sun8i-h3-bananapi-m2-plus.dtb \
314 sun8i-h3-orangepi-2.dtb \ 315 sun8i-h3-orangepi-2.dtb \
315 sun8i-h3-orangepi-lite.dtb \ 316 sun8i-h3-orangepi-lite.dtb \
316 sun8i-h3-orangepi-one.dtb \ 317 sun8i-h3-orangepi-one.dtb \
317 sun8i-h3-orangepi-pc.dtb \ 318 sun8i-h3-orangepi-pc.dtb \
318 sun8i-h3-orangepi-pc-plus.dtb \ 319 sun8i-h3-orangepi-pc-plus.dtb \
319 sun8i-h3-orangepi-plus.dtb \ 320 sun8i-h3-orangepi-plus.dtb \
320 sun8i-h3-orangepi-plus2e.dtb \ 321 sun8i-h3-orangepi-plus2e.dtb \
321 sun8i-h3-nanopi-m1.dtb \ 322 sun8i-h3-nanopi-m1.dtb \
322 sun8i-h3-nanopi-m1-plus.dtb \ 323 sun8i-h3-nanopi-m1-plus.dtb \
323 sun8i-h3-nanopi-neo.dtb \ 324 sun8i-h3-nanopi-neo.dtb \
324 sun8i-h3-nanopi-neo-air.dtb 325 sun8i-h3-nanopi-neo-air.dtb
325 dtb-$(CONFIG_MACH_SUN8I_R40) += \ 326 dtb-$(CONFIG_MACH_SUN8I_R40) += \
326 sun8i-r40-bananapi-m2-ultra.dtb 327 sun8i-r40-bananapi-m2-ultra.dtb
327 dtb-$(CONFIG_MACH_SUN8I_V3S) += \ 328 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
328 sun8i-v3s-licheepi-zero.dtb 329 sun8i-v3s-licheepi-zero.dtb
329 dtb-$(CONFIG_MACH_SUN50I_H5) += \ 330 dtb-$(CONFIG_MACH_SUN50I_H5) += \
330 sun50i-h5-nanopi-neo2.dtb \ 331 sun50i-h5-nanopi-neo2.dtb \
331 sun50i-h5-orangepi-pc2.dtb \ 332 sun50i-h5-orangepi-pc2.dtb \
332 sun50i-h5-orangepi-prime.dtb \ 333 sun50i-h5-orangepi-prime.dtb \
333 sun50i-h5-orangepi-zero-plus2.dtb 334 sun50i-h5-orangepi-zero-plus2.dtb
334 dtb-$(CONFIG_MACH_SUN50I) += \ 335 dtb-$(CONFIG_MACH_SUN50I) += \
335 sun50i-a64-bananapi-m64.dtb \ 336 sun50i-a64-bananapi-m64.dtb \
336 sun50i-a64-orangepi-win.dtb \ 337 sun50i-a64-orangepi-win.dtb \
337 sun50i-a64-pine64-plus.dtb \ 338 sun50i-a64-pine64-plus.dtb \
338 sun50i-a64-pine64.dtb 339 sun50i-a64-pine64.dtb
339 dtb-$(CONFIG_MACH_SUN9I) += \ 340 dtb-$(CONFIG_MACH_SUN9I) += \
340 sun9i-a80-optimus.dtb \ 341 sun9i-a80-optimus.dtb \
341 sun9i-a80-cubieboard4.dtb \ 342 sun9i-a80-cubieboard4.dtb \
342 sun9i-a80-cx-a99.dtb 343 sun9i-a80-cx-a99.dtb
343 344
344 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ 345 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
345 vf610-colibri.dtb \ 346 vf610-colibri.dtb \
346 vf610-twr.dtb \ 347 vf610-twr.dtb \
347 pcm052.dtb \ 348 pcm052.dtb \
348 bk4r1.dtb 349 bk4r1.dtb
349 350
350 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb 351 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
351 352
352 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ 353 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
353 imx6sl-evk.dtb \ 354 imx6sl-evk.dtb \
354 imx6sll-evk.dtb \ 355 imx6sll-evk.dtb \
355 imx6dl-icore.dtb \ 356 imx6dl-icore.dtb \
356 imx6dl-icore-rqs.dtb \ 357 imx6dl-icore-rqs.dtb \
357 imx6q-icore.dtb \ 358 imx6q-icore.dtb \
358 imx6q-icore-rqs.dtb \ 359 imx6q-icore-rqs.dtb \
359 imx6q-logicpd.dtb \ 360 imx6q-logicpd.dtb \
360 imx6sx-sabreauto.dtb \ 361 imx6sx-sabreauto.dtb \
361 imx6ul-geam-kit.dtb \ 362 imx6ul-geam-kit.dtb \
362 imx6ul-isiot-emmc.dtb \ 363 imx6ul-isiot-emmc.dtb \
363 imx6ul-isiot-mmc.dtb \ 364 imx6ul-isiot-mmc.dtb \
364 imx6ul-isiot-nand.dtb \ 365 imx6ul-isiot-nand.dtb \
365 imx6ul-opos6uldev.dtb 366 imx6ul-opos6uldev.dtb
366 367
367 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ 368 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
368 imx7d-sdb.dtb 369 imx7d-sdb.dtb
369 370
370 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb 371 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
371 372
372 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ 373 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
373 keystone-k2l-evm.dtb \ 374 keystone-k2l-evm.dtb \
374 keystone-k2e-evm.dtb \ 375 keystone-k2e-evm.dtb \
375 keystone-k2g-evm.dtb 376 keystone-k2g-evm.dtb
376 377
377 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb 378 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
378 379
379 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb 380 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
380 381
381 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ 382 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
382 at91sam9260ek.dtb \ 383 at91sam9260ek.dtb \
383 at91sam9g20ek.dtb \ 384 at91sam9g20ek.dtb \
384 at91sam9g20ek_2mmc.dtb 385 at91sam9g20ek_2mmc.dtb
385 386
386 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb 387 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
387 388
388 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ 389 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
389 at91sam9g15ek.dtb \ 390 at91sam9g15ek.dtb \
390 at91sam9g25ek.dtb \ 391 at91sam9g25ek.dtb \
391 at91sam9g35ek.dtb \ 392 at91sam9g35ek.dtb \
392 at91sam9x25ek.dtb \ 393 at91sam9x25ek.dtb \
393 at91sam9x35ek.dtb 394 at91sam9x35ek.dtb
394 395
395 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb 396 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
396 397
397 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ 398 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
398 logicpd-torpedo-37xx-devkit.dtb \ 399 logicpd-torpedo-37xx-devkit.dtb \
399 logicpd-som-lv-37xx-devkit.dtb 400 logicpd-som-lv-37xx-devkit.dtb
400 401
401 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ 402 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
402 at91-sama5d2_xplained.dtb 403 at91-sama5d2_xplained.dtb
403 404
404 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ 405 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
405 sama5d31ek.dtb \ 406 sama5d31ek.dtb \
406 sama5d33ek.dtb \ 407 sama5d33ek.dtb \
407 sama5d34ek.dtb \ 408 sama5d34ek.dtb \
408 sama5d35ek.dtb \ 409 sama5d35ek.dtb \
409 sama5d36ek.dtb \ 410 sama5d36ek.dtb \
410 sama5d36ek_cmp.dtb 411 sama5d36ek_cmp.dtb
411 412
412 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ 413 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
413 at91-sama5d3_xplained.dtb 414 at91-sama5d3_xplained.dtb
414 415
415 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ 416 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
416 at91-sama5d4ek.dtb 417 at91-sama5d4ek.dtb
417 418
418 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ 419 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
419 at91-sama5d4_xplained.dtb 420 at91-sama5d4_xplained.dtb
420 421
421 dtb-$(CONFIG_ARCH_BCM283X) += \ 422 dtb-$(CONFIG_ARCH_BCM283X) += \
422 bcm2835-rpi-a-plus.dtb \ 423 bcm2835-rpi-a-plus.dtb \
423 bcm2835-rpi-a.dtb \ 424 bcm2835-rpi-a.dtb \
424 bcm2835-rpi-b-plus.dtb \ 425 bcm2835-rpi-b-plus.dtb \
425 bcm2835-rpi-b-rev2.dtb \ 426 bcm2835-rpi-b-rev2.dtb \
426 bcm2835-rpi-b.dtb \ 427 bcm2835-rpi-b.dtb \
427 bcm2836-rpi-2-b.dtb \ 428 bcm2836-rpi-2-b.dtb \
428 bcm2837-rpi-3-b.dtb 429 bcm2837-rpi-3-b.dtb
429 430
430 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb 431 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
431 432
432 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb 433 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
433 434
434 targets += $(dtb-y) 435 targets += $(dtb-y)
435 436
436 # Add any required device tree compiler flags here 437 # Add any required device tree compiler flags here
437 DTC_FLAGS += 438 DTC_FLAGS +=
438 439
439 PHONY += dtbs 440 PHONY += dtbs
440 dtbs: $(addprefix $(obj)/, $(dtb-y)) 441 dtbs: $(addprefix $(obj)/, $(dtb-y))
441 @: 442 @:
442 443
443 clean-files := *.dtb 444 clean-files := *.dtb
444 445
arch/arm/dts/rk3288-phycore-rdk.dts
Diff comments   View file @ bafcf2d
File was created 1 /*
2 * Device tree file for Phytec PCM-947 carrier board
3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 /dts-v1/;
46
47 #include <dt-bindings/input/input.h>
48 #include "rk3288-phycore-som.dtsi"
49
50 / {
51 model = "Phytec RK3288 PCM-947";
52 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
53
54 chosen {
55 stdout-path = &uart2;
56 };
57
58 config {
59 u-boot,dm-pre-reloc;
60 u-boot,boot0 = &emmc;
61 };
62
63 user_buttons: user-buttons {
64 compatible = "gpio-keys";
65 pinctrl-names = "default";
66 pinctrl-0 = <&user_button_pins>;
67
68 button@0 {
69 label = "home";
70 linux,code = <KEY_HOME>;
71 gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
72 wakeup-source;
73 };
74
75 button@1 {
76 label = "menu";
77 linux,code = <KEY_MENU>;
78 gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
79 wakeup-source;
80 };
81 };
82
83 vcc_host0_5v: usb-host0-regulator {
84 compatible = "regulator-fixed";
85 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&host0_vbus_drv>;
88 regulator-name = "vcc_host0_5v";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 regulator-always-on;
92 vin-supply = <&vdd_in_otg_out>;
93 };
94
95 vcc_host1_5v: usb-host1-regulator {
96 compatible = "regulator-fixed";
97 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&host1_vbus_drv>;
100 regulator-name = "vcc_host1_5v";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 vin-supply = <&vdd_in_otg_out>;
105 };
106
107 vcc_otg_5v: usb-otg-regulator {
108 compatible = "regulator-fixed";
109 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&otg_vbus_drv>;
112 regulator-name = "vcc_otg_5v";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 regulator-always-on;
116 vin-supply = <&vdd_in_otg_out>;
117 };
118 };
119
120 &dmc {
121 rockchip,num-channels = <2>;
122 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
123 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
124 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
125 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
126 0x5 0x0>;
127 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
128 0xa60 0x40 0x10 0x0>;
129 rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
130 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
131 };
132
133 &gmac {
134 status = "okay";
135 };
136
137 &hdmi {
138 status = "okay";
139 };
140
141 &i2c1 {
142 status = "okay";
143
144 touchscreen@44 {
145 compatible = "st,stmpe811";
146 reg = <0x44>;
147 };
148
149 adc@64 {
150 compatible = "maxim,max1037";
151 reg = <0x64>;
152 };
153
154 i2c_rtc: rtc@68 {
155 compatible = "rv4162";
156 reg = <0x68>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&i2c_rtc_int>;
159 interrupt-parent = <&gpio5>;
160 interrupts = <10 0>;
161 };
162 };
163
164 &i2c3 {
165 status = "okay";
166
167 i2c_eeprom_cb: eeprom@51 {
168 compatible = "atmel,24c32";
169 reg = <0x51>;
170 pagesize = <32>;
171 };
172 };
173
174 &i2c4 {
175 status = "okay";
176 };
177
178 &i2c5 {
179 status = "okay";
180 };
181
182 &pinctrl {
183 u-boot,dm-pre-reloc;
184
185 pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
186 bias-pull-up;
187 drive-strength = <12>;
188 };
189
190 buttons {
191 user_button_pins: user-button-pins {
192 /* button 1 */
193 rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
194 /* button 2 */
195 <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
196 };
197 };
198
199 rv4162 {
200 i2c_rtc_int: i2c-rtc-int {
201 rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
202 };
203 };
204
205 sdmmc {
206 /*
207 * Default drive strength isn't enough to achieve even
208 * high-speed mode on pcm-947 board so bump up to 12 mA.
209 */
210 sdmmc_bus4: sdmmc-bus4 {
211 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
212 <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
213 <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
214 <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
215 };
216
217 sdmmc_clk: sdmmc-clk {
218 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
219 };
220
221 sdmmc_cmd: sdmmc-cmd {
222 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
223 };
224
225 sdmmc_pwr: sdmmc-pwr {
226 rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
227 };
228 };
229
230 touchscreen {
231 ts_irq_pin: ts-irq-pin {
232 rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
233 };
234 };
235
236 usb_host {
237 host0_vbus_drv: host0-vbus-drv {
238 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
239 };
240
241 host1_vbus_drv: host1-vbus-drv {
242 rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
243 };
244 };
245
246 usb_otg {
247 otg_vbus_drv: otg-vbus-drv {
248 rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
249 };
250 };
251 };
252
253 &sdmmc {
254 u-boot,dm-pre-reloc;
255
256 bus-width = <4>;
257 cap-mmc-highspeed;
258 cap-sd-highspeed;
259 card-detect-delay = <200>;
260 disable-wp;
261 num-slots = <1>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
264 vmmc-supply = <&vdd_io_sd>;
265 vqmmc-supply = <&vdd_io_sd>;
266 status = "okay";
267 };
268
269 &uart0 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
272 status = "okay";
273 };
274
275 &uart2 {
276 u-boot,dm-pre-reloc;
277 status = "okay";
278 };
279
280 &usbphy {
281 status = "okay";
282 };
283
284 &usb_host0_ehci {
285 status = "okay";
286 };
287
288 &usb_host1 {
289 status = "okay";
290 };
291
292 &usb_otg {
293 status = "okay";
294 };
295
arch/arm/dts/rk3288-phycore-som.dtsi
Diff comments   View file @ bafcf2d
File was created 1 /*
2 * Device tree file for Phytec phyCORE-RK3288 SoM
3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include <dt-bindings/net/ti-dp83867.h>
46 #include "rk3288.dtsi"
47
48 / {
49 model = "Phytec RK3288 phyCORE";
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
51
52 /*
53 * Set the minimum memory size here and
54 * let the bootloader set the real size.
55 */
56 memory {
57 device_type = "memory";
58 reg = <0 0x8000000>;
59 };
60
61 aliases {
62 rtc0 = &i2c_rtc;
63 rtc1 = &rk818;
64 };
65
66 ext_gmac: external-gmac-clock {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <125000000>;
70 clock-output-names = "ext_gmac";
71 };
72
73 io_domains: io_domains {
74 compatible = "rockchip,rk3288-io-voltage-domain";
75
76 status = "okay";
77 sdcard-supply = <&vdd_io_sd>;
78 flash0-supply = <&vdd_emmc_io>;
79 flash1-supply = <&vdd_misc_1v8>;
80 gpio1830-supply = <&vdd_3v3_io>;
81 gpio30-supply = <&vdd_3v3_io>;
82 bb-supply = <&vdd_3v3_io>;
83 dvp-supply = <&vdd_3v3_io>;
84 lcdc-supply = <&vdd_3v3_io>;
85 wifi-supply = <&vdd_3v3_io>;
86 audio-supply = <&vdd_3v3_io>;
87 };
88
89 leds: user-leds {
90 compatible = "gpio-leds";
91 pinctrl-names = "default";
92 pinctrl-0 = <&user_led>;
93
94 user {
95 label = "green_led";
96 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
97 linux,default-trigger = "heartbeat";
98 default-state = "keep";
99 };
100 };
101
102 vdd_emmc_io: vdd-emmc-io {
103 compatible = "regulator-fixed";
104 regulator-name = "vdd_emmc_io";
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <1800000>;
107 vin-supply = <&vdd_3v3_io>;
108 };
109
110 vdd_in_otg_out: vdd-in-otg-out {
111 compatible = "regulator-fixed";
112 regulator-name = "vdd_in_otg_out";
113 regulator-always-on;
114 regulator-boot-on;
115 regulator-min-microvolt = <5000000>;
116 regulator-max-microvolt = <5000000>;
117 };
118
119 vdd_misc_1v8: vdd-misc-1v8 {
120 compatible = "regulator-fixed";
121 regulator-name = "vdd_misc_1v8";
122 regulator-always-on;
123 regulator-boot-on;
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 };
127 };
128
129 &cpu0 {
130 cpu0-supply = <&vdd_cpu>;
131 operating-points = <
132 /* KHz uV */
133 1800000 1400000
134 1608000 1350000
135 1512000 1300000
136 1416000 1200000
137 1200000 1100000
138 1008000 1050000
139 816000 1000000
140 696000 950000
141 600000 900000
142 408000 900000
143 312000 900000
144 216000 900000
145 126000 900000
146 >;
147 };
148
149 &emmc {
150 status = "okay";
151 u-boot,dm-pre-reloc;
152
153 bus-width = <8>;
154 cap-mmc-highspeed;
155 disable-wp;
156 non-removable;
157 num-slots = <1>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
160 vmmc-supply = <&vdd_3v3_io>;
161 vqmmc-supply = <&vdd_emmc_io>;
162 };
163
164 &gmac {
165 assigned-clocks = <&cru SCLK_MAC>;
166 assigned-clock-parents = <&ext_gmac>;
167 clock_in_out = "input";
168 pinctrl-names = "default";
169 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
170 phy-handle = <&phy0>;
171 phy-supply = <&vdd_eth_2v5>;
172 phy-mode = "rgmii-id";
173 snps,reset-active-low;
174 snps,reset-delays-us = <0 10000 1000000>;
175 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
176 tx_delay = <0x0>;
177 rx_delay = <0x0>;
178
179 mdio0 {
180 compatible = "snps,dwmac-mdio";
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 phy0: ethernet-phy@0 {
185 compatible = "ethernet-phy-ieee802.3-c22";
186 reg = <0>;
187 interrupt-parent = <&gpio4>;
188 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
189 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
190 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
191 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
192 enet-phy-lane-no-swap;
193 };
194 };
195 };
196
197 &hdmi {
198 ddc-i2c-bus = <&i2c5>;
199 };
200
201 &i2c0 {
202 status = "okay";
203 u-boot,dm-pre-reloc;
204
205 clock-frequency = <400000>;
206
207 rk818: pmic@1c {
208 status = "okay";
209 compatible = "rockchip,rk818";
210 reg = <0x1c>;
211 interrupt-parent = <&gpio0>;
212 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pmic_int>;
215 rockchip,system-power-controller;
216 wakeup-source;
217 #clock-cells = <1>;
218 u-boot,dm-pre-reloc;
219
220 vcc1-supply = <&vdd_sys>;
221 vcc2-supply = <&vdd_sys>;
222 vcc3-supply = <&vdd_sys>;
223 vcc4-supply = <&vdd_sys>;
224 boost-supply = <&vdd_in_otg_out>;
225 vcc6-supply = <&vdd_sys>;
226 vcc7-supply = <&vdd_misc_1v8>;
227 vcc8-supply = <&vdd_misc_1v8>;
228 vcc9-supply = <&vdd_3v3_io>;
229 vddio-supply = <&vdd_3v3_io>;
230
231 regulators {
232 u-boot,dm-pre-reloc;
233 vdd_log: DCDC_REG1 {
234 regulator-name = "vdd_log";
235 regulator-always-on;
236 regulator-boot-on;
237 regulator-min-microvolt = <1100000>;
238 regulator-max-microvolt = <1100000>;
239 regulator-state-mem {
240 regulator-off-in-suspend;
241 };
242 };
243
244 vdd_gpu: DCDC_REG2 {
245 regulator-name = "vdd_gpu";
246 regulator-always-on;
247 regulator-boot-on;
248 regulator-min-microvolt = <800000>;
249 regulator-max-microvolt = <1250000>;
250 regulator-state-mem {
251 regulator-on-in-suspend;
252 regulator-suspend-microvolt = <1000000>;
253 };
254 };
255
256 vcc_ddr: DCDC_REG3 {
257 regulator-name = "vcc_ddr";
258 regulator-always-on;
259 regulator-boot-on;
260 regulator-state-mem {
261 regulator-on-in-suspend;
262 };
263 };
264
265 vdd_3v3_io: DCDC_REG4 {
266 regulator-name = "vdd_3v3_io";
267 regulator-always-on;
268 regulator-boot-on;
269 regulator-min-microvolt = <3300000>;
270 regulator-max-microvolt = <3300000>;
271 regulator-state-mem {
272 regulator-on-in-suspend;
273 regulator-suspend-microvolt = <3300000>;
274 };
275 };
276
277 vdd_sys: DCDC_BOOST {
278 regulator-name = "vdd_sys";
279 regulator-always-on;
280 regulator-boot-on;
281 regulator-min-microvolt = <5000000>;
282 regulator-max-microvolt = <5000000>;
283 regulator-state-mem {
284 regulator-on-in-suspend;
285 regulator-suspend-microvolt = <5000000>;
286 };
287 };
288
289 /* vcc9 */
290 vdd_sd: SWITCH_REG {
291 regulator-name = "vdd_sd";
292 regulator-always-on;
293 regulator-boot-on;
294 regulator-state-mem {
295 regulator-off-in-suspend;
296 };
297 };
298
299 /* vcc6 */
300 vdd_eth_2v5: LDO_REG2 {
301 regulator-name = "vdd_eth_2v5";
302 regulator-always-on;
303 regulator-boot-on;
304 regulator-min-microvolt = <2500000>;
305 regulator-max-microvolt = <2500000>;
306 regulator-state-mem {
307 regulator-on-in-suspend;
308 regulator-suspend-microvolt = <2500000>;
309 };
310 };
311
312 /* vcc7 */
313 vdd_1v0: LDO_REG3 {
314 regulator-name = "vdd_1v0";
315 regulator-always-on;
316 regulator-boot-on;
317 regulator-min-microvolt = <1000000>;
318 regulator-max-microvolt = <1000000>;
319 regulator-state-mem {
320 regulator-on-in-suspend;
321 regulator-suspend-microvolt = <1000000>;
322 };
323 };
324
325 /* vcc8 */
326 vdd_1v8_lcd_ldo: LDO_REG4 {
327 regulator-name = "vdd_1v8_lcd_ldo";
328 regulator-always-on;
329 regulator-boot-on;
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
332 regulator-state-mem {
333 regulator-on-in-suspend;
334 regulator-suspend-microvolt = <1800000>;
335 };
336 };
337
338 /* vcc8 */
339 vdd_1v0_lcd: LDO_REG6 {
340 regulator-name = "vdd_1v0_lcd";
341 regulator-always-on;
342 regulator-boot-on;
343 regulator-min-microvolt = <1000000>;
344 regulator-max-microvolt = <1000000>;
345 regulator-state-mem {
346 regulator-on-in-suspend;
347 regulator-suspend-microvolt = <1000000>;
348 };
349 };
350
351 /* vcc7 */
352 vdd_1v8_ldo: LDO_REG7 {
353 regulator-name = "vdd_1v8_ldo";
354 regulator-always-on;
355 regulator-boot-on;
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-state-mem {
359 regulator-off-in-suspend;
360 regulator-suspend-microvolt = <1800000>;
361 };
362 };
363
364 /* vcc9 */
365 vdd_io_sd: LDO_REG9 {
366 regulator-name = "vdd_io_sd";
367 regulator-always-on;
368 regulator-boot-on;
369 regulator-min-microvolt = <3300000>;
370 regulator-max-microvolt = <3300000>;
371 regulator-state-mem {
372 regulator-on-in-suspend;
373 regulator-suspend-microvolt = <3300000>;
374 };
375 };
376 };
377 };
378
379 /* M24C32-D */
380 i2c_eeprom: eeprom@50 {
381 compatible = "atmel,24c32";
382 reg = <0x50>;
383 pagesize = <32>;
384 };
385
386 vdd_cpu: regulator@60 {
387 compatible = "fcs,fan53555";
388 reg = <0x60>;
389 fcs,suspend-voltage-selector = <1>;
390 regulator-always-on;
391 regulator-boot-on;
392 regulator-enable-ramp-delay = <300>;
393 regulator-name = "vdd_cpu";
394 regulator-min-microvolt = <800000>;
395 regulator-max-microvolt = <1430000>;
396 regulator-ramp-delay = <8000>;
397 vin-supply = <&vdd_sys>;
398 };
399 };
400
401 &pinctrl {
402 pcfg_output_high: pcfg-output-high {
403 output-high;
404 };
405
406 emmc {
407 /*
408 * We run eMMC at max speed; bump up drive strength.
409 * We also have external pulls, so disable the internal ones.
410 */
411 emmc_clk: emmc-clk {
412 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
413 };
414
415 emmc_cmd: emmc-cmd {
416 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
417 };
418
419 emmc_bus8: emmc-bus8 {
420 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
421 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
422 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
423 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
424 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
425 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
426 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
427 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
428 };
429 };
430
431 gmac {
432 phy_int: phy-int {
433 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
434 };
435
436 phy_rst: phy-rst {
437 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
438 };
439 };
440
441 leds {
442 user_led: user-led {
443 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
444 };
445 };
446
447 pmic {
448 pmic_int: pmic-int {
449 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
450 };
451
452 /* Pin for switching state between sleep and non-sleep state */
453 pmic_sleep: pmic-sleep {
454 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
455 };
456 };
457 };
458
459 &pwm1 {
460 status = "okay";
461 };
462
463 &saradc {
464 status = "okay";
465 vref-supply = <&vdd_1v8_ldo>;
466 };
467
468 &spi2 {
469 status = "okay";
470
471 serial_flash: flash@0 {
472 compatible = "micron,n25q128a13", "jedec,spi-nor";
473 reg = <0x0>;
474 spi-max-frequency = <50000000>;
475 m25p,fast-read;
476 #address-cells = <1>;
477 #size-cells = <1>;
478 status = "okay";
479 };
480 };
481
482 &tsadc {
483 status = "okay";
484 rockchip,hw-tshut-mode = <0>;
485 rockchip,hw-tshut-polarity = <0>;
486 };
487
488 &vopb {
489 status = "okay";
490 };
491
492 &vopb_mmu {
493 status = "okay";
494 };
495
496 &vopl {
497 status = "okay";
498 };
499
500 &vopl_mmu {
501 status = "okay";
502 };
503
504 &wdt {
505 status = "okay";
506 };
507
arch/arm/mach-rockchip/rk3288-board-spl.c
Diff comments   View file @ bafcf2d
1 /* 1 /*
2 * (C) Copyright 2015 Google, Inc 2 * (C) Copyright 2015 Google, Inc
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <debug_uart.h> 8 #include <debug_uart.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <fdtdec.h> 10 #include <fdtdec.h>
11 #include <i2c.h>
11 #include <led.h> 12 #include <led.h>
12 #include <malloc.h> 13 #include <malloc.h>
13 #include <ram.h> 14 #include <ram.h>
14 #include <spl.h> 15 #include <spl.h>
15 #include <asm/gpio.h> 16 #include <asm/gpio.h>
16 #include <asm/io.h> 17 #include <asm/io.h>
17 #include <asm/arch/bootrom.h> 18 #include <asm/arch/bootrom.h>
18 #include <asm/arch/clock.h> 19 #include <asm/arch/clock.h>
19 #include <asm/arch/hardware.h> 20 #include <asm/arch/hardware.h>
20 #include <asm/arch/periph.h> 21 #include <asm/arch/periph.h>
21 #include <asm/arch/sdram.h> 22 #include <asm/arch/sdram.h>
22 #include <asm/arch/timer.h> 23 #include <asm/arch/timer.h>
23 #include <dm/pinctrl.h> 24 #include <dm/pinctrl.h>
24 #include <dm/root.h> 25 #include <dm/root.h>
25 #include <dm/test.h> 26 #include <dm/test.h>
26 #include <dm/util.h> 27 #include <dm/util.h>
27 #include <power/regulator.h> 28 #include <power/regulator.h>
29 #include <power/rk8xx_pmic.h>
28 30
29 DECLARE_GLOBAL_DATA_PTR; 31 DECLARE_GLOBAL_DATA_PTR;
30 32
31 u32 spl_boot_device(void) 33 u32 spl_boot_device(void)
32 { 34 {
33 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 35 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
34 const void *blob = gd->fdt_blob; 36 const void *blob = gd->fdt_blob;
35 struct udevice *dev; 37 struct udevice *dev;
36 const char *bootdev; 38 const char *bootdev;
37 int node; 39 int node;
38 int ret; 40 int ret;
39 41
40 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); 42 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
41 debug("Boot device %s\n", bootdev); 43 debug("Boot device %s\n", bootdev);
42 if (!bootdev) 44 if (!bootdev)
43 goto fallback; 45 goto fallback;
44 46
45 node = fdt_path_offset(blob, bootdev); 47 node = fdt_path_offset(blob, bootdev);
46 if (node < 0) { 48 if (node < 0) {
47 debug("node=%d\n", node); 49 debug("node=%d\n", node);
48 goto fallback; 50 goto fallback;
49 } 51 }
50 ret = device_get_global_by_of_offset(node, &dev); 52 ret = device_get_global_by_of_offset(node, &dev);
51 if (ret) { 53 if (ret) {
52 debug("device at node %s/%d not found: %d\n", bootdev, node, 54 debug("device at node %s/%d not found: %d\n", bootdev, node,
53 ret); 55 ret);
54 goto fallback; 56 goto fallback;
55 } 57 }
56 debug("Found device %s\n", dev->name); 58 debug("Found device %s\n", dev->name);
57 switch (device_get_uclass_id(dev)) { 59 switch (device_get_uclass_id(dev)) {
58 case UCLASS_SPI_FLASH: 60 case UCLASS_SPI_FLASH:
59 return BOOT_DEVICE_SPI; 61 return BOOT_DEVICE_SPI;
60 case UCLASS_MMC: 62 case UCLASS_MMC:
61 return BOOT_DEVICE_MMC1; 63 return BOOT_DEVICE_MMC1;
62 default: 64 default:
63 debug("Booting from device uclass '%s' not supported\n", 65 debug("Booting from device uclass '%s' not supported\n",
64 dev_get_uclass_name(dev)); 66 dev_get_uclass_name(dev));
65 } 67 }
66 68
67 fallback: 69 fallback:
68 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 70 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
69 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 71 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
70 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 72 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
71 return BOOT_DEVICE_SPI; 73 return BOOT_DEVICE_SPI;
72 #endif 74 #endif
73 return BOOT_DEVICE_MMC1; 75 return BOOT_DEVICE_MMC1;
74 } 76 }
75 77
76 u32 spl_boot_mode(const u32 boot_device) 78 u32 spl_boot_mode(const u32 boot_device)
77 { 79 {
78 return MMCSD_MODE_RAW; 80 return MMCSD_MODE_RAW;
79 } 81 }
80 82
81 /* read L2 control register (L2CTLR) */ 83 /* read L2 control register (L2CTLR) */
82 static inline uint32_t read_l2ctlr(void) 84 static inline uint32_t read_l2ctlr(void)
83 { 85 {
84 uint32_t val = 0; 86 uint32_t val = 0;
85 87
86 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 88 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
87 89
88 return val; 90 return val;
89 } 91 }
90 92
91 /* write L2 control register (L2CTLR) */ 93 /* write L2 control register (L2CTLR) */
92 static inline void write_l2ctlr(uint32_t val) 94 static inline void write_l2ctlr(uint32_t val)
93 { 95 {
94 /* 96 /*
95 * Note: L2CTLR can only be written when the L2 memory system 97 * Note: L2CTLR can only be written when the L2 memory system
96 * is idle, ie before the MMU is enabled. 98 * is idle, ie before the MMU is enabled.
97 */ 99 */
98 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); 100 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
99 isb(); 101 isb();
100 } 102 }
101 103
102 static void configure_l2ctlr(void) 104 static void configure_l2ctlr(void)
103 { 105 {
104 uint32_t l2ctlr; 106 uint32_t l2ctlr;
105 107
106 l2ctlr = read_l2ctlr(); 108 l2ctlr = read_l2ctlr();
107 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ 109 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
108 110
109 /* 111 /*
110 * Data RAM write latency: 2 cycles 112 * Data RAM write latency: 2 cycles
111 * Data RAM read latency: 2 cycles 113 * Data RAM read latency: 2 cycles
112 * Data RAM setup latency: 1 cycle 114 * Data RAM setup latency: 1 cycle
113 * Tag RAM write latency: 1 cycle 115 * Tag RAM write latency: 1 cycle
114 * Tag RAM read latency: 1 cycle 116 * Tag RAM read latency: 1 cycle
115 * Tag RAM setup latency: 1 cycle 117 * Tag RAM setup latency: 1 cycle
116 */ 118 */
117 l2ctlr |= (1 << 3 | 1 << 0); 119 l2ctlr |= (1 << 3 | 1 << 0);
118 write_l2ctlr(l2ctlr); 120 write_l2ctlr(l2ctlr);
119 } 121 }
120 122
121 #ifdef CONFIG_SPL_MMC_SUPPORT 123 #ifdef CONFIG_SPL_MMC_SUPPORT
122 static int configure_emmc(struct udevice *pinctrl) 124 static int configure_emmc(struct udevice *pinctrl)
123 { 125 {
124 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) 126 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
125 127
126 struct gpio_desc desc; 128 struct gpio_desc desc;
127 int ret; 129 int ret;
128 130
129 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); 131 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
130 132
131 /* 133 /*
132 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps 134 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
133 * use the EMMC_PWREN setting. 135 * use the EMMC_PWREN setting.
134 */ 136 */
135 ret = dm_gpio_lookup_name("D9", &desc); 137 ret = dm_gpio_lookup_name("D9", &desc);
136 if (ret) { 138 if (ret) {
137 debug("gpio ret=%d\n", ret); 139 debug("gpio ret=%d\n", ret);
138 return ret; 140 return ret;
139 } 141 }
140 ret = dm_gpio_request(&desc, "emmc_pwren"); 142 ret = dm_gpio_request(&desc, "emmc_pwren");
141 if (ret) { 143 if (ret) {
142 debug("gpio_request ret=%d\n", ret); 144 debug("gpio_request ret=%d\n", ret);
143 return ret; 145 return ret;
144 } 146 }
145 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); 147 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
146 if (ret) { 148 if (ret) {
147 debug("gpio dir ret=%d\n", ret); 149 debug("gpio dir ret=%d\n", ret);
148 return ret; 150 return ret;
149 } 151 }
150 ret = dm_gpio_set_value(&desc, 1); 152 ret = dm_gpio_set_value(&desc, 1);
151 if (ret) { 153 if (ret) {
152 debug("gpio value ret=%d\n", ret); 154 debug("gpio value ret=%d\n", ret);
153 return ret; 155 return ret;
154 } 156 }
155 #endif 157 #endif
156 return 0; 158 return 0;
157 } 159 }
158 #endif 160 #endif
159 161
162 #if !defined(CONFIG_SPL_OF_PLATDATA)
163 static int phycore_init(void)
164 {
165 struct udevice *pmic;
166 int ret;
167
168 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
169 if (ret)
170 return ret;
171
172 #if defined(CONFIG_SPL_POWER_SUPPORT)
173 /* Increase USB input current to 2A */
174 ret = rk818_spl_configure_usb_input_current(pmic, 2000);
175 if (ret)
176 return ret;
177
178 /* Close charger when USB lower then 3.26V */
179 ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
180 if (ret)
181 return ret;
182 #endif
183
184 return 0;
185 }
186 #endif
187
160 void board_init_f(ulong dummy) 188 void board_init_f(ulong dummy)
161 { 189 {
162 struct udevice *pinctrl; 190 struct udevice *pinctrl;
163 struct udevice *dev; 191 struct udevice *dev;
164 int ret; 192 int ret;
165 193
166 /* Example code showing how to enable the debug UART on RK3288 */ 194 /* Example code showing how to enable the debug UART on RK3288 */
167 #include <asm/arch/grf_rk3288.h> 195 #include <asm/arch/grf_rk3288.h>
168 /* Enable early UART on the RK3288 */ 196 /* Enable early UART on the RK3288 */
169 #define GRF_BASE 0xff770000 197 #define GRF_BASE 0xff770000
170 struct rk3288_grf * const grf = (void *)GRF_BASE; 198 struct rk3288_grf * const grf = (void *)GRF_BASE;
171 199
172 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | 200 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
173 GPIO7C6_MASK << GPIO7C6_SHIFT, 201 GPIO7C6_MASK << GPIO7C6_SHIFT,
174 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | 202 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
175 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); 203 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
176 /* 204 /*
177 * Debug UART can be used from here if required: 205 * Debug UART can be used from here if required:
178 * 206 *
179 * debug_uart_init(); 207 * debug_uart_init();
180 * printch('a'); 208 * printch('a');
181 * printhex8(0x1234); 209 * printhex8(0x1234);
182 * printascii("string"); 210 * printascii("string");
183 */ 211 */
184 debug_uart_init(); 212 debug_uart_init();
185 debug("\nspl:debug uart enabled in %s\n", __func__); 213 debug("\nspl:debug uart enabled in %s\n", __func__);
186 ret = spl_early_init(); 214 ret = spl_early_init();
187 if (ret) { 215 if (ret) {
188 debug("spl_early_init() failed: %d\n", ret); 216 debug("spl_early_init() failed: %d\n", ret);
189 hang(); 217 hang();
190 } 218 }
191 219
192 rockchip_timer_init(); 220 rockchip_timer_init();
193 configure_l2ctlr(); 221 configure_l2ctlr();
194 222
195 ret = rockchip_get_clk(&dev); 223 ret = rockchip_get_clk(&dev);
196 if (ret) { 224 if (ret) {
197 debug("CLK init failed: %d\n", ret); 225 debug("CLK init failed: %d\n", ret);
198 return; 226 return;
199 } 227 }
200 228
201 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 229 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
202 if (ret) { 230 if (ret) {
203 debug("Pinctrl init failed: %d\n", ret); 231 debug("Pinctrl init failed: %d\n", ret);
204 return; 232 return;
205 } 233 }
234
235 #if !defined(CONFIG_SPL_OF_PLATDATA)
236 if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
237 ret = phycore_init();
238 if (ret) {
239 debug("Failed to set up phycore power settings: %d\n",
240 ret);
241 return;
242 }
243 }
244 #endif
245
206 debug("\nspl:init dram\n"); 246 debug("\nspl:init dram\n");
207 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 247 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
208 if (ret) { 248 if (ret) {
209 debug("DRAM init failed: %d\n", ret); 249 debug("DRAM init failed: %d\n", ret);
210 return; 250 return;
211 } 251 }
212 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 252 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
213 back_to_bootrom(); 253 back_to_bootrom();
214 #endif 254 #endif
215 } 255 }
216 256
217 static int setup_led(void) 257 static int setup_led(void)
218 { 258 {
219 #ifdef CONFIG_SPL_LED 259 #ifdef CONFIG_SPL_LED
220 struct udevice *dev; 260 struct udevice *dev;
221 char *led_name; 261 char *led_name;
222 int ret; 262 int ret;
223 263
224 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 264 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
225 if (!led_name) 265 if (!led_name)
226 return 0; 266 return 0;
227 ret = led_get_by_label(led_name, &dev); 267 ret = led_get_by_label(led_name, &dev);
228 if (ret) { 268 if (ret) {
229 debug("%s: get=%d\n", __func__, ret); 269 debug("%s: get=%d\n", __func__, ret);
230 return ret; 270 return ret;
231 } 271 }
232 ret = led_set_on(dev, 1); 272 ret = led_set_on(dev, 1);
233 if (ret) 273 if (ret)
234 return ret; 274 return ret;
235 #endif 275 #endif
236 276
237 return 0; 277 return 0;
238 } 278 }
239 279
240 void spl_board_init(void) 280 void spl_board_init(void)
241 { 281 {
242 struct udevice *pinctrl; 282 struct udevice *pinctrl;
243 int ret; 283 int ret;
244 284
245 ret = setup_led(); 285 ret = setup_led();
246 286
247 if (ret) { 287 if (ret) {
248 debug("LED ret=%d\n", ret); 288 debug("LED ret=%d\n", ret);
249 hang(); 289 hang();
250 } 290 }
251 291
252 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 292 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
253 if (ret) { 293 if (ret) {
254 debug("%s: Cannot find pinctrl device\n", __func__); 294 debug("%s: Cannot find pinctrl device\n", __func__);
255 goto err; 295 goto err;
256 } 296 }
257 297
258 #ifdef CONFIG_SPL_MMC_SUPPORT 298 #ifdef CONFIG_SPL_MMC_SUPPORT
259 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 299 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
260 if (ret) { 300 if (ret) {
261 debug("%s: Failed to set up SD card\n", __func__); 301 debug("%s: Failed to set up SD card\n", __func__);
262 goto err; 302 goto err;
263 } 303 }
264 ret = configure_emmc(pinctrl); 304 ret = configure_emmc(pinctrl);
265 if (ret) { 305 if (ret) {
266 debug("%s: Failed to set up eMMC\n", __func__); 306 debug("%s: Failed to set up eMMC\n", __func__);
267 goto err; 307 goto err;
268 } 308 }
269 #endif 309 #endif
270 310
271 /* Enable debug UART */ 311 /* Enable debug UART */
272 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 312 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
273 if (ret) { 313 if (ret) {
274 debug("%s: Failed to set up console UART\n", __func__); 314 debug("%s: Failed to set up console UART\n", __func__);
275 goto err; 315 goto err;
276 } 316 }
277 317
278 preloader_console_init(); 318 preloader_console_init();
279 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 319 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
280 back_to_bootrom(); 320 back_to_bootrom();
281 #endif 321 #endif
282 return; 322 return;
283 err: 323 err:
284 printf("spl_board_init: Error %d\n", ret); 324 printf("spl_board_init: Error %d\n", ret);
285 325
286 /* No way to report error here */ 326 /* No way to report error here */
287 hang(); 327 hang();
288 } 328 }
289 329
arch/arm/mach-rockchip/rk3288/Kconfig
Diff comments   View file @ bafcf2d
1 if ROCKCHIP_RK3288 1 if ROCKCHIP_RK3288
2 2
3 config TARGET_CHROMEBOOK_JERRY 3 config TARGET_CHROMEBOOK_JERRY
4 bool "Google/Rockchip Veyron-Jerry Chromebook" 4 bool "Google/Rockchip Veyron-Jerry Chromebook"
5 select BOARD_LATE_INIT 5 select BOARD_LATE_INIT
6 help 6 help
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports, 7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and 8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to 9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
10 the keyboard and battery functions. 10 the keyboard and battery functions.
11 11
12 config TARGET_CHROMEBIT_MICKEY 12 config TARGET_CHROMEBIT_MICKEY
13 bool "Google/Rockchip Veyron-Mickey Chromebit" 13 bool "Google/Rockchip Veyron-Mickey Chromebit"
14 select BOARD_LATE_INIT 14 select BOARD_LATE_INIT
15 help 15 help
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI 16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
17 and WiFi. It has a separate power port and is designed to connect 17 and WiFi. It has a separate power port and is designed to connect
18 to the HDMI input of a monitor or TV. It has no internal battery. 18 to the HDMI input of a monitor or TV. It has no internal battery.
19 Typically a USB hub or wireless keyboard/touchpad is used to get 19 Typically a USB hub or wireless keyboard/touchpad is used to get
20 keyboard and mouse access. 20 keyboard and mouse access.
21 21
22 config TARGET_CHROMEBOOK_MINNIE 22 config TARGET_CHROMEBOOK_MINNIE
23 bool "Google/Rockchip Veyron-Minnie Chromebook" 23 bool "Google/Rockchip Veyron-Minnie Chromebook"
24 select BOARD_LATE_INIT 24 select BOARD_LATE_INIT
25 help 25 help
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, 27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
28 HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS 28 HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
29 EC (Cortex-M3) to provide access to the keyboard and battery 29 EC (Cortex-M3) to provide access to the keyboard and battery
30 functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of 30 functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
31 internal MMC. The product name is ASUS Chromebook Flip. 31 internal MMC. The product name is ASUS Chromebook Flip.
32 32
33 config TARGET_EVB_RK3288 33 config TARGET_EVB_RK3288
34 bool "Evb-RK3288" 34 bool "Evb-RK3288"
35 select BOARD_LATE_INIT 35 select BOARD_LATE_INIT
36 help 36 help
37 EVB-RK3288 is a RK3288-based development board with 2 USB ports, 37 EVB-RK3288 is a RK3288-based development board with 2 USB ports,
38 HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It 38 HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
39 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors 39 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
40 provide access to display pins, I2C, SPI, UART and GPIOs. 40 provide access to display pins, I2C, SPI, UART and GPIOs.
41 41
42 config TARGET_FENNEC_RK3288 42 config TARGET_FENNEC_RK3288
43 bool "Fennec-RK3288" 43 bool "Fennec-RK3288"
44 select BOARD_LATE_INIT 44 select BOARD_LATE_INIT
45 help 45 help
46 Fennec is a RK3288-based development board with 2 USB ports, 46 Fennec is a RK3288-based development board with 2 USB ports,
47 HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also 47 HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also
48 includes on-board eMMC and 2GB of SDRAM. Expansion connectors 48 includes on-board eMMC and 2GB of SDRAM. Expansion connectors
49 provide access to display pins, I2C, SPI, UART and GPIOs. 49 provide access to display pins, I2C, SPI, UART and GPIOs.
50 50
51 config TARGET_FIREFLY_RK3288 51 config TARGET_FIREFLY_RK3288
52 bool "Firefly-RK3288" 52 bool "Firefly-RK3288"
53 select BOARD_LATE_INIT 53 select BOARD_LATE_INIT
54 help 54 help
55 Firefly is a RK3288-based development board with 2 USB ports, 55 Firefly is a RK3288-based development board with 2 USB ports,
56 HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It 56 HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
57 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors 57 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
58 provide access to display pins, I2C, SPI, UART and GPIOs. 58 provide access to display pins, I2C, SPI, UART and GPIOs.
59 59
60 config TARGET_MIQI_RK3288 60 config TARGET_MIQI_RK3288
61 bool "MiQi-RK3288" 61 bool "MiQi-RK3288"
62 select BOARD_LATE_INIT 62 select BOARD_LATE_INIT
63 help 63 help
64 MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0 64 MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0
65 ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It 65 ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It
66 has 1 or 2 GiB SDRAM. Expansion connectors provide access to 66 has 1 or 2 GiB SDRAM. Expansion connectors provide access to
67 I2C, SPI, UART, GPIOs and fan control. 67 I2C, SPI, UART, GPIOs and fan control.
68 68
69 config TARGET_PHYCORE_RK3288
70 bool "phyCORE-RK3288"
71 select BOARD_LATE_INIT
72 help
73 Add basic support for the PCM-947 carrier board, a RK3288 based
74 development board made by PHYTEC. This board works in a combination
75 with the phyCORE-RK3288 System on Module.
76
69 config TARGET_POPMETAL_RK3288 77 config TARGET_POPMETAL_RK3288
70 bool "PopMetal-RK3288" 78 bool "PopMetal-RK3288"
71 select BOARD_LATE_INIT 79 select BOARD_LATE_INIT
72 help 80 help
73 PopMetal is a RK3288-based development board with 3 USB host ports, 81 PopMetal is a RK3288-based development board with 3 USB host ports,
74 1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit 82 1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit
75 Ethernet and lots of sensors. It also includes on-board 8 GeMMC and 83 Ethernet and lots of sensors. It also includes on-board 8 GeMMC and
76 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, 84 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
77 GPIOs and display interface. 85 GPIOs and display interface.
78 86
79 config TARGET_ROCK2 87 config TARGET_ROCK2
80 bool "Radxa Rock 2" 88 bool "Radxa Rock 2"
81 select BOARD_LATE_INIT 89 select BOARD_LATE_INIT
82 help 90 help
83 Rock 2 is a SOM and base-board combination based on RK3288. It 91 Rock 2 is a SOM and base-board combination based on RK3288. It
84 includes Ethernet, HDMI, 3 USB, micro-SD, audio, SATA, WiFi and 92 includes Ethernet, HDMI, 3 USB, micro-SD, audio, SATA, WiFi and
85 space for a real-time-clock battery. There is also an expansion 93 space for a real-time-clock battery. There is also an expansion
86 interface which provides access to many pins. 94 interface which provides access to many pins.
87 95
88 config TARGET_TINKER_RK3288 96 config TARGET_TINKER_RK3288
89 bool "Tinker-RK3288" 97 bool "Tinker-RK3288"
90 select BOARD_LATE_INIT 98 select BOARD_LATE_INIT
91 help 99 help
92 Tinker is a RK3288-based development board with 2 USB ports, HDMI, 100 Tinker is a RK3288-based development board with 2 USB ports, HDMI,
93 micro-SD card, audio, Gigabit Ethernet. It also includes on-board 101 micro-SD card, audio, Gigabit Ethernet. It also includes on-board
94 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to 102 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
95 I2C, SPI, UART, GPIOs. 103 I2C, SPI, UART, GPIOs.
96 104
97 config ROCKCHIP_FAST_SPL 105 config ROCKCHIP_FAST_SPL
98 bool "Change the CPU to full speed in SPL" 106 bool "Change the CPU to full speed in SPL"
99 depends on TARGET_CHROMEBOOK_JERRY 107 depends on TARGET_CHROMEBOOK_JERRY
100 help 108 help
101 Some boards want to boot as fast as possible. We can increase the 109 Some boards want to boot as fast as possible. We can increase the
102 CPU frequency in SPL if the power supply is configured to the correct 110 CPU frequency in SPL if the power supply is configured to the correct
103 voltage. This option is only available on boards which support it 111 voltage. This option is only available on boards which support it
104 and have the required PMIC code. 112 and have the required PMIC code.
105 113
106 config SYS_SOC 114 config SYS_SOC
107 default "rockchip" 115 default "rockchip"
108 116
109 config SYS_MALLOC_F_LEN 117 config SYS_MALLOC_F_LEN
110 default 0x0800 118 default 0x0800
111 119
112 config SPL_DRIVERS_MISC_SUPPORT 120 config SPL_DRIVERS_MISC_SUPPORT
113 default y 121 default y
114 122
115 config SPL_LIBCOMMON_SUPPORT 123 config SPL_LIBCOMMON_SUPPORT
116 default y 124 default y
117 125
118 config SPL_LIBGENERIC_SUPPORT 126 config SPL_LIBGENERIC_SUPPORT
119 default y 127 default y
120 128
121 config SPL_SERIAL_SUPPORT 129 config SPL_SERIAL_SUPPORT
122 default y 130 default y
123 131
124 source "board/chipspark/popmetal_rk3288/Kconfig" 132 source "board/chipspark/popmetal_rk3288/Kconfig"
125 133
126 source "board/firefly/firefly-rk3288/Kconfig" 134 source "board/firefly/firefly-rk3288/Kconfig"
127 135
128 source "board/google/veyron/Kconfig" 136 source "board/google/veyron/Kconfig"
129 137
130 source "board/mqmaker/miqi_rk3288/Kconfig" 138 source "board/mqmaker/miqi_rk3288/Kconfig"
139
140 source "board/phytec/phycore_rk3288/Kconfig"
131 141
132 source "board/radxa/rock2/Kconfig" 142 source "board/radxa/rock2/Kconfig"
133 143
134 source "board/rockchip/evb_rk3288/Kconfig" 144 source "board/rockchip/evb_rk3288/Kconfig"
135 145
136 source "board/rockchip/fennec_rk3288/Kconfig" 146 source "board/rockchip/fennec_rk3288/Kconfig"
137 147
138 source "board/rockchip/tinker_rk3288/Kconfig" 148 source "board/rockchip/tinker_rk3288/Kconfig"
139 149
140 endif 150 endif
141 151
board/phytec/phycore_rk3288/Kconfig
Diff comments   View file @ bafcf2d
File was created 1 if TARGET_PHYCORE_RK3288
2
3 config SYS_BOARD
4 default "phycore_rk3288"
5
6 config SYS_VENDOR
7 default "phytec"
8
9 config SYS_CONFIG_NAME
10 default "phycore_rk3288"
11
12 config BOARD_SPECIFIC_OPTIONS # dummy
13 def_bool y
14
15 endif
16
board/phytec/phycore_rk3288/MAINTAINERS
Diff comments   View file @ bafcf2d
File was created 1 phyCORE-RK3288
2 M: Wadim Egorov <w.egorov@phytec.de>
3 S: Maintained
4 F: board/phytec/phycore_rk3288
5 F: include/configs/phycore_rk3288.h
6 F: configs/phycore-rk3288_defconfig
7
board/phytec/phycore_rk3288/Makefile
Diff comments   View file @ bafcf2d
File was created 1 #
2 # Copyright (C) 2017 PHYTEC Messtechnik GmbH
3 # Author: Wadim Egorov <w.egorov@phytec.de>
4 #
5 # SPDX-License-Identifier: GPL-2.0+
6 #
7
8 obj-y += phycore-rk3288.o
9
board/phytec/phycore_rk3288/phycore-rk3288.c
Diff comments   View file @ bafcf2d
File was created 1 /*
2 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
3 * Author: Wadim Egorov <w.egorov@phytec.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9
configs/phycore-rk3288_defconfig
Diff comments   View file @ bafcf2d
File was created 1 CONFIG_ARM=y
2 CONFIG_ARCH_ROCKCHIP=y
3 CONFIG_SYS_MALLOC_F_LEN=0x2000
4 CONFIG_ROCKCHIP_RK3288=y
5 CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
6 CONFIG_TARGET_PHYCORE_RK3288=y
7 CONFIG_SPL_STACK_R_ADDR=0x80000
8 CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk"
9 CONFIG_DEBUG_UART=y
10 CONFIG_SILENT_CONSOLE=y
11 CONFIG_CONSOLE_MUX=y
12 # CONFIG_DISPLAY_CPUINFO is not set
13 CONFIG_SPL_STACK_R=y
14 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
15 CONFIG_SPL_I2C_SUPPORT=y
16 CONFIG_SPL_POWER_SUPPORT=y
17 # CONFIG_CMD_IMLS is not set
18 CONFIG_CMD_GPT=y
19 CONFIG_CMD_MMC=y
20 CONFIG_CMD_SF=y
21 CONFIG_CMD_SPI=y
22 CONFIG_CMD_I2C=y
23 CONFIG_CMD_USB=y
24 CONFIG_CMD_GPIO=y
25 # CONFIG_CMD_SETEXPR is not set
26 CONFIG_CMD_CACHE=y
27 CONFIG_CMD_TIME=y
28 CONFIG_CMD_PMIC=y
29 CONFIG_CMD_REGULATOR=y
30 # CONFIG_SPL_DOS_PARTITION is not set
31 # CONFIG_SPL_ISO_PARTITION is not set
32 # CONFIG_SPL_EFI_PARTITION is not set
33 CONFIG_SPL_PARTITION_UUIDS=y
34 CONFIG_SPL_OF_CONTROL=y
35 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
36 CONFIG_REGMAP=y
37 CONFIG_SPL_REGMAP=y
38 CONFIG_SYSCON=y
39 CONFIG_SPL_SYSCON=y
40 # CONFIG_SPL_SIMPLE_BUS is not set
41 CONFIG_CLK=y
42 CONFIG_SPL_CLK=y
43 CONFIG_ROCKCHIP_GPIO=y
44 CONFIG_SYS_I2C_ROCKCHIP=y
45 CONFIG_MMC_DW=y
46 CONFIG_MMC_DW_ROCKCHIP=y
47 CONFIG_DM_ETH=y
48 CONFIG_ETH_DESIGNWARE=y
49 CONFIG_GMAC_ROCKCHIP=y
50 CONFIG_PINCTRL=y
51 CONFIG_SPL_PINCTRL=y
52 # CONFIG_SPL_PINCTRL_FULL is not set
53 CONFIG_PINCTRL_ROCKCHIP_RK3288=y
54 CONFIG_DM_PMIC=y
55 CONFIG_PMIC_RK8XX=y
56 CONFIG_DM_REGULATOR_FIXED=y
57 CONFIG_REGULATOR_RK8XX=y
58 CONFIG_PWM_ROCKCHIP=y
59 CONFIG_RAM=y
60 CONFIG_SPL_RAM=y
61 CONFIG_DEBUG_UART_BASE=0xff690000
62 CONFIG_DEBUG_UART_CLOCK=24000000
63 CONFIG_DEBUG_UART_SHIFT=2
64 CONFIG_SYS_NS16550=y
65 CONFIG_SYSRESET=y
66 CONFIG_USB=y
67 CONFIG_USB_STORAGE=y
68 CONFIG_USE_TINY_PRINTF=y
69 CONFIG_CMD_DHRYSTONE=y
70 CONFIG_ERRNO_STR=y
71
include/configs/phycore_rk3288.h
Diff comments   View file @ bafcf2d
File was created 1 /*
2 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
3 * Author: Wadim Egorov <w.egorov@phytec.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 #define ROCKCHIP_DEVICE_SETTINGS
12 #include <configs/rk3288_common.h>
13
14 #undef BOOT_TARGET_DEVICES
15
16 #define BOOT_TARGET_DEVICES(func) \
17 func(MMC, mmc, 0) \
18 func(MMC, mmc, 1)
19
20 #define CONFIG_ENV_IS_IN_MMC
21 #define CONFIG_SYS_MMC_ENV_DEV 1
22
23 #endif
24