net/phy/vitesse: Rework RGMII skew configuration for VSC8601

The VSC8601 config tried to add an RGMII skew based on #defines that no config defines. That's quite an ugly way to do it. Since the skew is only needed on RGMII interfaces, check the interface mode at runtime, and apply the settings accordingly. Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net/phy/vitesse: Rework RGMII skew configuration for VSC8601
The VSC8601 config tried to add an RGMII skew based on #defines that no config defines. That's quite an ugly way to do it. Since the skew is only needed on RGMII interfaces, check the interface mode at runtime, and apply the settings accordingly. Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
alex · Joe Hershberger · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent c7ac15388e
Showing 1 changed file with 24 additions and 19 deletions Side-by-side Diff
drivers/net/phy/vitesse.c
@@ -30,9 +30,8 @@
 #define MIIM_CIS8204_SLEDCON_INIT	0x1115
  
 /* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON		0x17
-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
-#define MIIM_VSC8601_SKEW_CTRL		0x1c
+#define MII_VSC8601_EPHY_CTL		0x17
+#define MII_VSC8601_EPHY_CTL_RGMII_SKEW	(1 << 8)
  
 #define PHY_EXT_PAGE_ACCESS    0x1f
 #define PHY_EXT_PAGE_ACCESS_GENERAL	0x10
  
  
  
@@ -142,26 +141,32 @@
 }
  
 /* Vitesse VSC8601 */
+/* This adds a skew for both TX and RX clocks, so the skew should only be
+ * applied to "rgmii-id" interfaces. It may not work as expected
+ * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
+static int vsc8601_add_skew(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL);
+	if (ret < 0)
+		return ret;
+
+	ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
+	return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret);
+}
+
 static int vsc8601_config(struct phy_device *phydev)
 {
-	/* Configure some basic stuff */
-#ifdef CONFIG_SYS_VSC8601_SKEWFIX
-	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
-			MIIM_VSC8601_EPHY_CON_INIT_SKEW);
-#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
-	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
-#define VSC8101_SKEW \
-	((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
-	| (CONFIG_SYS_VSC8601_SKEW_RX << 12))
-	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
-			VSC8101_SKEW);
-	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
-#endif
-#endif
+	int ret = 0;
  
-	genphy_config_aneg(phydev);
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		ret = vsc8601_add_skew(phydev);
  
-	return 0;
+	if (ret < 0)
+		return ret;
+
+	return genphy_config_aneg(phydev);
 }
  
 static int vsc8574_config(struct phy_device *phydev)
...	...	@@ -30,9 +30,8 @@
30	30	#define MIIM_CIS8204_SLEDCON_INIT 0x1115
31	31
32	32	/* Vitesse VSC8601 Extended PHY Control Register 1 */
33		-#define MIIM_VSC8601_EPHY_CON 0x17
34		-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
35		-#define MIIM_VSC8601_SKEW_CTRL 0x1c
	33	+#define MII_VSC8601_EPHY_CTL 0x17
	34	+#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
36	35
37	36	#define PHY_EXT_PAGE_ACCESS 0x1f
38	37	#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
39	38
40	39
41	40
...	...	@@ -142,26 +141,32 @@
142	141	}
143	142
144	143	/* Vitesse VSC8601 */
	144	+/* This adds a skew for both TX and RX clocks, so the skew should only be
	145	+ * applied to "rgmii-id" interfaces. It may not work as expected
	146	+ * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
	147	+static int vsc8601_add_skew(struct phy_device *phydev)
	148	+{
	149	+ int ret;
	150	+
	151	+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL);
	152	+ if (ret < 0)
	153	+ return ret;
	154	+
	155	+ ret \|= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
	156	+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret);
	157	+}
	158	+
145	159	static int vsc8601_config(struct phy_device *phydev)
146	160	{
147		- /* Configure some basic stuff */
148		-#ifdef CONFIG_SYS_VSC8601_SKEWFIX
149		- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
150		- MIIM_VSC8601_EPHY_CON_INIT_SKEW);
151		-#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
152		- phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
153		-#define VSC8101_SKEW \
154		- ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
155		- \| (CONFIG_SYS_VSC8601_SKEW_RX << 12))
156		- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
157		- VSC8101_SKEW);
158		- phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
159		-#endif
160		-#endif
	161	+ int ret = 0;
161	162
162		- genphy_config_aneg(phydev);
	163	+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	164	+ ret = vsc8601_add_skew(phydev);
163	165
164		- return 0;
	166	+ if (ret < 0)
	167	+ return ret;
	168	+
	169	+ return genphy_config_aneg(phydev);
165	170	}
166	171
167	172	static int vsc8574_config(struct phy_device *phydev)