Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit bb5783224b9b12eecf406761f82e3de2a2ca9dae

Authored by York Sun
1 parent d9c68b1444
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

driver/ddr/fsl: Fix tXP and tCKE 

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 22 additions and 14 deletions Side-by-side Diff

drivers/ddr/fsl/ctrl_regs.c
Diff comments   View file @ bb57832
... ... @@ -297,10 +297,13 @@
297 297 unsigned char taxpd_mclk = 0;
298 298 /* Mode register set cycle time (tMRD). */
299 299 unsigned char tmrd_mclk;
  300 +#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
  301 + const unsigned int mclk_ps = get_memory_clk_period_ps();
  302 +#endif
300 303  
301 304 #ifdef CONFIG_SYS_FSL_DDR4
302 305 /* tXP=max(4nCK, 6ns) */
303   - int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
  306 + int txp = max(mclk_ps * 4, 6000); /* unit=ps */
304 307 trwt_mclk = 2;
305 308 twrt_mclk = 1;
306 309 act_pd_exit_mclk = picos_to_mclk(txp);
307 310  
308 311  
... ... @@ -311,16 +314,19 @@
311 314 */
312 315 tmrd_mclk = max(24, picos_to_mclk(15000));
313 316 #elif defined(CONFIG_SYS_FSL_DDR3)
  317 + unsigned int data_rate = get_ddr_freq(0);
  318 + int txp;
314 319 /*
315 320 * (tXARD and tXARDS). Empirical?
316 321 * The DDR3 spec has not tXARD,
317 322 * we use the tXP instead of it.
318   - * tXP=max(3nCK, 7.5ns) for DDR3.
  323 + * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
  324 + * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
319 325 * spec has not the tAXPD, we use
320 326 * tAXPD=1, need design to confirm.
321 327 */
322   - int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
323   - unsigned int data_rate = get_ddr_freq(0);
  328 + txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
  329 +
324 330 tmrd_mclk = 4;
325 331 /* set the turnaround time */
326 332  
... ... @@ -578,6 +584,9 @@
578 584 unsigned char cke_pls;
579 585 /* Window for four activates (tFAW) */
580 586 unsigned short four_act;
  587 +#ifdef CONFIG_SYS_FSL_DDR3
  588 + const unsigned int mclk_ps = get_memory_clk_period_ps();
  589 +#endif
581 590  
582 591 /* FIXME add check that this must be less than acttorw_mclk */
583 592 add_lat_mclk = additive_latency;
584 593  
585 594  
... ... @@ -619,10 +628,17 @@
619 628 #ifdef CONFIG_SYS_FSL_DDR4
620 629 cpo = 0;
621 630 cke_pls = max(3, picos_to_mclk(5000));
  631 +#elif defined(CONFIG_SYS_FSL_DDR3)
  632 + /*
  633 + * cke pulse = max(3nCK, 7.5ns) for DDR3-800
  634 + * max(3nCK, 5.625ns) for DDR3-1066, 1333
  635 + * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
  636 + */
  637 + cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
  638 + (mclk_ps > 1245 ? 5625 : 5000)));
622 639 #else
623   - cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
  640 + cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
624 641 #endif
625   -
626 642 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
627 643  
628 644 ddr->timing_cfg_2 = (0
drivers/ddr/fsl/interactive.c
Diff comments   View file @ bb57832
... ... @@ -517,7 +517,6 @@
517 517 CTRL_OPTIONS(rcw_2),
518 518 CTRL_OPTIONS(ddr_cdr1),
519 519 CTRL_OPTIONS(ddr_cdr2),
520   - CTRL_OPTIONS(tcke_clock_pulse_width_ps),
521 520 CTRL_OPTIONS(tfaw_window_four_activates_ps),
522 521 CTRL_OPTIONS(trwt_override),
523 522 CTRL_OPTIONS(trwt),
... ... @@ -808,7 +807,6 @@
808 807 CTRL_OPTIONS(rcw_2),
809 808 CTRL_OPTIONS_HEX(ddr_cdr1),
810 809 CTRL_OPTIONS_HEX(ddr_cdr2),
811   - CTRL_OPTIONS(tcke_clock_pulse_width_ps),
812 810 CTRL_OPTIONS(tfaw_window_four_activates_ps),
813 811 CTRL_OPTIONS(trwt_override),
814 812 CTRL_OPTIONS(trwt),
drivers/ddr/fsl/options.c
Diff comments   View file @ bb57832
... ... @@ -777,10 +777,6 @@
777 777 */
778 778 popts->bstopre = 0x100;
779 779  
780   - /* Minimum CKE pulse width -- tCKE(MIN) */
781   - popts->tcke_clock_pulse_width_ps
782   - = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
783   -
784 780 /*
785 781 * Window for four activates -- tFAW
786 782 *
include/fsl_ddr_sdram.h
Diff comments   View file @ bb57832
... ... @@ -51,7 +51,6 @@
51 51 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
52 52 #endif
53 53 #elif defined(CONFIG_SYS_FSL_DDR3)
54   -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
55 54 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
56 55 #ifndef CONFIG_FSL_SDRAM_TYPE
57 56 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
... ... @@ -352,7 +351,6 @@
352 351 unsigned int twot_en;
353 352 unsigned int threet_en;
354 353 unsigned int bstopre;
355   - unsigned int tcke_clock_pulse_width_ps; /* tCKE */
356 354 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
357 355  
358 356 /* Rtt impedance */