Eric Lee / smarc-uboot

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Commit bb71569f51762cdee876fc4a6154624285d548f5

Authored by Peng Fan
1 parent b3b0a429ef
Exists in smarc-m6.0.1_2.1.0-ga

MLK-12616-4 OCOTP: Update driver for mx6ull 

The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other
banks use 256 bits. So we have to adjust the word and bank index when accessing
the bank 8.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 1 changed file with 38 additions and 5 deletions Side-by-side Diff

drivers/misc/mxc_ocotp.c
Diff comments   View file @ bb71569
... ... @@ -7,7 +7,7 @@
7 7 * which is based on Freescale's
8 8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
9 9 * which is:
10   - * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
  10 + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
11 11 *
12 12 * SPDX-License-Identifier: GPL-2.0+
13 13 */
... ... @@ -61,6 +61,8 @@
61 61 #define FUSE_BANK_SIZE 0x80
62 62 #ifdef CONFIG_MX6SL
63 63 #define FUSE_BANKS 8
  64 +#elif defined CONFIG_MX6ULL
  65 +#define FUSE_BANKS 9
64 66 #else
65 67 #define FUSE_BANKS 16
66 68 #endif
... ... @@ -76,7 +78,7 @@
76 78  
77 79 /*
78 80 * There is a hole in shadow registers address map of size 0x100
79   - * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
  81 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, iMX6UL and iMX6ULL.
80 82 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
81 83 * we should account for this hole in address space.
82 84 *
... ... @@ -98,7 +100,10 @@
98 100 if ((index == 0) || is_cpu_type(MXC_CPU_MX6SL) ||
99 101 is_cpu_type(MXC_CPU_MX7D))
100 102 phy_index = index;
101   - else if (is_cpu_type(MXC_CPU_MX6UL)) {
  103 + else if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) {
  104 + if (is_cpu_type(MXC_CPU_MX6ULL) && index == 8)
  105 + index = 7;
  106 +
102 107 if (index >= 6)
103 108 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
104 109 else
105 110  
... ... @@ -113,11 +118,27 @@
113 118 }
114 119 return phy_index;
115 120 }
  121 +
  122 +u32 fuse_word_physical(u32 bank, u32 word_index)
  123 +{
  124 + if (is_cpu_type(MXC_CPU_MX6ULL)) {
  125 + if (bank == 8)
  126 + word_index = word_index + 4;
  127 + }
  128 +
  129 + return word_index;
  130 +}
116 131 #else
117 132 u32 fuse_bank_physical(int index)
118 133 {
119 134 return index;
120 135 }
  136 +
  137 +u32 fuse_word_physical(u32 bank, u32 word_index)
  138 +{
  139 + return word_index;
  140 +}
  141 +
121 142 #endif
122 143  
123 144 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
... ... @@ -143,6 +164,14 @@
143 164 return -EINVAL;
144 165 }
145 166  
  167 + if (is_cpu_type(MXC_CPU_MX6ULL)) {
  168 + if ((bank == 7 || bank == 8) &&
  169 + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
  170 + printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", caller);
  171 + return -EINVAL;
  172 + }
  173 + }
  174 +
146 175 enable_ocotp_clk(1);
147 176  
148 177 wait_busy(*regs, 1);
149 178  
150 179  
... ... @@ -177,14 +206,16 @@
177 206 struct ocotp_regs *regs;
178 207 int ret;
179 208 u32 phy_bank;
  209 + u32 phy_word;
180 210  
181 211 ret = prepare_read(&regs, bank, word, val, __func__);
182 212 if (ret)
183 213 return ret;
184 214  
185 215 phy_bank = fuse_bank_physical(bank);
  216 + phy_word = fuse_word_physical(bank, word);
186 217  
187   - *val = readl(&regs->bank[phy_bank].fuse_regs[word << 2]);
  218 + *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
188 219  
189 220 return finish_access(regs, __func__);
190 221 }
191 222  
192 223  
... ... @@ -326,14 +357,16 @@
326 357 struct ocotp_regs *regs;
327 358 int ret;
328 359 u32 phy_bank;
  360 + u32 phy_word;
329 361  
330 362 ret = prepare_write(&regs, bank, word, __func__);
331 363 if (ret)
332 364 return ret;
333 365  
334 366 phy_bank = fuse_bank_physical(bank);
  367 + phy_word = fuse_word_physical(bank, word);
335 368  
336   - writel(val, &regs->bank[phy_bank].fuse_regs[word << 2]);
  369 + writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
337 370  
338 371 return finish_access(regs, __func__);
339 372 }