board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL

In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL
In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha · York Sun
1 parent 3051f3f999
Showing 8 changed files with 450 additions and 268 deletions Side-by-side Diff
board/freescale/p1_p2_rdb/Makefile
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p1_p2_rdb/spl.c
board/freescale/p1_p2_rdb/spl_minimal.c
board/freescale/p1_p2_rdb/tlb.c
include/configs/P1_P2_RDB.h
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
@@ -4,9 +4,28 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-y	+= p1_p2_rdb.o
+obj-$(CONFIG_PCI)  += pci.o
+endif
 obj-y	+= ddr.o
 obj-y	+= law.o
-obj-$(CONFIG_PCI)  += pci.o
 obj-y	+= tlb.o
+
+endif
@@ -180,27 +180,22 @@
  
 phys_size_t fixed_sdram (void)
 {
-	char buf[32];
 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
 	size_t ddr_size;
 	struct cpu_type *cpu;
 	ulong ddr_freq, ddr_freq_mhz;
  
 	cpu = gd->arch.cpu;
-	/* P1020 and it's derivatives support max 32bit DDR width */
-	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
-		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
-	} else {
-		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	}
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
 #if defined(CONFIG_SYS_RAMBOOT)
 	return ddr_size;
 #endif
 	ddr_freq = get_ddr_freq(0);
 	ddr_freq_mhz = ddr_freq / 1000000;
  
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
+	printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
  
 	if(ddr_freq_mhz <= 400)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@@ -211,8 +206,7 @@
 	else if(ddr_freq_mhz <= 800)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
 	else
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
+		panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
  
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+	if (sysclk_gpio == 0)
+		return SYSCLK_66;
+	else
+		return SYSCLK_100;
+
+	return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+	if (sysclk_gpio == 0)
+		return SYSCLK_66;
+	else
+		return SYSCLK_100;
+
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
@@ -37,6 +37,7 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
  
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -55,6 +56,7 @@
 			0, 4, BOOKE_PAGESZ_256K, 1),
  
 #endif /* #if defined(CONFIG_PCI) */
+#endif
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -65,7 +67,21 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
  
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 7, BOOKE_PAGESZ_1G, 1)
@@ -20,41 +20,121 @@
  
 #ifdef CONFIG_P1011RDB
 #define CONFIG_P1011
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
 #endif
 #ifdef CONFIG_P1020RDB
 #define CONFIG_P1020
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
 #endif
 #ifdef CONFIG_P2010RDB
 #define CONFIG_P2010
+#define CONFIG_SYS_L2_SIZE	(512 << 10)
 #endif
 #ifdef CONFIG_P2020RDB
 #define CONFIG_P2020
+#define CONFIG_SYS_L2_SIZE	(512 << 10)
 #endif
  
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT		1
-#define CONFIG_RAMBOOT_NAND		1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE		0xf8f82000
-#endif /* CONFIG_NAND_SPL */
-#endif
-
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD		1
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(129 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
 #endif
+#endif
  
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH		1
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
 #endif
+#endif
  
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
  
@@ -64,8 +144,12 @@
 #endif
  
 #ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
+#endif
  
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
  
  
  
  
  
@@ -120,22 +204,45 @@
 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
  
- /*
-  * Config the L2 Cache as L2 SRAM
-  */
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
 #else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
 #endif
-#define CONFIG_SYS_L2_SIZE		(512 << 10)
-#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#endif
  
-#define CONFIG_SYS_CCSRBAR		0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
  
@@ -146,7 +253,15 @@
  
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
  
-#define CONFIG_SYS_SDRAM_SIZE	1024 	/* DDR size on P1_P2 RDBs */
+#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
+/*
+ * P1020 and it's derivatives support max 32bit DDR width
+ * So Reduce available DDR size
+*/
+#define CONFIG_SYS_SDRAM_SIZE	512
+#else
+#define CONFIG_SYS_SDRAM_SIZE	1024
+#endif
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
  
@@ -201,14 +316,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
  
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
-    defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
  
  
@@ -241,21 +348,12 @@
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
  
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
-#else
-#define CONFIG_SYS_NAND_BASE		0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-#endif
  
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
@@ -264,15 +362,6 @@
 #define CONFIG_NAND_FSL_ELBC		1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
  
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
@@ -288,7 +377,7 @@
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
  
-#ifdef CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
@@ -323,7 +412,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
  
  
  
  
  
@@ -490,32 +579,44 @@
 /*
  * Environment
  */
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-	#define CONFIG_ENV_IS_IN_NAND	1
-	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-	#define CONFIG_ENV_OFFSET	((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
-	#define CONFIG_ENV_IS_IN_SPI_FLASH
-	#define CONFIG_ENV_SPI_BUS	0
-	#define CONFIG_ENV_SPI_CS	0
-	#define CONFIG_ENV_SPI_MAX_HZ	10000000
-	#define CONFIG_ENV_SPI_MODE	0
-	#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
-	#define CONFIG_ENV_SECT_SIZE	0x10000
-	#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-	#define CONFIG_ENV_SIZE		0x2000
-	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
+
  
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj	:= $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
-		$(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-		-ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
-	@rm -f $@
-	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
-	@rm -f $@
-	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
-	@rm -f $@
-	ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
-	@rm -f $@
-	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
-	@rm -f $@
-	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
-	@rm -f $@
-	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_MASK     0x00200000
-#define BOARDREV_MASK   0x10100000
-#define BOARDREV_B      0x10100000
-#define BOARDREV_C      0x00100000
-
-#define SYSCLK_66       66666666
-#define SYSCLK_50       50000000
-#define SYSCLK_100      100000000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
-	uint plat_ratio, bus_clk, sys_clk = 0;
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-	uint val, temp, sysclk_mask;
-
-	val = pgpio->gpdat;
-	sysclk_mask = val & SYSCLK_MASK;
-	temp = val & BOARDREV_MASK;
-	if (temp == BOARDREV_C) {
-		if(sysclk_mask == 0)
-			sys_clk = SYSCLK_66;
-		else
-			sys_clk = SYSCLK_100;
-	} else if (temp == BOARDREV_B) {
-		if(sysclk_mask == 0)
-			sys_clk = SYSCLK_66;
-		else
-			sys_clk = SYSCLK_50;
-	}
-
-	plat_ratio = gur->porpllsr & 0x0000003e;
-	plat_ratio >>= 1;
-	bus_clk = plat_ratio * sys_clk;
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-			bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* copy code to DDR and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
-			CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
...	...	@@ -4,9 +4,28 @@
4	4	# SPDX-License-Identifier: GPL-2.0+
5	5	#
6	6
	7	+MINIMAL=
	8	+
	9	+ifdef CONFIG_SPL_BUILD
	10	+ifdef CONFIG_SPL_INIT_MINIMAL
	11	+MINIMAL=y
	12	+endif
	13	+endif
	14	+
	15	+ifdef MINIMAL
	16	+
	17	+obj-y += spl_minimal.o tlb.o law.o
	18	+
	19	+else
	20	+ifdef CONFIG_SPL_BUILD
	21	+obj-y += spl.o
	22	+else
7	23	obj-y += p1_p2_rdb.o
	24	+obj-$(CONFIG_PCI) += pci.o
	25	+endif
8	26	obj-y += ddr.o
9	27	obj-y += law.o
10		-obj-$(CONFIG_PCI) += pci.o
11	28	obj-y += tlb.o
	29	+
	30	+endif
...	...	@@ -180,27 +180,22 @@
180	180
181	181	phys_size_t fixed_sdram (void)
182	182	{
183		- char buf[32];
184	183	fsl_ddr_cfg_regs_t ddr_cfg_regs;
185	184	size_t ddr_size;
186	185	struct cpu_type *cpu;
187	186	ulong ddr_freq, ddr_freq_mhz;
188	187
189	188	cpu = gd->arch.cpu;
190		- /* P1020 and it's derivatives support max 32bit DDR width */
191		- if (cpu->soc_ver == SVR_P1020 \|\| cpu->soc_ver == SVR_P1011) {
192		- ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
193		- } else {
194		- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
195		- }
	189	+
	190	+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	191	+
196	192	#if defined(CONFIG_SYS_RAMBOOT)
197	193	return ddr_size;
198	194	#endif
199	195	ddr_freq = get_ddr_freq(0);
200	196	ddr_freq_mhz = ddr_freq / 1000000;
201	197
202		- printf("Configuring DDR for %s MT/s data rate\n",
203		- strmhz(buf, ddr_freq));
	198	+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
204	199
205	200	if(ddr_freq_mhz <= 400)
206	201	memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
...	...	@@ -211,8 +206,7 @@
211	206	else if(ddr_freq_mhz <= 800)
212	207	memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
213	208	else
214		- panic("Unsupported DDR data rate %s MT/s data rate\n",
215		- strmhz(buf, ddr_freq));
	209	+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
216	210
217	211	/* P1020 and it's derivatives support max 32bit DDR width */
218	212	if (cpu->soc_ver == SVR_P1020 \|\| cpu->soc_ver == SVR_P1011) {
	1	+/*
	2	+ * Copyright 2013 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <ns16550.h>
	9	+#include <malloc.h>
	10	+#include <mmc.h>
	11	+#include <nand.h>
	12	+#include <i2c.h>
	13	+#include <fsl_esdhc.h>
	14	+#include <spi_flash.h>
	15	+
	16	+DECLARE_GLOBAL_DATA_PTR;
	17	+
	18	+#define SYSCLK_MASK 0x00200000
	19	+#define BOARDREV_MASK 0x10100000
	20	+
	21	+#define SYSCLK_66 66666666
	22	+#define SYSCLK_100 100000000
	23	+
	24	+unsigned long get_board_sys_clk(ulong dummy)
	25	+{
	26	+ ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	27	+ u32 val_gpdat, sysclk_gpio;
	28	+
	29	+ val_gpdat = in_be32(&pgpio->gpdat);
	30	+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
	31	+
	32	+ if (sysclk_gpio == 0)
	33	+ return SYSCLK_66;
	34	+ else
	35	+ return SYSCLK_100;
	36	+
	37	+ return 0;
	38	+}
	39	+
	40	+phys_size_t get_effective_memsize(void)
	41	+{
	42	+ return CONFIG_SYS_L2_SIZE;
	43	+}
	44	+
	45	+void board_init_f(ulong bootflag)
	46	+{
	47	+ u32 plat_ratio, bus_clk;
	48	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	49	+
	50	+ console_init_f();
	51	+
	52	+ /* Set pmuxcr to allow both i2c1 and i2c2 */
	53	+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) \| 0x1000);
	54	+ setbits_be32(&gur->pmuxcr,
	55	+ in_be32(&gur->pmuxcr) \| MPC85xx_PMUXCR_SD_DATA);
	56	+
	57	+ /* Read back the register to synchronize the write. */
	58	+ in_be32(&gur->pmuxcr);
	59	+
	60	+#ifdef CONFIG_SPL_SPI_BOOT
	61	+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	62	+#endif
	63	+
	64	+ /* initialize selected port with appropriate baud rate */
	65	+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
	66	+ plat_ratio >>= 1;
	67	+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
	68	+ gd->bus_clk = bus_clk;
	69	+
	70	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	71	+ bus_clk / 16 / CONFIG_BAUDRATE);
	72	+#ifdef CONFIG_SPL_MMC_BOOT
	73	+ puts("\nSD boot...\n");
	74	+#elif defined(CONFIG_SPL_SPI_BOOT)
	75	+ puts("\nSPI Flash boot...\n");
	76	+#endif
	77	+
	78	+ /* copy code to RAM and jump to it - this should not return */
	79	+ /* NOTE - code has to be copied out of NAND buffer before
	80	+ * other blocks can be read.
	81	+ */
	82	+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
	83	+}
	84	+
	85	+void board_init_r(gd_t *gd, ulong dest_addr)
	86	+{
	87	+ /* Pointer is writable since we allocated a register for it */
	88	+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
	89	+ bd_t *bd;
	90	+
	91	+ memset(gd, 0, sizeof(gd_t));
	92	+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
	93	+ memset(bd, 0, sizeof(bd_t));
	94	+ gd->bd = bd;
	95	+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
	96	+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
	97	+
	98	+ probecpu();
	99	+ get_clocks();
	100	+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	101	+ CONFIG_SPL_RELOC_MALLOC_SIZE);
	102	+
	103	+#ifdef CONFIG_SPL_MMC_BOOT
	104	+ mmc_initialize(bd);
	105	+#endif
	106	+ /* relocate environment function pointers etc. */
	107	+#ifdef CONFIG_SPL_NAND_BOOT
	108	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	109	+ (uchar *)CONFIG_ENV_ADDR);
	110	+#endif
	111	+#ifdef CONFIG_SPL_NAND_BOOT
	112	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	113	+ (uchar *)CONFIG_ENV_ADDR);
	114	+#endif
	115	+#ifdef CONFIG_SPL_MMC_BOOT
	116	+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	117	+ (uchar *)CONFIG_ENV_ADDR);
	118	+#endif
	119	+#ifdef CONFIG_SPL_SPI_BOOT
	120	+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	121	+ (uchar *)CONFIG_ENV_ADDR);
	122	+#endif
	123	+
	124	+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	125	+ gd->env_valid = 1;
	126	+
	127	+ gd->ram_size = initdram(0);
	128	+#ifdef CONFIG_SPL_NAND_BOOT
	129	+ puts("Tertiary program loader running in sram...");
	130	+#else
	131	+ puts("Second program loader running in sram...\n");
	132	+#endif
	133	+
	134	+#ifdef CONFIG_SPL_MMC_BOOT
	135	+ mmc_boot();
	136	+#elif defined(CONFIG_SPL_SPI_BOOT)
	137	+ spi_boot();
	138	+#elif defined(CONFIG_SPL_NAND_BOOT)
	139	+ nand_boot();
	140	+#endif
	141	+}
	1	+/*
	2	+ * Copyright 2011 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <ns16550.h>
	9	+#include <asm/io.h>
	10	+#include <nand.h>
	11	+#include <linux/compiler.h>
	12	+#include <asm/fsl_law.h>
	13	+#include <fsl_ddr_sdram.h>
	14	+#include <asm/global_data.h>
	15	+
	16	+DECLARE_GLOBAL_DATA_PTR;
	17	+#define SYSCLK_MASK 0x00200000
	18	+#define BOARDREV_MASK 0x10100000
	19	+
	20	+#define SYSCLK_66 66666666
	21	+#define SYSCLK_100 100000000
	22	+
	23	+unsigned long get_board_sys_clk(ulong dummy)
	24	+{
	25	+ ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	26	+ u32 val_gpdat, sysclk_gpio;
	27	+
	28	+ val_gpdat = in_be32(&pgpio->gpdat);
	29	+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
	30	+
	31	+ if (sysclk_gpio == 0)
	32	+ return SYSCLK_66;
	33	+ else
	34	+ return SYSCLK_100;
	35	+
	36	+ return 0;
	37	+}
	38	+
	39	+void board_init_f(ulong bootflag)
	40	+{
	41	+ u32 plat_ratio;
	42	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	43	+
	44	+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
	45	+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
	46	+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
	47	+#endif
	48	+
	49	+ /* initialize selected port with appropriate baud rate */
	50	+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
	51	+ plat_ratio >>= 1;
	52	+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
	53	+
	54	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	55	+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
	56	+
	57	+ puts("\nNAND boot... ");
	58	+
	59	+ /* copy code to RAM and jump to it - this should not return */
	60	+ /* NOTE - code has to be copied out of NAND buffer before
	61	+ * other blocks can be read.
	62	+ */
	63	+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
	64	+}
	65	+
	66	+void board_init_r(gd_t *gd, ulong dest_addr)
	67	+{
	68	+ puts("\nSecond program loader running in sram...");
	69	+ nand_boot();
	70	+}
	71	+
	72	+void putc(char c)
	73	+{
	74	+ if (c == '\n')
	75	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
	76	+
	77	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
	78	+}
	79	+
	80	+void puts(const char *str)
	81	+{
	82	+ while (*str)
	83	+ putc(*str++);
	84	+}
...	...	@@ -37,6 +37,7 @@
37	37	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
38	38	0, 1, BOOKE_PAGESZ_1M, 1),
39	39
	40	+#ifndef CONFIG_SPL_BUILD
40	41	/* W*G - Flash/promjet, localbus */
41	42	/* This will be changed to IG* after relocation to RAM. */
42	43	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
...	...	@@ -55,6 +56,7 @@
55	56	0, 4, BOOKE_PAGESZ_256K, 1),
56	57
57	58	#endif /* #if defined(CONFIG_PCI) */
	59	+#endif
58	60	/* IG - NAND */
59	61	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
60	62	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -65,7 +67,21 @@
65	67	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
66	68	0, 6, BOOKE_PAGESZ_1M, 1),
67	69
68		-#if defined(CONFIG_SYS_RAMBOOT)
	70	+#ifdef CONFIG_SYS_INIT_L2_ADDR
	71	+ /* IG - L2SRAM */
	72	+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
	73	+ MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_G,
	74	+ 0, 11, BOOKE_PAGESZ_256K, 1),
	75	+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
	76	+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
	77	+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
	78	+ MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	79	+ 0, 12, BOOKE_PAGESZ_256K, 1),
	80	+#endif
	81	+#endif
	82	+
	83	+#if defined(CONFIG_SYS_RAMBOOT) \|\| \
	84	+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
69	85	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
70	86	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
71	87	0, 7, BOOKE_PAGESZ_1G, 1)
...	...	@@ -20,41 +20,121 @@
20	20
21	21	#ifdef CONFIG_P1011RDB
22	22	#define CONFIG_P1011
	23	+#define CONFIG_SYS_L2_SIZE (256 << 10)
23	24	#endif
24	25	#ifdef CONFIG_P1020RDB
25	26	#define CONFIG_P1020
	27	+#define CONFIG_SYS_L2_SIZE (256 << 10)
26	28	#endif
27	29	#ifdef CONFIG_P2010RDB
28	30	#define CONFIG_P2010
	31	+#define CONFIG_SYS_L2_SIZE (512 << 10)
29	32	#endif
30	33	#ifdef CONFIG_P2020RDB
31	34	#define CONFIG_P2020
	35	+#define CONFIG_SYS_L2_SIZE (512 << 10)
32	36	#endif
33	37
34		-#ifdef CONFIG_NAND
35		-#define CONFIG_NAND_U_BOOT 1
36		-#define CONFIG_RAMBOOT_NAND 1
37		-#ifdef CONFIG_NAND_SPL
38		-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
39		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
40		-#else
41		-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
42		-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
43		-#endif /* CONFIG_NAND_SPL */
44		-#endif
45		-
46	38	#ifdef CONFIG_SDCARD
47		-#define CONFIG_RAMBOOT_SDCARD 1
48		-#define CONFIG_SYS_TEXT_BASE 0x11000000
49		-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
	39	+#define CONFIG_SPL
	40	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	41	+#define CONFIG_SPL_ENV_SUPPORT
	42	+#define CONFIG_SPL_SERIAL_SUPPORT
	43	+#define CONFIG_SPL_MMC_SUPPORT
	44	+#define CONFIG_SPL_MMC_MINIMAL
	45	+#define CONFIG_SPL_FLUSH_IMAGE
	46	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	47	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	48	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	49	+#define CONFIG_SPL_I2C_SUPPORT
	50	+#define CONFIG_SYS_TEXT_BASE 0x11001000
	51	+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	52	+#define CONFIG_SPL_PAD_TO 0x20000
	53	+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
	54	+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	55	+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
	56	+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
	57	+#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
	58	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	59	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	60	+#define CONFIG_SPL_MMC_BOOT
	61	+#ifdef CONFIG_SPL_BUILD
	62	+#define CONFIG_SPL_COMMON_INIT_DDR
50	63	#endif
	64	+#endif
51	65
52	66	#ifdef CONFIG_SPIFLASH
53		-#define CONFIG_RAMBOOT_SPIFLASH 1
54		-#define CONFIG_SYS_TEXT_BASE 0x11000000
55		-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
	67	+#define CONFIG_SPL
	68	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	69	+#define CONFIG_SPL_ENV_SUPPORT
	70	+#define CONFIG_SPL_SERIAL_SUPPORT
	71	+#define CONFIG_SPL_SPI_SUPPORT
	72	+#define CONFIG_SPL_SPI_FLASH_SUPPORT
	73	+#define CONFIG_SPL_SPI_FLASH_MINIMAL
	74	+#define CONFIG_SPL_FLUSH_IMAGE
	75	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	76	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	77	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	78	+#define CONFIG_SPL_I2C_SUPPORT
	79	+#define CONFIG_SYS_TEXT_BASE 0x11001000
	80	+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	81	+#define CONFIG_SPL_PAD_TO 0x20000
	82	+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
	83	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	84	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
	85	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
	86	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
	87	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	88	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	89	+#define CONFIG_SPL_SPI_BOOT
	90	+#ifdef CONFIG_SPL_BUILD
	91	+#define CONFIG_SPL_COMMON_INIT_DDR
56	92	#endif
	93	+#endif
57	94
	95	+#ifdef CONFIG_NAND
	96	+#define CONFIG_SPL
	97	+#define CONFIG_TPL
	98	+#ifdef CONFIG_TPL_BUILD
	99	+#define CONFIG_SPL_NAND_BOOT
	100	+#define CONFIG_SPL_FLUSH_IMAGE
	101	+#define CONFIG_SPL_ENV_SUPPORT
	102	+#define CONFIG_SPL_NAND_INIT
	103	+#define CONFIG_SPL_SERIAL_SUPPORT
	104	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	105	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	106	+#define CONFIG_SPL_I2C_SUPPORT
	107	+#define CONFIG_SPL_NAND_SUPPORT
	108	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	109	+#define CONFIG_SPL_COMMON_INIT_DDR
	110	+#define CONFIG_SPL_MAX_SIZE (128 << 10)
	111	+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	112	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	113	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
	114	+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
	115	+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
	116	+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
	117	+#elif defined(CONFIG_SPL_BUILD)
	118	+#define CONFIG_SPL_INIT_MINIMAL
	119	+#define CONFIG_SPL_SERIAL_SUPPORT
	120	+#define CONFIG_SPL_NAND_SUPPORT
	121	+#define CONFIG_SPL_FLUSH_IMAGE
	122	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	123	+#define CONFIG_SPL_TEXT_BASE 0xff800000
	124	+#define CONFIG_SPL_MAX_SIZE 4096
	125	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
	126	+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
	127	+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
	128	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
	129	+#endif /* not CONFIG_TPL_BUILD */
	130	+
	131	+#define CONFIG_SPL_PAD_TO 0x20000
	132	+#define CONFIG_TPL_PAD_TO 0x20000
	133	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	134	+#define CONFIG_SYS_TEXT_BASE 0x11001000
	135	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	136	+#endif
	137	+
58	138	#ifndef CONFIG_SYS_TEXT_BASE
59	139	#define CONFIG_SYS_TEXT_BASE 0xeff40000
60	140	#endif
61	141
...	...	@@ -64,8 +144,12 @@
64	144	#endif
65	145
66	146	#ifndef CONFIG_SYS_MONITOR_BASE
	147	+#ifdef CONFIG_SPL_BUILD
	148	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	149	+#else
67	150	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
68	151	#endif
	152	+#endif
69	153
70	154	/* High Level Configuration Options */
71	155	#define CONFIG_BOOKE 1 /* BOOKE */
72	156
73	157
74	158
75	159
76	160
...	...	@@ -120,22 +204,45 @@
120	204	#define CONFIG_SYS_MEMTEST_END 0x1fffffff
121	205	#define CONFIG_PANIC_HANG /* do not reset board on panic */
122	206
123		- /*
124		- * Config the L2 Cache as L2 SRAM
125		- */
	207	+/*
	208	+ * Config the L2 Cache as L2 SRAM
	209	+*/
	210	+#if defined(CONFIG_SPL_BUILD)
	211	+#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
126	212	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
127		-#ifdef CONFIG_PHYS_64BIT
128		-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
	213	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	214	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	215	+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	216	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
	217	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
	218	+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
	219	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
	220	+#if defined(CONFIG_P2020RDB)
	221	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
129	222	#else
	223	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
	224	+#endif
	225	+#elif defined(CONFIG_NAND)
	226	+#ifdef CONFIG_TPL_BUILD
	227	+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
130	228	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	229	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	230	+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	231	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
	232	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
	233	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
	234	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
	235	+#else
	236	+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	237	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	238	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	239	+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
	240	+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
	241	+#endif /* CONFIG_TPL_BUILD */
131	242	#endif
132		-#define CONFIG_SYS_L2_SIZE (512 << 10)
133		-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	243	+#endif
134	244
135		-#define CONFIG_SYS_CCSRBAR 0xffe00000
136		-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
137		-
138		-#if defined(CONFIG_NAND_SPL)
	245	+#ifdef CONFIG_SPL_BUILD
139	246	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
140	247	#endif
141	248
...	...	@@ -146,7 +253,15 @@
146	253
147	254	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
148	255
149		-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
	256	+#if defined(CONFIG_P1011RDB) \|\| defined(CONFIG_P1020RDB)
	257	+/*
	258	+ * P1020 and it's derivatives support max 32bit DDR width
	259	+ * So Reduce available DDR size
	260	+*/
	261	+#define CONFIG_SYS_SDRAM_SIZE 512
	262	+#else
	263	+#define CONFIG_SYS_SDRAM_SIZE 1024
	264	+#endif
150	265	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
151	266	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
152	267
...	...	@@ -201,14 +316,6 @@
201	316	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
202	317	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
203	318
204		-#if defined(CONFIG_RAMBOOT_NAND) \|\| defined(CONFIG_RAMBOOT_SDCARD) \|\| \
205		- defined(CONFIG_RAMBOOT_SPIFLASH)
206		-#define CONFIG_SYS_RAMBOOT
207		-#define CONFIG_SYS_EXTRA_ENV_RELOC
208		-#else
209		-#undef CONFIG_SYS_RAMBOOT
210		-#endif
211		-
212	319	#define CONFIG_FLASH_CFI_DRIVER
213	320	#define CONFIG_SYS_FLASH_CFI
214	321	#define CONFIG_SYS_FLASH_EMPTY_INFO
215	322
216	323
...	...	@@ -241,21 +348,12 @@
241	348	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
242	349	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
243	350
244		-#ifndef CONFIG_NAND_SPL
245		-#define CONFIG_SYS_NAND_BASE 0xffa00000
	351	+#define CONFIG_SYS_NAND_BASE 0xff800000
246	352	#ifdef CONFIG_PHYS_64BIT
247		-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
	353	+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
248	354	#else
249	355	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
250	356	#endif
251		-#else
252		-#define CONFIG_SYS_NAND_BASE 0xfff00000
253		-#ifdef CONFIG_PHYS_64BIT
254		-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
255		-#else
256		-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
257		-#endif
258		-#endif
259	357
260	358	#define CONFIG_CMD_NAND
261	359	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
...	...	@@ -264,15 +362,6 @@
264	362	#define CONFIG_NAND_FSL_ELBC 1
265	363	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
266	364
267		-/* NAND boot: 4K NAND loader config */
268		-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
269		-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
270		-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
271		-#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
272		-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
273		-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
274		-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
275		-
276	365	/* NAND flash config */
277	366	#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
278	367	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
...	...	@@ -288,7 +377,7 @@
288	377	\| OR_FCM_TRLX \
289	378	\| OR_FCM_EHTR)
290	379
291		-#ifdef CONFIG_RAMBOOT_NAND
	380	+#ifdef CONFIG_NAND
292	381	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
293	382	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
294	383	#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
...	...	@@ -323,7 +412,7 @@
323	412	#define CONFIG_SYS_NS16550_SERIAL
324	413	#define CONFIG_SYS_NS16550_REG_SIZE 1
325	414	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
326		-#ifdef CONFIG_NAND_SPL
	415	+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
327	416	#define CONFIG_NS16550_MIN_FUNCTIONS
328	417	#endif
329	418
330	419
331	420
332	421
333	422
...	...	@@ -490,32 +579,44 @@
490	579	/*
491	580	* Environment
492	581	*/
493		-#if defined(CONFIG_SYS_RAMBOOT)
494		-#if defined(CONFIG_RAMBOOT_NAND)
495		- #define CONFIG_ENV_IS_IN_NAND 1
496		- #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
497		- #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
498		-#elif defined(CONFIG_RAMBOOT_SDCARD)
	582	+#ifdef CONFIG_SPIFLASH
	583	+#define CONFIG_ENV_IS_IN_SPI_FLASH
	584	+#define CONFIG_ENV_SPI_BUS 0
	585	+#define CONFIG_ENV_SPI_CS 0
	586	+#define CONFIG_ENV_SPI_MAX_HZ 10000000
	587	+#define CONFIG_ENV_SPI_MODE 0
	588	+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	589	+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	590	+#define CONFIG_ENV_SECT_SIZE 0x10000
	591	+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	592	+#elif defined(CONFIG_SDCARD)
499	593	#define CONFIG_ENV_IS_IN_MMC
500	594	#define CONFIG_FSL_FIXED_MMC_LOCATION
501		-#define CONFIG_ENV_SIZE 0x2000
502		-#define CONFIG_SYS_MMC_ENV_DEV 0
503		-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
504		- #define CONFIG_ENV_IS_IN_SPI_FLASH
505		- #define CONFIG_ENV_SPI_BUS 0
506		- #define CONFIG_ENV_SPI_CS 0
507		- #define CONFIG_ENV_SPI_MAX_HZ 10000000
508		- #define CONFIG_ENV_SPI_MODE 0
509		- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
510		- #define CONFIG_ENV_SECT_SIZE 0x10000
511		- #define CONFIG_ENV_SIZE 0x2000
	595	+#define CONFIG_ENV_SIZE 0x2000
	596	+#define CONFIG_SYS_MMC_ENV_DEV 0
	597	+#define CONFIG_ENV_OFFSET (512 * 0x800)
	598	+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	599	+#elif defined(CONFIG_NAND)
	600	+#ifdef CONFIG_TPL_BUILD
	601	+#define CONFIG_ENV_SIZE 0x2000
	602	+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	603	+#else
	604	+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
512	605	#endif
	606	+#define CONFIG_ENV_IS_IN_NAND
	607	+#define CONFIG_ENV_OFFSET (1024 * 1024)
	608	+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
	609	+#elif defined(CONFIG_SYS_RAMBOOT)
	610	+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
	611	+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	612	+#define CONFIG_ENV_SIZE 0x2000
513	613	#else
514		- #define CONFIG_ENV_IS_IN_FLASH 1
515		- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
516		- #define CONFIG_ENV_SIZE 0x2000
517		- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
	614	+#define CONFIG_ENV_IS_IN_FLASH
	615	+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	616	+#define CONFIG_ENV_SIZE 0x2000
	617	+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
518	618	#endif
	619	+
519	620
520	621	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
521	622	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1		-#
2		-# (C) Copyright 2007
3		-# Stefan Roese, DENX Software Engineering, sr@denx.de.
4		-#
5		-# Copyright 2009-2011 Freescale Semiconductor, Inc.
6		-#
7		-# SPDX-License-Identifier: GPL-2.0+
8		-#
9		-
10		-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
11		-PAD_TO := 0xfff01000
12		-
13		-nandobj := $(objtree)/nand_spl/
14		-
15		-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
16		-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
17		- $(LDFLAGS) $(LDFLAGS_FINAL)
18		-asflags-y += -DCONFIG_NAND_SPL
19		-ccflags-y += -DCONFIG_NAND_SPL
20		-
21		-SOBJS = start.o resetvec.o
22		-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
23		- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
24		-
25		-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
26		-__OBJS := $(SOBJS) $(COBJS)
27		-LNDIR := $(nandobj)board/$(BOARDDIR)
28		-
29		-targets += $(__OBJS)
30		-
31		-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
32		-
33		-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
34		- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
35		-
36		-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
37		- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
38		-
39		-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
40		- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
41		- -Map $(nandobj)u-boot-spl.map -o $@
42		-
43		-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
44		- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
45		- -ansi -D__ASSEMBLY__ -P - <$< >$@
46		-
47		-# create symbolic links for common files
48		-
49		-$(obj)/cache.c:
50		- @rm -f $@
51		- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
52		-
53		-$(obj)/cpu_init_early.c:
54		- @rm -f $@
55		- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
56		-
57		-$(obj)/spl_minimal.c:
58		- @rm -f $@
59		- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
60		-
61		-$(obj)/fsl_law.c:
62		- @rm -f $@
63		- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
64		-
65		-$(obj)/law.c:
66		- @rm -f $@
67		- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
68		-
69		-$(obj)/nand_boot_fsl_elbc.c:
70		- @rm -f $@
71		- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
72		-
73		-$(obj)/ns16550.c:
74		- @rm -f $@
75		- ln -sf $(srctree)/drivers/serial/ns16550.c $@
76		-
77		-$(obj)/resetvec.S:
78		- @rm -f $@
79		- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
80		-
81		-$(obj)/start.S:
82		- @rm -f $@
83		- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
84		-
85		-$(obj)/tlb.c:
86		- @rm -f $@
87		- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
88		-
89		-$(obj)/tlb_table.c:
90		- @rm -f $@
91		- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
1		-/*
2		- * Copyright 2009 Freescale Semiconductor, Inc.
3		- *
4		- * SPDX-License-Identifier: GPL-2.0+
5		- */
6		-#include <common.h>
7		-#include <mpc85xx.h>
8		-#include <asm/io.h>
9		-#include <ns16550.h>
10		-#include <nand.h>
11		-#include <asm/mmu.h>
12		-#include <asm/immap_85xx.h>
13		-#include <fsl_ddr_sdram.h>
14		-#include <asm/fsl_law.h>
15		-
16		-#define SYSCLK_MASK 0x00200000
17		-#define BOARDREV_MASK 0x10100000
18		-#define BOARDREV_B 0x10100000
19		-#define BOARDREV_C 0x00100000
20		-
21		-#define SYSCLK_66 66666666
22		-#define SYSCLK_50 50000000
23		-#define SYSCLK_100 100000000
24		-
25		-DECLARE_GLOBAL_DATA_PTR;
26		-
27		-void board_init_f(ulong bootflag)
28		-{
29		- uint plat_ratio, bus_clk, sys_clk = 0;
30		- volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
31		- volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
32		- uint val, temp, sysclk_mask;
33		-
34		- val = pgpio->gpdat;
35		- sysclk_mask = val & SYSCLK_MASK;
36		- temp = val & BOARDREV_MASK;
37		- if (temp == BOARDREV_C) {
38		- if(sysclk_mask == 0)
39		- sys_clk = SYSCLK_66;
40		- else
41		- sys_clk = SYSCLK_100;
42		- } else if (temp == BOARDREV_B) {
43		- if(sysclk_mask == 0)
44		- sys_clk = SYSCLK_66;
45		- else
46		- sys_clk = SYSCLK_50;
47		- }
48		-
49		- plat_ratio = gur->porpllsr & 0x0000003e;
50		- plat_ratio >>= 1;
51		- bus_clk = plat_ratio * sys_clk;
52		- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
53		- bus_clk / 16 / CONFIG_BAUDRATE);
54		-
55		- puts("\nNAND boot... ");
56		-
57		- /* copy code to DDR and jump to it - this should not return */
58		- /* NOTE - code has to be copied out of NAND buffer before
59		- * other blocks can be read.
60		- */
61		- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
62		- CONFIG_SYS_NAND_U_BOOT_RELOC);
63		-}
64		-
65		-void board_init_r(gd_t *gd, ulong dest_addr)
66		-{
67		- nand_boot();
68		-}
69		-
70		-void putc(char c)
71		-{
72		- if (c == '\n')
73		- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
74		-
75		- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
76		-}
77		-
78		-void puts(const char *str)
79		-{
80		- while (*str)
81		- putc(*str++);
82		-}