Eric Lee / smarc-uboot

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Commit bc7380c150269e15f68e9824f8ee03022d62800d

Authored by Ye Li
1 parent 7a60e28035
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-14938-17 pcie: Add support for i.MX8QM/QXP PCIe 

- one lane pcie gen2 link is okay, the cfg space
  of the rc/ep can be accessed.
  rc cfg base 0x5f00_0000. ep cfg base 0x6000_0000
- limit to gen2 speed
- mask the wait of eq3 finish, because it is used
  for gen3.
- use pcie_ctrla_init_rc() to do the initialization
  of the pciea controller
- setup the common pcie codes in pcie_imx8x.c, separate
  the different soc speicifed initialization codes into
  their own pcie/board codes, move the macro definitions
  into the new header file imx8_hsio.h.
- i.MX8QXP only have PCIe Control B. Enable PORT B at default.
  i.MX8QM needs to set CONFIG_IMX_PCIEB to enable PORT B.
- Disable the LTSSM when link is down.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 03141c2b955ce6034f06e701126aea1493dc2b4b)
(cherry picked from commit 99c90ff2de4849aafa0043932353e2c199d22e5f)
(cherry picked from commit ededb7dfeeb765bc64939dc8ba09c826568ff04e)

Showing 5 changed files with 740 additions and 0 deletions Side-by-side Diff

drivers/pci/Makefile
Diff comments   View file @ bc7380c
... ... @@ -22,6 +22,7 @@
22 22 obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
23 23 obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
24 24 obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
  25 +obj-$(CONFIG_PCIE_IMX8X) += pcie_imx8x.o pcie_imx8qm.o
25 26 obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
26 27 obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
27 28 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
drivers/pci/pcie_imx8qm.c
Diff comments   View file @ bc7380c
  1 +/*
  2 + *
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + */
  7 +
  8 +#include <linux/errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/sci/sci.h>
  11 +#include <common.h>
  12 +#include <linux/sizes.h>
  13 +#include <imx8_hsio.h>
  14 +
  15 +void pcie_ctrlx2_rst(void)
  16 +{
  17 + /* gpio config */
  18 + /* dir wakeup input clkreq and pereset output */
  19 + writel(0x2d, HSIO_GPIO_BASE_ADDR + 0x4);
  20 + writel(0x24, HSIO_GPIO_BASE_ADDR + 0x0); /* do pereset 1 */
  21 +
  22 + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_BUTTON_RST_N);
  23 + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_PERST_N);
  24 + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_POWER_UP_RST_N);
  25 + udelay(10);
  26 + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_BUTTON_RST_N);
  27 + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_PERST_N);
  28 + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_POWER_UP_RST_N);
  29 +}
  30 +
  31 +void pcie_ctrlx1_rst(void)
  32 +{
  33 + /* gpio config */
  34 + /* dir wakeup input clkreq and pereset output */
  35 + writel(0x2d, HSIO_GPIO_BASE_ADDR + 0x4);
  36 + writel(0x24, HSIO_GPIO_BASE_ADDR + 0x0); /* do pereset 1 */
  37 +
  38 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N);
  39 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N);
  40 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N);
  41 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N);
  42 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N);
  43 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N);
  44 +}
  45 +
  46 +int pcie_ctrla_init_rc(int lane)
  47 +{
  48 + u32 val, i = 0;
  49 +
  50 + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_APB_RSTN_0
  51 + | HW_PHYX2_CTRL0_APB_RSTN_1); /* APB_RSTN_0/1 */
  52 +
  53 + clrbits_le32(HW_PCIEX2_CTRL0_ADDR, HW_PCIEX2_CTRL0_DEVICE_TYPE_MASK);
  54 + setbits_le32(HW_PCIEX2_CTRL0_ADDR, HW_PCIEX2_CTRL0_DEVICE_TYPE_RC);
  55 +
  56 + if (lane == 1) {
  57 + /*
  58 + * bit 0 rx ena. bit 11 fast_init.
  59 + * bit12 PHY_X1_EPCS_SEL 1.
  60 + * bit13 phy_ab_select 1.
  61 + */
  62 + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA
  63 + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL
  64 + | HW_MISC_CTRL0_PCIE_AB_SELECT);
  65 + /* pipe_ln2lk = 1001 */
  66 + clrbits_le32(HW_PHYX2_CTRL0_ADDR,
  67 + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK);
  68 + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_PIPE_LN2LK_3
  69 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0);
  70 + for (i = 0; i < 100; i++) {
  71 + val = readl(HW_PHYX2_STTS0_ADDR);
  72 + val &= HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK;
  73 + if (val == HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK)
  74 + break;
  75 + udelay(10);
  76 + }
  77 +
  78 + if (val != HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK) {
  79 + printf("TX PLL is not locked.\n");
  80 + return -ENODEV;
  81 + }
  82 + setbits_le32(GPR_LPCG_PHYX2APB_0_APB, BIT(1));
  83 + /* Set the link_capable to be lane1 */
  84 + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_EN_MASK);
  85 + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_LANE1);
  86 + clrbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_MASK);
  87 + setbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_1);
  88 + } else if (lane == 2) {
  89 + /*
  90 + * bit 0 rx ena. bit 11 fast_init.
  91 + * bit12 PHY_X1_EPCS_SEL 1.
  92 + */
  93 + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA
  94 + | HW_MISC_CTRL0_PHY_X1_EPCS_SEL);
  95 + /* pipe_ln2lk = 0011 */
  96 + clrbits_le32(HW_PHYX2_CTRL0_ADDR,
  97 + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK);
  98 + setbits_le32(HW_PHYX2_CTRL0_ADDR, HW_PHYX2_CTRL0_PIPE_LN2LK_1
  99 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0);
  100 + for (i = 0; i < 100; i++) {
  101 + val = readl(HW_PHYX2_STTS0_ADDR);
  102 + val &= (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK);
  103 + if (val == (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK))
  104 + break;
  105 + udelay(10);
  106 + }
  107 +
  108 + if (val != (HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK | HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK)) {
  109 + printf("TX PLL is not locked.\n");
  110 + return -ENODEV;
  111 + }
  112 + setbits_le32(GPR_LPCG_PHYX2APB_0_APB, BIT(1) + BIT(5));
  113 + /* Set the link_capable to be lane2 */
  114 + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_EN_MASK);
  115 + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_LANE2);
  116 + clrbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_MASK);
  117 + setbits_le32(PORT0_GEN2_CTRL, PORT_GEN2_CTRL_NUM_LANES_2);
  118 + } else {
  119 + printf("%s %d lane %d is invalid.\n", __func__, __LINE__, lane);
  120 + }
  121 +
  122 + /* bit19 PM_REQ_CORE_RST of pciex2_stts0 should be cleared. */
  123 + for (i = 0; i < 100; i++) {
  124 + val = readl(HW_PCIEX2_STTS0_ADDR);
  125 + if ((val & HW_PCIEX2_STTS0_PM_REQ_CORE_RST) == 0)
  126 + break;
  127 + udelay(10);
  128 + }
  129 +
  130 + if ((val & HW_PCIEX2_STTS0_PM_REQ_CORE_RST) != 0)
  131 + printf("ERROR PM_REQ_CORE_RST is set.\n");
  132 +
  133 + /* DBI_RO_WR_EN =1 to write PF0_SPCIE_CAP_OFF_0CH_REG */
  134 + writel(0x1, PORT0_MISC_CONTROL_1);
  135 + writel(0x35353535, PF0_SPCIE_CAP_OFF_0CH_REG); /* set preset not golden */
  136 + setbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK);
  137 + setbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE);
  138 +
  139 + do {
  140 + udelay(100);
  141 + val = readl(PORT0_LINK_DEBUG1);
  142 + } while (((val & PORT_LINK_DEBUG1_LINK_UP) == 0) && (i++ < 100));
  143 +
  144 + if ((val & PORT_LINK_DEBUG1_LINK_UP) == PORT_LINK_DEBUG1_LINK_UP)
  145 + printf("[%s] LNK UP %x\r\n", __func__, val);
  146 + else {
  147 + printf("[%s] LNK DOWN %x\r\n", __func__, val);
  148 + clrbits_le32(HW_PCIEX2_CTRL2_ADDR, HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE);
  149 + return -ENODEV;
  150 + }
  151 +
  152 + clrbits_le32(PORT0_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK);
  153 +
  154 + val = readl(PF0_LINK_CONTROL_LINK_STATUS_REG);
  155 + printf("[%s] PCIe GEN[%d] Lane[%d] is up.\n", __func__,
  156 + (val >> 16) & 0xF, (val >> 20) & 0x3F);
  157 +
  158 + /* EQ phase 3 finish
  159 + * wait_read_check(LINK_CONTROL2_LINK_STATUS2_REG,BIT(17),BIT(17),1000);
  160 + */
  161 + /* make sure that pciea is L0 state now */
  162 + for (i = 0; i < 100; i++) {
  163 + val = readl(HW_PCIEX2_STTS0_ADDR);
  164 + if ((val & 0x3f) == 0x11)
  165 + break;
  166 + udelay(10);
  167 + }
  168 +
  169 + if ((val & 0x3f) != 0x11)
  170 + printf("can't return back to L0 state.\n");
  171 +
  172 + writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
  173 + PF0_TYPE1_STATUS_COMMAND_REG);
  174 + printf("pcie ctrla initialization is finished.\n");
  175 +
  176 + return 0;
  177 +}
  178 +
  179 +int pcie_ctrlb_sata_phy_init_rc(void)
  180 +{
  181 + u32 val, i = 0;
  182 +
  183 + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_APB_RSTN); /* APB_RSTN */
  184 +
  185 + clrbits_le32(HW_PCIEX1_CTRL0_ADDR, HW_PCIEX1_CTRL0_DEVICE_TYPE_MASK);
  186 + setbits_le32(HW_PCIEX1_CTRL0_ADDR, HW_PCIEX1_CTRL0_DEVICE_TYPE_RC);
  187 +
  188 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_BUTTON_RST_N);
  189 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N);
  190 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_PERST_N);
  191 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N);
  192 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_POWER_UP_RST_N);
  193 +
  194 + /*
  195 + * bit 0 rx ena. bit 11 fast_init.
  196 + * bit13 phy_ab_select 1.
  197 + */
  198 + setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA);
  199 + clrbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_PHY_X1_EPCS_SEL);
  200 +
  201 + /* pipe_ln2lk = 0011 */
  202 + clrbits_le32(HW_PHYX1_CTRL0_ADDR,
  203 + HW_PHYX1_CTRL0_PIPE_LN2LK_MASK);
  204 + setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_PIPE_LN2LK_1
  205 + | HW_PHYX2_CTRL0_PIPE_LN2LK_0);
  206 + for (i = 0; i < 100; i++) {
  207 + val = readl(HW_PHYX1_STTS0_ADDR);
  208 + val &= HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK;
  209 + if (val == HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK)
  210 + break;
  211 + udelay(10);
  212 + }
  213 +
  214 + if (val != HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) {
  215 + printf("TX PLL is not locked.\n");
  216 + return -ENODEV;
  217 + }
  218 +
  219 + setbits_le32(GPR_LPCG_PHYX1_APB, BIT(1));
  220 +
  221 + /* bit19 PM_REQ_CORE_RST of pciex1_stts0 should be cleared. */
  222 + for (i = 0; i < 100; i++) {
  223 + val = readl(HW_PCIEX1_STTS0_ADDR);
  224 + if ((val & HW_PCIEX1_STTS0_PM_REQ_CORE_RST) == 0)
  225 + break;
  226 + udelay(10);
  227 + }
  228 +
  229 + if ((val & HW_PCIEX1_STTS0_PM_REQ_CORE_RST) != 0)
  230 + printf("ERROR PM_REQ_CORE_RST is set.\n");
  231 +
  232 + /* DBI_RO_WR_EN =1 to write PF1_SPCIE_CAP_OFF_0CH_REG */
  233 + writel(0x1, PORT1_MISC_CONTROL_1);
  234 + writel(0x35353535, PF1_SPCIE_CAP_OFF_0CH_REG); /* set preset not golden */
  235 + setbits_le32(PORT1_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK);
  236 + setbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE);
  237 +
  238 + do {
  239 + udelay(100);
  240 + val = readl(PORT1_LINK_DEBUG1);
  241 + } while (((val & PORT_LINK_DEBUG1_LINK_UP) == 0) && (i++ < 100));
  242 +
  243 + if ((val & PORT_LINK_DEBUG1_LINK_UP) == PORT_LINK_DEBUG1_LINK_UP) {
  244 + printf("[%s] LNK UP %x\r\n", __func__, val);
  245 + } else {
  246 + printf("[%s] LNK DOWN %x\r\n", __func__, val);
  247 + clrbits_le32(HW_PCIEX1_CTRL2_ADDR, HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE);
  248 + return -ENODEV;
  249 + }
  250 + clrbits_le32(PORT1_LINK_CTRL, PORT_LINK_CTRL_LNK_FAST_LNK);
  251 +
  252 + val = readl(PF1_LINK_CONTROL_LINK_STATUS_REG);
  253 + printf("[%s] PCIe GEN[%d] Lane[%d] is up.\n", __func__,
  254 + (val >> 16) & 0xF, (val >> 20) & 0x3F);
  255 +
  256 + /* EQ phase 3 finish
  257 + * wait_read_check(LINK_CONTROL2_LINK_STATUS2_REG,BIT(17),BIT(17),1000);
  258 + */
  259 + /* make sure that pcieb is L0 state now */
  260 + for (i = 0; i < 100; i++) {
  261 + val = readl(HW_PCIEX1_STTS0_ADDR);
  262 + if ((val & 0x3f) == 0x11)
  263 + break;
  264 + udelay(10);
  265 + }
  266 +
  267 + if ((val & 0x3f) != 0x11) {
  268 + printf("can't return back to L0 state.\n");
  269 + return -ENODEV;
  270 + }
  271 +
  272 + writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
  273 + PF1_TYPE1_STATUS_COMMAND_REG);
  274 +
  275 + return 0;
  276 +}
  277 +
  278 +DECLARE_GLOBAL_DATA_PTR;
  279 +void mx8qxp_pcie_init(void)
  280 +{
  281 + pcie_ctrlx1_rst();
  282 + if (!pcie_ctrlb_sata_phy_init_rc())
  283 + mx8x_pcie_ctrlb_setup_regions();
  284 +}
  285 +
  286 +void mx8qm_pcie_init(void)
  287 +{
  288 + pcie_ctrlx2_rst();
  289 + if (!pcie_ctrla_init_rc(1))
  290 + mx8x_pcie_ctrla_setup_regions();
  291 +
  292 +#ifdef CONFIG_IMX_PCIEB
  293 + pcie_ctrlx1_rst();
  294 + if (!pcie_ctrlb_sata_phy_init_rc())
  295 + mx8x_pcie_ctrlb_setup_regions();
  296 +#endif
  297 +}
drivers/pci/pcie_imx8x.c
Diff comments   View file @ bc7380c
  1 +/*
  2 + *
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <pci.h>
  10 +#include <asm/gpio.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/sci/sci.h>
  13 +#include <linux/sizes.h>
  14 +#include <errno.h>
  15 +#include <imx8_hsio.h>
  16 +
  17 +void mx8x_pcie_controller_reset(sc_ipc_t ipc, u32 scr)
  18 +{
  19 + sc_err_t err;
  20 + int i;
  21 +
  22 + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_G_RST, 1);
  23 + if (err != SC_ERR_NONE)
  24 + printf("SC_R_PCIE G_RST failed! (error = %d)\n", err);
  25 + for (i = 0; i < 200; i = i + 1)
  26 + asm("nop");
  27 +
  28 + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_G_RST, 0);
  29 + if (err != SC_ERR_NONE)
  30 + printf("SC_R_PCIE G_RST failed! (error = %d)\n", err);
  31 +
  32 + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_PERST, 1);
  33 + if (err != SC_ERR_NONE)
  34 + printf("SC_R_PCIE PCIE_RST failed! (error = %d)\n", err);
  35 +
  36 + err = sc_misc_set_control(ipc, scr, SC_C_PCIE_BUTTON_RST, 1);
  37 + if (err != SC_ERR_NONE)
  38 + printf("SC_R_PCIE BUTTON_RST failed! (error = %d)\n", err);
  39 +}
  40 +
  41 +static void pcie_mapping_region(u32 index, u32 direction, u32 type,
  42 + u32 addr, u32 size, u32 target_l, u32 target_h)
  43 +{
  44 + /* Select a iATU and configure its direction */
  45 + pcie_writel(index | direction, PCIE0_ATU_VIEWPORT);
  46 + setbits_le32(PCIE0_ATU_CR1, type);
  47 +
  48 + /* Set memory address and size */
  49 + pcie_writel(addr, PCIE0_ATU_LOWER_BASE);
  50 + pcie_writel(0, PCIE0_ATU_UPPER_BASE);
  51 + pcie_writel((addr + size - 1), PCIE0_ATU_LIMIT);
  52 +
  53 + pcie_writel(target_l, PCIE0_ATU_LOWER_TARGET);
  54 + pcie_writel(target_h, PCIE0_ATU_UPPER_TARGET);
  55 +
  56 + /* Enable this iATU */
  57 + setbits_le32(PCIE0_ATU_CR2, PCIE_ATU_ENABLE);
  58 +}
  59 +
  60 +static void pcie_ctrlb_mapping_region(u32 index, u32 direction, u32 type,
  61 + u32 addr, u32 size, u32 target_l, u32 target_h)
  62 +{
  63 + /* Select a iATU and configure its direction */
  64 + pcie_writel(index | direction, PCIE1_ATU_VIEWPORT);
  65 + setbits_le32(PCIE1_ATU_CR1, type);
  66 +
  67 + /* Set memory address and size */
  68 + pcie_writel(addr, PCIE1_ATU_LOWER_BASE);
  69 + pcie_writel(0, PCIE1_ATU_UPPER_BASE);
  70 + pcie_writel((addr + size - 1), PCIE1_ATU_LIMIT);
  71 +
  72 + pcie_writel(target_l, PCIE1_ATU_LOWER_TARGET);
  73 + pcie_writel(target_h, PCIE1_ATU_UPPER_TARGET);
  74 +
  75 + /* Enable this iATU */
  76 + setbits_le32(PCIE1_ATU_CR2, PCIE_ATU_ENABLE);
  77 +}
  78 +
  79 +/* CFG Space --> 0x40000000
  80 + * 1st Region --> 0x41000000
  81 + * 2nd Region --> 0x42000000
  82 + * ...
  83 + */
  84 +void mx8x_pcie_ctrla_setup_regions(void)
  85 +{
  86 + u32 i, cmd;
  87 + u32 val, index;
  88 + u32 is_32bit;
  89 + u32 type, size;
  90 + u64 size64;
  91 + const u32 region_types[] = {
  92 + PCIE_ATU_TYPE_MEM,
  93 + PCIE_ATU_TYPE_IO,
  94 + };
  95 +
  96 + cmd = PCI_COMMAND_MASTER;
  97 +
  98 + pcie_mapping_region(0, PCIE_ATU_REGION_OUTBOUND, PCIE_ATU_TYPE_CFG0,
  99 + PCIEA_CFG_PCI_BASE, PCIE_CFG_MEM_SIZE, 0, 0);
  100 +
  101 + index = 1;
  102 + udelay(1000);
  103 +
  104 + for (i = 0; i < 6; i++) {
  105 + val = pcie_readl(PCIEA_CFG_CPU_BASE + 0x10 + i * 4);
  106 + printf("#### [%d] val=%X addr=%X\r\n ", i, val,
  107 + PCIEA_CFG_CPU_BASE + 0x10 + i * 4);
  108 + if (!val)
  109 + continue;
  110 + type = region_types[val & 0x1];
  111 + is_32bit = ((val & 0x4) == 0);
  112 + pcie_writel(0xFFFFFFFF, PCIEA_CFG_CPU_BASE + 0x10 + i * 4);
  113 + size = pcie_readl(PCIEA_CFG_CPU_BASE + 0x10 + i * 4);
  114 + size = 0xFFFFFFFF - (size & ~0xF) + 1;
  115 + if (is_32bit) {
  116 + pcie_mapping_region(index, PCIE_ATU_REGION_OUTBOUND,
  117 + type, PCIEA_CFG_PCI_BASE
  118 + + index * 0x1000000, size,
  119 + index * 0x1000000, 0);
  120 + val = (val & 0xF) + index * 0x1000000;
  121 + pcie_writel(val, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4));
  122 + } else {
  123 + pcie_writel(0xFFFFFFFF, (PCIEA_CFG_CPU_BASE + 0x10
  124 + + i * 4 + 4));
  125 + size64 = pcie_readl(PCIEA_CFG_CPU_BASE
  126 + + 0x10 + i * 4 + 4);
  127 + size64 = 0xFFFFFFFF - size64;
  128 + size64 <<= 32;
  129 + size64 |= size;
  130 + size64++;
  131 + pcie_mapping_region(index, PCIE_ATU_REGION_OUTBOUND,
  132 + type, PCIEA_CFG_PCI_BASE
  133 + + index * 0x1000000, size64,
  134 + index * 0x1000000, 0);
  135 + val = (val & 0xF) + index * 0x1000000;
  136 + pcie_writel(val, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4));
  137 + pcie_writel(0, (PCIEA_CFG_CPU_BASE + 0x10 + i * 4 + 4));
  138 + i++;
  139 + }
  140 +
  141 + index++;
  142 +
  143 + if (type == PCIE_ATU_TYPE_MEM)
  144 + cmd |= PCI_COMMAND_MEMORY;
  145 + else
  146 + cmd |= PCI_COMMAND_IO;
  147 + }
  148 +
  149 + pcie_writel(cmd, PCIEA_CFG_CPU_BASE + 4);
  150 +}
  151 +
  152 +/* CFG Space --> 0x80000000
  153 + * 1st Region --> 0x81000000
  154 + * 2nd Region --> 0x82000000
  155 + * ...
  156 + */
  157 +void mx8x_pcie_ctrlb_setup_regions(void)
  158 +{
  159 + u32 i, cmd;
  160 + u32 val, index;
  161 + u32 is_32bit;
  162 + u32 type, size;
  163 + u64 size64;
  164 + const u32 region_types[] = {
  165 + PCIE_ATU_TYPE_MEM,
  166 + PCIE_ATU_TYPE_IO,
  167 + };
  168 +
  169 + cmd = PCI_COMMAND_MASTER;
  170 +
  171 + pcie_ctrlb_mapping_region(0, PCIE_ATU_REGION_OUTBOUND, PCIE_ATU_TYPE_CFG0,
  172 + PCIEB_CFG_PCI_BASE, PCIE_CFG_MEM_SIZE, 0, 0);
  173 +
  174 + index = 1;
  175 + udelay(1000);
  176 +
  177 + for (i = 0; i < 6; i++) {
  178 + val = pcie_readl(PCIEB_CFG_CPU_BASE + 0x10 + i * 4);
  179 + printf("#### [%d] val=%X addr=%X\r\n ", i, val,
  180 + PCIEB_CFG_CPU_BASE + 0x10 + i * 4);
  181 + if (!val)
  182 + continue;
  183 + type = region_types[val & 0x1];
  184 + is_32bit = ((val & 0x4) == 0);
  185 + pcie_writel(0xFFFFFFFF, PCIEB_CFG_CPU_BASE + 0x10 + i * 4);
  186 + size = pcie_readl(PCIEB_CFG_CPU_BASE + 0x10 + i * 4);
  187 + size = 0xFFFFFFFF - (size & ~0xF) + 1;
  188 + if (is_32bit) {
  189 + pcie_ctrlb_mapping_region(index, PCIE_ATU_REGION_OUTBOUND,
  190 + type, PCIEB_CFG_PCI_BASE
  191 + + index * 0x1000000, size,
  192 + index * 0x1000000, 0);
  193 + val = (val & 0xF) + index * 0x1000000;
  194 + pcie_writel(val, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4));
  195 + } else {
  196 + pcie_writel(0xFFFFFFFF, (PCIEB_CFG_CPU_BASE + 0x10
  197 + + i * 4 + 4));
  198 + size64 = pcie_readl(PCIEB_CFG_CPU_BASE
  199 + + 0x10 + i * 4 + 4);
  200 + size64 = 0xFFFFFFFF - size64;
  201 + size64 <<= 32;
  202 + size64 |= size;
  203 + size64++;
  204 + pcie_ctrlb_mapping_region(index, PCIE_ATU_REGION_OUTBOUND,
  205 + type, PCIEB_CFG_PCI_BASE
  206 + + index * 0x1000000, size64,
  207 + index * 0x1000000, 0);
  208 + val = (val & 0xF) + index * 0x1000000;
  209 + pcie_writel(val, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4));
  210 + pcie_writel(0, (PCIEB_CFG_CPU_BASE + 0x10 + i * 4 + 4));
  211 + i++;
  212 + }
  213 +
  214 + index++;
  215 +
  216 + if (type == PCIE_ATU_TYPE_MEM)
  217 + cmd |= PCI_COMMAND_MEMORY;
  218 + else
  219 + cmd |= PCI_COMMAND_IO;
  220 + }
  221 +
  222 + pcie_writel(cmd, PCIEB_CFG_CPU_BASE + 4);
  223 +}
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
  3 + */
  4 +/*
  5 + * The code contained herein is licensed under the GNU General Public
  6 + * License. You may obtain a copy of the GNU General Public License
  7 + * Version 2 or later at the following locations:
  8 + *
  9 + * http://www.opensource.org/licenses/gpl-license.html
  10 + * http://www.gnu.org/copyleft/gpl.html
  11 + */
  12 +
  13 +#ifndef _IMX8_HSIO_H_
  14 +#define _IMX8_HSIO_H_
  15 +
  16 +#define PCIEA_CFG_CPU_BASE 0x60000000
  17 +#define PCIEA_CFG_PCI_BASE 0x40000000
  18 +#define PCIEB_CFG_CPU_BASE 0x70000000
  19 +#define PCIEB_CFG_PCI_BASE 0x80000000
  20 +#define PCIE_CFG_MEM_SIZE 0x4000
  21 +
  22 +#define PCIE_DBI_BASE_ADDR 0x5f000000
  23 +#define PCIE_CTRLA_BASE_ADDR PCIE_DBI_BASE_ADDR
  24 +#define PCIE_CTRLB_BASE_ADDR (PCIE_DBI_BASE_ADDR + 0x10000)
  25 +
  26 +/* For 8DV */
  27 +#define DEVICE_TYPE_RC BIT(14)
  28 +#define REFCLK_SEL BIT(4)
  29 +#define CMN_REG_RST BIT(3)
  30 +
  31 +#define HSIO_BASE_ADDR 0x5F070000
  32 +#define HSIO_GPR_PCIE_CTRL0_ADDR (HSIO_BASE_ADDR + 0x00000000)
  33 +#define HSIO_GPR_PCIE_CTRL1_ADDR (HSIO_BASE_ADDR + 0x00000004)
  34 +#define HSIO_GPR_PCIE_STATUS0_ADDR (HSIO_BASE_ADDR + 0x00000008)
  35 +
  36 +/* For 8QM */
  37 +#define AHCI_BASE_ADDR 0x5F020000
  38 +#define HW_SATA_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00040000)
  39 +#define HW_SATA_CTRL0_ADDR_MASK 0x000017fb
  40 +#define HW_SATA_CTRL0_ADDR_RESET 0x0
  41 +#define HW_SATA_CTRL0_PHY_FOMREQ BIT(0)
  42 +#define HW_SATA_CTRL0_PHY_PMA_DRVN BIT(1)
  43 +#define HW_SATA_CTRL0_EPCS_SKIPBIT BIT(3)
  44 +#define HW_SATA_CTRL0_EPCS_RXERR BIT(4)
  45 +#define HW_SATA_CTRL0_EPCS_TXDEEMP BIT(5)
  46 +#define HW_SATA_CTRL0_EPCS_TXDEEMP_SEL BIT(6)
  47 +#define HW_SATA_CTRL0_PHY_RESET BIT(7)
  48 +#define HW_SATA_CTRL0_EPCS_PHYRESET_SEL BIT(8)
  49 +#define HW_SATA_CTRL0_EPCS_RXOOB BIT(9)
  50 +#define HW_SATA_CTRL0_EPCS_RXOOB_SEL BIT(10)
  51 +#define HW_SATA_CTRL0_RESET BIT(12)
  52 +
  53 +#define HSIO_LPCG_BASE_ADDR 0x5F050000
  54 +#define HSIO_GPIO_BASE_ADDR 0x5F170000
  55 +
  56 +#define GPR_LPCG_PCIEA_CTRL_MSTR_ACLK (HSIO_LPCG_BASE_ADDR + 0x00000000)
  57 +#define GPR_LPCG_PCIEB_CTRL_MSTR_ACLK (HSIO_LPCG_BASE_ADDR + 0x00010000)
  58 +#define GPR_LPCG_PHYX2APB_0_APB (HSIO_LPCG_BASE_ADDR + 0x00030000)
  59 +#define GPR_LPCG_PHYX1_APB (HSIO_LPCG_BASE_ADDR + 0x00040000)
  60 +#define GPR_LPCG_CRR_0 (HSIO_LPCG_BASE_ADDR + 0x00050000)
  61 +#define GPR_LPCG_CRR_1 (HSIO_LPCG_BASE_ADDR + 0x00060000)
  62 +#define GPR_LPCG_CRR_2 (HSIO_LPCG_BASE_ADDR + 0x00070000)
  63 +#define GPR_LPCG_CRR_3 (HSIO_LPCG_BASE_ADDR + 0x00080000)
  64 +#define GPR_LPCG_CRR_4 (HSIO_LPCG_BASE_ADDR + 0x00090000)
  65 +#define GPR_LPCG_CRR_5 (HSIO_LPCG_BASE_ADDR + 0x000a0000)
  66 +#define GPR_LPCG_GPIO (HSIO_LPCG_BASE_ADDR + 0x000b0000)
  67 +
  68 +#define HSIO_CRR_BASE_ADDR 0x5F110000
  69 +
  70 +#define HW_PHYX2_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00000000)
  71 +#define HW_PHYX2_CTRL0_APB_RSTN_0 BIT(0)
  72 +#define HW_PHYX2_CTRL0_APB_RSTN_1 BIT(1)
  73 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_MASK (0xF << 13)
  74 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_0 BIT(13)
  75 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_1 BIT(14)
  76 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_2 BIT(15)
  77 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_3 BIT(16)
  78 +
  79 +#define HW_PHYX2_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x00000004)
  80 +#define HW_PHYX2_STTS0_LANE0_TX_PLL_LOCK BIT(4)
  81 +#define HW_PHYX2_STTS0_LANE1_TX_PLL_LOCK BIT(12)
  82 +
  83 +#define HW_PHYX1_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00010000)
  84 +#define HW_PHYX1_CTRL0_APB_RSTN BIT(0)
  85 +#define HW_PHYX1_CTRL0_PIPE_LN2LK_MASK (0xF << 13)
  86 +#define HW_PHYX1_CTRL0_PIPE_LN2LK_0 BIT(13)
  87 +#define HW_PHYX1_CTRL0_PIPE_LN2LK_1 BIT(14)
  88 +#define HW_PHYX1_CTRL0_PIPE_LN2LK_2 BIT(15)
  89 +#define HW_PHYX1_CTRL0_PIPE_LN2LK_3 BIT(16)
  90 +
  91 +#define HW_PHYX1_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x00010004)
  92 +#define HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK BIT(4)
  93 +#define HW_PHYX1_STTS0_LANE0_RX_PLL_LOCK BIT(5)
  94 +
  95 +#define HW_MISC_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00050000)
  96 +#define HW_MISC_CTRL0_IOB_RXENA BIT(0)
  97 +#define HW_MISC_CTRL0_IOB_TXENA BIT(1)
  98 +#define HW_MISC_CTRL0_FAST_INIT BIT(11)
  99 +#define HW_MISC_CTRL0_PHY_X1_EPCS_SEL BIT(12)
  100 +#define HW_MISC_CTRL0_PCIE_AB_SELECT BIT(13)
  101 +
  102 +#define HW_PCIEX2_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00020000)
  103 +#define HW_PCIEX2_CTRL0_DEVICE_TYPE_MASK (0xF << 24)
  104 +#define HW_PCIEX2_CTRL0_DEVICE_TYPE_RC BIT(26)
  105 +
  106 +#define HW_PCIEX2_CTRL2_ADDR (HSIO_CRR_BASE_ADDR + 0x00020008)
  107 +#define HW_PCIEX2_CTRL2_APP_LTSSM_ENABLE BIT(4)
  108 +#define HW_PCIEX2_CTRL2_BUTTON_RST_N BIT(21)
  109 +#define HW_PCIEX2_CTRL2_PERST_N BIT(22)
  110 +#define HW_PCIEX2_CTRL2_POWER_UP_RST_N BIT(23)
  111 +
  112 +#define HW_PCIEX2_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x0002000C)
  113 +#define HW_PCIEX2_STTS0_PM_REQ_CORE_RST BIT(19)
  114 +
  115 +#define HW_PCIEX1_CTRL0_ADDR (HSIO_CRR_BASE_ADDR + 0x00030000)
  116 +#define HW_PCIEX1_CTRL0_DEVICE_TYPE_MASK (0xF << 24)
  117 +#define HW_PCIEX1_CTRL0_DEVICE_TYPE_RC BIT(26)
  118 +
  119 +#define HW_PCIEX1_CTRL2_ADDR (HSIO_CRR_BASE_ADDR + 0x00030008)
  120 +#define HW_PCIEX1_CTRL2_APP_LTSSM_ENABLE BIT(4)
  121 +#define HW_PCIEX1_CTRL2_BUTTON_RST_N BIT(21)
  122 +#define HW_PCIEX1_CTRL2_PERST_N BIT(22)
  123 +#define HW_PCIEX1_CTRL2_POWER_UP_RST_N BIT(23)
  124 +
  125 +#define HW_PCIEX1_STTS0_ADDR (HSIO_CRR_BASE_ADDR + 0x0003000c)
  126 +#define HW_PCIEX1_STTS0_PM_REQ_CORE_RST BIT(19)
  127 +
  128 +/* PCIe Port Logic registers (memory-mapped) */
  129 +#define PF0_PORT_LOGIC (PCIE_CTRLA_BASE_ADDR + 0x700)
  130 +#define PF1_PORT_LOGIC (PCIE_CTRLB_BASE_ADDR + 0x700)
  131 +
  132 +#define PORT0_LINK_CTRL (PF0_PORT_LOGIC + 0x10)
  133 +#define PORT1_LINK_CTRL (PF1_PORT_LOGIC + 0x10)
  134 +#define PORT_LINK_CTRL_LNK_EN_MASK (0x3F << 16)
  135 +#define PORT_LINK_CTRL_LNK_LANE1 (0x1 << 16)
  136 +#define PORT_LINK_CTRL_LNK_LANE2 (0x3 << 16)
  137 +#define PORT_LINK_CTRL_LNK_FAST_LNK BIT(7)
  138 +
  139 +#define PORT0_LINK_DEBUG1 (PF0_PORT_LOGIC + 0x2C)
  140 +#define PORT1_LINK_DEBUG1 (PF1_PORT_LOGIC + 0x2C)
  141 +#define PORT_LINK_DEBUG1_LINK_UP BIT(4)
  142 +
  143 +#define PORT0_GEN2_CTRL (PF0_PORT_LOGIC + 0x10C)
  144 +#define PORT1_GEN2_CTRL (PF1_PORT_LOGIC + 0x10C)
  145 +#define PORT_GEN2_CTRL_NUM_LANES_MASK (0xFF << 8)
  146 +#define PORT_GEN2_CTRL_NUM_LANES_1 (0x1 << 8)
  147 +#define PORT_GEN2_CTRL_NUM_LANES_2 (0x2 << 8)
  148 +
  149 +#define PORT0_MISC_CONTROL_1 (PF0_PORT_LOGIC + 0x1BC)
  150 +#define PORT1_MISC_CONTROL_1 (PF1_PORT_LOGIC + 0x1BC)
  151 +
  152 +#define PORT0_DBI_LNK_STS_CTRL2 (PCIE_CTRLA_BASE_ADDR + 0xA0)
  153 +
  154 +#define PF0_TYPE1_HDR (PCIE_CTRLA_BASE_ADDR + 0x0)
  155 +#define PF0_TYPE1_STATUS_COMMAND_REG (PF0_TYPE1_HDR + 0x4)
  156 +#define PF1_TYPE1_HDR (PCIE_CTRLB_BASE_ADDR + 0x0)
  157 +#define PF1_TYPE1_STATUS_COMMAND_REG (PF1_TYPE1_HDR + 0x4)
  158 +
  159 +#define PF0_PCIE_CAP (PCIE_CTRLA_BASE_ADDR + 0x70)
  160 +#define PF0_LINK_CONTROL_LINK_STATUS_REG (PF0_PCIE_CAP + 0x10)
  161 +#define PF1_PCIE_CAP (PCIE_CTRLB_BASE_ADDR + 0x70)
  162 +#define PF1_LINK_CONTROL_LINK_STATUS_REG (PF1_PCIE_CAP + 0x10)
  163 +
  164 +#define PF0_SPICE_CAP (PCIE_CTRLA_BASE_ADDR + 0x148)
  165 +#define PF0_SPCIE_CAP_OFF_0CH_REG (PF0_SPICE_CAP + 0xC)
  166 +#define PF1_SPICE_CAP (PCIE_CTRLB_BASE_ADDR + 0x148)
  167 +#define PF1_SPCIE_CAP_OFF_0CH_REG (PF1_SPICE_CAP + 0xC)
  168 +
  169 +/* iATU registers */
  170 +#define PCIE0_ATU_VIEWPORT (PCIE_CTRLA_BASE_ADDR + 0x900)
  171 +#define PCIE1_ATU_VIEWPORT (PCIE_CTRLB_BASE_ADDR + 0x900)
  172 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  173 +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  174 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  175 +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  176 +#define PCIE0_ATU_CR1 (PCIE_CTRLA_BASE_ADDR + 0x904)
  177 +#define PCIE1_ATU_CR1 (PCIE_CTRLB_BASE_ADDR + 0x904)
  178 +#define PCIE_ATU_TYPE_MEM (0x0 << 0)
  179 +#define PCIE_ATU_TYPE_IO (0x2 << 0)
  180 +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  181 +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  182 +#define PCIE0_ATU_CR2 (PCIE_CTRLA_BASE_ADDR + 0x908)
  183 +#define PCIE1_ATU_CR2 (PCIE_CTRLB_BASE_ADDR + 0x908)
  184 +#define PCIE_ATU_ENABLE (0x1 << 31)
  185 +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  186 +#define PCIE0_ATU_LOWER_BASE (PCIE_CTRLA_BASE_ADDR + 0x90C)
  187 +#define PCIE0_ATU_UPPER_BASE (PCIE_CTRLA_BASE_ADDR + 0x910)
  188 +#define PCIE0_ATU_LIMIT (PCIE_CTRLA_BASE_ADDR + 0x914)
  189 +#define PCIE0_ATU_LOWER_TARGET (PCIE_CTRLA_BASE_ADDR + 0x918)
  190 +#define PCIE0_ATU_UPPER_TARGET (PCIE_CTRLA_BASE_ADDR + 0x91C)
  191 +#define PCIE1_ATU_LOWER_BASE (PCIE_CTRLB_BASE_ADDR + 0x90C)
  192 +#define PCIE1_ATU_UPPER_BASE (PCIE_CTRLB_BASE_ADDR + 0x910)
  193 +#define PCIE1_ATU_LIMIT (PCIE_CTRLB_BASE_ADDR + 0x914)
  194 +#define PCIE1_ATU_LOWER_TARGET (PCIE_CTRLB_BASE_ADDR + 0x918)
  195 +#define PCIE1_ATU_UPPER_TARGET (PCIE_CTRLB_BASE_ADDR + 0x91C)
  196 +
  197 +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
  198 +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
  199 +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
  200 +
  201 +#define pcie_readl(x) readl((unsigned long)x)
  202 +#define pcie_writel(v, c) writel(v, (unsigned long)c)
  203 +#define pcie_clrbits_le32(addr, clear) clrbits_le32((unsigned long)addr, clear)
  204 +
  205 +void mx8x_pcie_controller_reset(sc_ipc_t ipc, u32 SC_R_PCIE);
  206 +void mx8x_pcie_ctrla_setup_regions(void);
  207 +void mx8x_pcie_ctrlb_setup_regions(void);
  208 +
  209 +void mx8dv_pcie_init(void);
  210 +void mx8qm_pcie_init(void);
  211 +void mx8qxp_pcie_init(void);
  212 +
  213 +int sata_init(void);
  214 +
  215 +#endif /* _IMX8_HSIO_H_ */
scripts/config_whitelist.txt
Diff comments   View file @ bc7380c
... ... @@ -568,6 +568,7 @@
568 568 CONFIG_FSL_ESDHC_PIN_MUX
569 569 CONFIG_FSL_FIXED_MMC_LOCATION
570 570 CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  571 +CONFIG_FSL_HSIO
571 572 CONFIG_FSL_I2C_CUSTOM_DFSR
572 573 CONFIG_FSL_I2C_CUSTOM_FDR
573 574 CONFIG_FSL_IIM
... ... @@ -860,6 +861,7 @@
860 861 CONFIG_IMX_HDMI
861 862 CONFIG_IMX_NAND
862 863 CONFIG_IMX_OTP
  864 +CONFIG_IMX_PCIEB
863 865 CONFIG_IMX_VIDEO_SKIP
864 866 CONFIG_INETSPACE_V2
865 867 CONFIG_INITRD_TAG
... ... @@ -1261,6 +1263,7 @@
1261 1263 CONFIG_PCIE3
1262 1264 CONFIG_PCIE4
1263 1265 CONFIG_PCIE_IMX
  1266 +CONFIG_PCIE_IMX8X
1264 1267 CONFIG_PCIE_IMX_PERST_GPIO
1265 1268 CONFIG_PCIE_IMX_POWER_GPIO
1266 1269 CONFIG_PCISLAVE