Eric Lee / smarc-uboot

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Commit bce752cfe43b3378dbd84b64d46f1d1818e0300f

Authored by Peng Fan
Committed by Ye Li
1 parent fa8e4ac67e
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18243-14 spi: fspi: init unused LUT to 0 

If not initialize unused LUT to 0, the value is random which might
cause qspi command failure.

On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on
i.MX8MM, ROM not initialize them, so let's do it here.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318)

Showing 1 changed file with 26 additions and 1 deletions Side-by-side Diff

drivers/spi/fsl_fspi.c
Diff comments   View file @ bce752c
1 1 /*
2   - * Copyright 2017 NXP
  2 + * Copyright 2017-2018 NXP
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
... ... @@ -191,6 +191,8 @@
191 191 fspi_write32(priv->flags, &regs->lut[lut_base + 1],
192 192 OPRND0(0) | PAD0(LUT_PAD1) |
193 193 INSTR0(LUT_READ));
  194 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  195 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
194 196  
195 197 /* Write Enable */
196 198 lut_base = SEQID_WREN * 4;
... ... @@ -316,6 +318,9 @@
316 318 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
317 319 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
318 320 #endif
  321 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  322 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  323 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
319 324  
320 325 #ifdef CONFIG_SPI_FLASH_BAR
321 326 /*
322 327  
323 328  
324 329  
325 330  
326 331  
... ... @@ -327,29 +332,47 @@
327 332 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BRRD) |
328 333 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
329 334 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  335 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  336 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  337 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
330 338  
331 339 lut_base = SEQID_BRWR * 4;
332 340 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_BRWR) |
333 341 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
334 342 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
  343 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  344 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  345 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
335 346  
336 347 lut_base = SEQID_RDEAR * 4;
337 348 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RDEAR) |
338 349 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
339 350 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
  351 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  352 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  353 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
340 354  
341 355 lut_base = SEQID_WREAR * 4;
342 356 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WREAR) |
343 357 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
344 358 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
  359 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  360 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  361 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
345 362 #endif
346 363 lut_base = SEQID_RDEVCR * 4;
347 364 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_RD_EVCR) |
348 365 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  366 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  367 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  368 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
349 369  
350 370 lut_base = SEQID_WREVCR * 4;
351 371 fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(FSPI_CMD_WR_EVCR) |
352 372 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  373 + fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
  374 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  375 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
353 376  
354 377 #ifdef CONFIG_FSPI_QUAD_SUPPORT
355 378 /* QUAD OUTPUT READ */
... ... @@ -362,6 +385,8 @@
362 385 OPRND0(0xc) | PAD0(LUT_PAD4) |
363 386 INSTR0(LUT_DUMMY_DDR) | OPRND1(0) |
364 387 PAD1(LUT_PAD4) | INSTR1(LUT_READ_DDR));
  388 + fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
  389 + fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
365 390 #endif
366 391  
367 392 /* Read Flag Status */