Merge git://git.denx.de/u-boot-i2c

Tom Rini
2 parents c8e1ca3ebf 28df8ed07f
Showing 4 changed files Side-by-side Diff
cmd/i2c.c
drivers/i2c/Kconfig
drivers/i2c/at91_i2c.c
drivers/i2c/meson_i2c.c
@@ -1156,7 +1156,10 @@
 	uint	chip;
 	u_char	data[128];
 	u_char	cksum;
-	int	j;
+	int	j, ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+#endif
  
 	static const char *decode_CAS_DDR2[] = {
 		" TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
@@ -1210,7 +1213,14 @@
 	 */
 	chip = simple_strtoul (argv[1], NULL, 16);
  
-	if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
+#ifdef CONFIG_DM_I2C
+	ret = i2c_get_cur_bus_chip(chip, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, 0, data, sizeof(data));
+#else
+	ret = i2c_read(chip, 0, 1, data, sizeof(data));
+#endif
+	if (ret) {
 		puts ("No SDRAM Serial Presence Detect found.\n");
 		return 1;
 	}
@@ -141,7 +141,12 @@
 	bool "Amlogic Meson I2C driver"
 	depends on DM_I2C && ARCH_MESON
 	help
-	  Add support for the Amlogic Meson I2C driver.
+	  Add support for the I2C controller available in Amlogic Meson
+	  SoCs. The controller supports programmable bus speed including
+	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
+	  software to define a flexible format of the bit streams. It has an
+	  internal buffer holding up to 8 bytes for transfers and supports
+	  both 7-bit and 10-bit addresses.
  
 config SYS_I2C_MXC
 	bool "NXP i.MX I2C driver"
@@ -72,6 +72,8 @@
  
 	} else {
 		writel(msg->buf[0], &reg->thr);
+		ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
+
 		for (i = 1; !ret && (i < msg->len); i++) {
 			writel(msg->buf[i], &reg->thr);
 			ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
@@ -199,27 +201,6 @@
 	return 0;
 }
  
-static int at91_i2c_probe_chip(struct udevice *dev, uint chip, uint chip_flags)
-{
-	struct at91_i2c_bus *bus = dev_get_priv(dev);
-	struct at91_i2c_regs *reg = bus->regs;
-	int ret;
-
-	ret = at91_i2c_enable_clk(dev);
-	if (ret)
-		return ret;
-
-	writel(TWI_CR_SWRST, &reg->cr);
-
-	at91_calc_i2c_clock(dev, bus->clock_frequency);
-
-	writel(bus->cwgr_val, &reg->cwgr);
-	writel(TWI_CR_MSEN, &reg->cr);
-	writel(TWI_CR_SVDIS, &reg->cr);
-
-	return 0;
-}
-
 static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
 	struct at91_i2c_bus *bus = dev_get_priv(dev);
@@ -254,7 +235,6 @@
  
 static const struct dm_i2c_ops at91_i2c_ops = {
 	.xfer		= at91_i2c_xfer,
-	.probe_chip	= at91_i2c_probe_chip,
 	.set_bus_speed	= at91_i2c_set_bus_speed,
 	.get_bus_speed	= at91_i2c_get_bus_speed,
 };
@@ -9,7 +9,7 @@
 #include <dm.h>
 #include <i2c.h>
  
-#define I2C_TIMEOUT_MS		500
+#define I2C_TIMEOUT_MS		100
  
 /* Control register fields */
 #define REG_CTRL_START		BIT(0)
@@ -44,12 +44,12 @@
  
 struct meson_i2c {
 	struct i2c_regs *regs;
-	struct i2c_msg *msg;
-	bool last;
-	uint count;
-	uint pos;
-	u32 tokens[2];
-	uint num_tokens;
+	struct i2c_msg *msg;	/* Current I2C message */
+	bool last;		/* Whether the message is the last */
+	uint count;		/* Number of bytes in the current transfer */
+	uint pos;		/* Position of current transfer in message */
+	u32 tokens[2];		/* Sequence of tokens to be written */
+	uint num_tokens;	/* Number of tokens to be written */
 };
  
 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
@@ -69,6 +69,10 @@
 	i2c->num_tokens++;
 }
  
+/*
+ * Retrieve data for the current transfer (which can be at most 8
+ * bytes) from the device internal buffer.
+ */
 static void meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len)
 {
 	u32 rdata0, rdata1;
@@ -86,6 +90,10 @@
 		*buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
 }
  
+/*
+ * Write data for the current transfer (which can be at most 8 bytes)
+ * to the device internal buffer.
+ */
 static void meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len)
 {
 	u32 wdata0 = 0, wdata1 = 0;
@@ -103,6 +111,11 @@
 	debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len);
 }
  
+/*
+ * Prepare the next transfer: pick the next 8 bytes in the remaining
+ * part of message and write tokens and data (if needed) to the
+ * device.
+ */
 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
 {
 	bool write = !(i2c->msg->flags & I2C_M_RD);
@@ -178,7 +191,7 @@
  
 		if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) {
 			debug("meson i2c: error\n");
-			return -ENXIO;
+			return -EREMOTEIO;
 		}
  
 		if ((msg->flags & I2C_M_RD) && i2c->count) {
@@ -200,7 +213,7 @@
 	for (i = 0; i < nmsgs; i++) {
 		ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1);
 		if (ret)
-			return -EREMOTEIO;
+			return ret;
 	}
  
 	return 0;
...	...	@@ -1156,7 +1156,10 @@
1156	1156	uint chip;
1157	1157	u_char data[128];
1158	1158	u_char cksum;
1159		- int j;
	1159	+ int j, ret;
	1160	+#ifdef CONFIG_DM_I2C
	1161	+ struct udevice *dev;
	1162	+#endif
1160	1163
1161	1164	static const char *decode_CAS_DDR2[] = {
1162	1165	" TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
...	...	@@ -1210,7 +1213,14 @@
1210	1213	*/
1211	1214	chip = simple_strtoul (argv[1], NULL, 16);
1212	1215
1213		- if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
	1216	+#ifdef CONFIG_DM_I2C
	1217	+ ret = i2c_get_cur_bus_chip(chip, &dev);
	1218	+ if (!ret)
	1219	+ ret = dm_i2c_read(dev, 0, data, sizeof(data));
	1220	+#else
	1221	+ ret = i2c_read(chip, 0, 1, data, sizeof(data));
	1222	+#endif
	1223	+ if (ret) {
1214	1224	puts ("No SDRAM Serial Presence Detect found.\n");
1215	1225	return 1;
1216	1226	}
...	...	@@ -141,7 +141,12 @@
141	141	bool "Amlogic Meson I2C driver"
142	142	depends on DM_I2C && ARCH_MESON
143	143	help
144		- Add support for the Amlogic Meson I2C driver.
	144	+ Add support for the I2C controller available in Amlogic Meson
	145	+ SoCs. The controller supports programmable bus speed including
	146	+ standard (100kbits/s) and fast (400kbit/s) speed and allows the
	147	+ software to define a flexible format of the bit streams. It has an
	148	+ internal buffer holding up to 8 bytes for transfers and supports
	149	+ both 7-bit and 10-bit addresses.
145	150
146	151	config SYS_I2C_MXC
147	152	bool "NXP i.MX I2C driver"
...	...	@@ -72,6 +72,8 @@
72	72
73	73	} else {
74	74	writel(msg->buf[0], &reg->thr);
	75	+ ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
	76	+
75	77	for (i = 1; !ret && (i < msg->len); i++) {
76	78	writel(msg->buf[i], &reg->thr);
77	79	ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
...	...	@@ -199,27 +201,6 @@
199	201	return 0;
200	202	}
201	203
202		-static int at91_i2c_probe_chip(struct udevice *dev, uint chip, uint chip_flags)
203		-{
204		- struct at91_i2c_bus *bus = dev_get_priv(dev);
205		- struct at91_i2c_regs *reg = bus->regs;
206		- int ret;
207		-
208		- ret = at91_i2c_enable_clk(dev);
209		- if (ret)
210		- return ret;
211		-
212		- writel(TWI_CR_SWRST, &reg->cr);
213		-
214		- at91_calc_i2c_clock(dev, bus->clock_frequency);
215		-
216		- writel(bus->cwgr_val, &reg->cwgr);
217		- writel(TWI_CR_MSEN, &reg->cr);
218		- writel(TWI_CR_SVDIS, &reg->cr);
219		-
220		- return 0;
221		-}
222		-
223	204	static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
224	205	{
225	206	struct at91_i2c_bus *bus = dev_get_priv(dev);
...	...	@@ -254,7 +235,6 @@
254	235
255	236	static const struct dm_i2c_ops at91_i2c_ops = {
256	237	.xfer = at91_i2c_xfer,
257		- .probe_chip = at91_i2c_probe_chip,
258	238	.set_bus_speed = at91_i2c_set_bus_speed,
259	239	.get_bus_speed = at91_i2c_get_bus_speed,
260	240	};
...	...	@@ -9,7 +9,7 @@
9	9	#include <dm.h>
10	10	#include <i2c.h>
11	11
12		-#define I2C_TIMEOUT_MS 500
	12	+#define I2C_TIMEOUT_MS 100
13	13
14	14	/* Control register fields */
15	15	#define REG_CTRL_START BIT(0)
...	...	@@ -44,12 +44,12 @@
44	44
45	45	struct meson_i2c {
46	46	struct i2c_regs *regs;
47		- struct i2c_msg *msg;
48		- bool last;
49		- uint count;
50		- uint pos;
51		- u32 tokens[2];
52		- uint num_tokens;
	47	+ struct i2c_msg msg; / Current I2C message */
	48	+ bool last; /* Whether the message is the last */
	49	+ uint count; /* Number of bytes in the current transfer */
	50	+ uint pos; /* Position of current transfer in message */
	51	+ u32 tokens[2]; /* Sequence of tokens to be written */
	52	+ uint num_tokens; /* Number of tokens to be written */
53	53	};
54	54
55	55	static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
...	...	@@ -69,6 +69,10 @@
69	69	i2c->num_tokens++;
70	70	}
71	71
	72	+/*
	73	+ * Retrieve data for the current transfer (which can be at most 8
	74	+ * bytes) from the device internal buffer.
	75	+ */
72	76	static void meson_i2c_get_data(struct meson_i2c i2c, u8 buf, int len)
73	77	{
74	78	u32 rdata0, rdata1;
...	...	@@ -86,6 +90,10 @@
86	90	buf++ = (rdata1 >> (i - 4) 8) & 0xff;
87	91	}
88	92
	93	+/*
	94	+ * Write data for the current transfer (which can be at most 8 bytes)
	95	+ * to the device internal buffer.
	96	+ */
89	97	static void meson_i2c_put_data(struct meson_i2c i2c, u8 buf, int len)
90	98	{
91	99	u32 wdata0 = 0, wdata1 = 0;
...	...	@@ -103,6 +111,11 @@
103	111	debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len);
104	112	}
105	113
	114	+/*
	115	+ * Prepare the next transfer: pick the next 8 bytes in the remaining
	116	+ * part of message and write tokens and data (if needed) to the
	117	+ * device.
	118	+ */
106	119	static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
107	120	{
108	121	bool write = !(i2c->msg->flags & I2C_M_RD);
...	...	@@ -178,7 +191,7 @@
178	191
179	192	if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) {
180	193	debug("meson i2c: error\n");
181		- return -ENXIO;
	194	+ return -EREMOTEIO;
182	195	}
183	196
184	197	if ((msg->flags & I2C_M_RD) && i2c->count) {
...	...	@@ -200,7 +213,7 @@
200	213	for (i = 0; i < nmsgs; i++) {
201	214	ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1);
202	215	if (ret)
203		- return -EREMOTEIO;
	216	+ return ret;
204	217	}
205	218
206	219	return 0;