Eric Lee / smarc-uboot

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Commit be25ff5c10a7f8292f461599d406d08fa7a89e69

Authored by Leonid Lobachev
Committed by Ji Luo
1 parent 98a6ffadea
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MA-14518 AIY: Enable i2c2 and i2c3 in u-boot. 

Enable i2c2 and i2c3 for AIY.

Change-Id: I984e2e76e7c8929cc62088b6838c81f5dc838568

Showing 1 changed file with 15 additions and 2 deletions Inline Diff

arch/arm/dts/fsl-imx8mq-aiy.dts
Diff comments   View file @ be25ff5
1 /* 1 /*
2 * Copyright 2018 NXP 2 * Copyright 2019 NXP
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15 /dts-v1/; 15 /dts-v1/;
16 16
17 /* First 128KB is for PSCI ATF. */ 17 /* First 128KB is for PSCI ATF. */
18 /memreserve/ 0x40000000 0x00020000; 18 /memreserve/ 0x40000000 0x00020000;
19 19
20 #include "fsl-imx8mq.dtsi" 20 #include "fsl-imx8mq.dtsi"
21 21
22 / { 22 / {
23 model = "Freescale i.MX8MQ AIY"; 23 model = "Freescale i.MX8MQ AIY";
24 compatible = "fsl,imx8mq-aiy", "fsl,imx8mq"; 24 compatible = "fsl,imx8mq-aiy", "fsl,imx8mq";
25 25
26 bcmdhd_wlan_0: bcmdhd_wlan@0 { 26 bcmdhd_wlan_0: bcmdhd_wlan@0 {
27 compatible = "android,bcmdhd_wlan"; 27 compatible = "android,bcmdhd_wlan";
28 bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; 28 bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin";
29 bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; 29 bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal";
30 }; 30 };
31 31
32 chosen { 32 chosen {
33 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; 33 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
34 stdout-path = &uart1; 34 stdout-path = &uart1;
35 }; 35 };
36 36
37 regulators { 37 regulators {
38 compatible = "simple-bus"; 38 compatible = "simple-bus";
39 #address-cells = <1>; 39 #address-cells = <1>;
40 #size-cells = <0>; 40 #size-cells = <0>;
41 41
42 reg_usdhc2_vmmc: usdhc2_vmmc { 42 reg_usdhc2_vmmc: usdhc2_vmmc {
43 compatible = "regulator-fixed"; 43 compatible = "regulator-fixed";
44 regulator-name = "VSD_3V3"; 44 regulator-name = "VSD_3V3";
45 regulator-min-microvolt = <3300000>; 45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>;
47 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 47 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
48 enable-active-high; 48 enable-active-high;
49 }; 49 };
50 }; 50 };
51 51
52 modem_reset: modem-reset { 52 modem_reset: modem-reset {
53 compatible = "gpio-reset"; 53 compatible = "gpio-reset";
54 reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 54 reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
55 reset-delay-us = <2000>; 55 reset-delay-us = <2000>;
56 reset-post-delay-ms = <40>; 56 reset-post-delay-ms = <40>;
57 #reset-cells = <0>; 57 #reset-cells = <0>;
58 }; 58 };
59 59
60 wm8524: wm8524 { 60 wm8524: wm8524 {
61 compatible = "wlf,wm8524"; 61 compatible = "wlf,wm8524";
62 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 62 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
63 clock-names = "mclk"; 63 clock-names = "mclk";
64 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 64 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
65 }; 65 };
66 66
67 sound-wm8524 { 67 sound-wm8524 {
68 compatible = "fsl,imx-audio-wm8524"; 68 compatible = "fsl,imx-audio-wm8524";
69 model = "wm8524-audio"; 69 model = "wm8524-audio";
70 audio-cpu = <&sai2>; 70 audio-cpu = <&sai2>;
71 audio-codec = <&wm8524>; 71 audio-codec = <&wm8524>;
72 audio-routing = 72 audio-routing =
73 "Line Out Jack", "LINEVOUTL", 73 "Line Out Jack", "LINEVOUTL",
74 "Line Out Jack", "LINEVOUTR"; 74 "Line Out Jack", "LINEVOUTR";
75 }; 75 };
76 76
77 pwmleds { 77 pwmleds {
78 compatible = "pwm-leds"; 78 compatible = "pwm-leds";
79 79
80 ledpwm2 { 80 ledpwm2 {
81 label = "PWM2"; 81 label = "PWM2";
82 pwms = <&pwm2 0 50000>; 82 pwms = <&pwm2 0 50000>;
83 max-brightness = <255>; 83 max-brightness = <255>;
84 }; 84 };
85 }; 85 };
86 regulator-virtuals { 86 regulator-virtuals {
87 compatible = "simple-bus"; 87 compatible = "simple-bus";
88 88
89 virt-buck1 { 89 virt-buck1 {
90 compatible = "regulator-virtual"; 90 compatible = "regulator-virtual";
91 virtual-supply = "buck1"; 91 virtual-supply = "buck1";
92 }; 92 };
93 virt-buck2 { 93 virt-buck2 {
94 compatible = "regulator-virtual"; 94 compatible = "regulator-virtual";
95 virtual-supply = "buck2"; 95 virtual-supply = "buck2";
96 }; 96 };
97 virt-buck3 { 97 virt-buck3 {
98 compatible = "regulator-virtual"; 98 compatible = "regulator-virtual";
99 virtual-supply = "buck3"; 99 virtual-supply = "buck3";
100 }; 100 };
101 virt-buck4 { 101 virt-buck4 {
102 compatible = "regulator-virtual"; 102 compatible = "regulator-virtual";
103 virtual-supply = "buck4"; 103 virtual-supply = "buck4";
104 }; 104 };
105 virt-buck5 { 105 virt-buck5 {
106 compatible = "regulator-virtual"; 106 compatible = "regulator-virtual";
107 virtual-supply = "buck5"; 107 virtual-supply = "buck5";
108 }; 108 };
109 virt-buck6 { 109 virt-buck6 {
110 compatible = "regulator-virtual"; 110 compatible = "regulator-virtual";
111 virtual-supply = "buck6"; 111 virtual-supply = "buck6";
112 }; 112 };
113 virt-buck7 { 113 virt-buck7 {
114 compatible = "regulator-virtual"; 114 compatible = "regulator-virtual";
115 virtual-supply = "buck7"; 115 virtual-supply = "buck7";
116 }; 116 };
117 virt-buck8 { 117 virt-buck8 {
118 compatible = "regulator-virtual"; 118 compatible = "regulator-virtual";
119 virtual-supply = "buck8"; 119 virtual-supply = "buck8";
120 }; 120 };
121 virt-ldo1 { 121 virt-ldo1 {
122 compatible = "regulator-virtual"; 122 compatible = "regulator-virtual";
123 virtual-supply = "ldo1"; 123 virtual-supply = "ldo1";
124 }; 124 };
125 virt-ldo2 { 125 virt-ldo2 {
126 compatible = "regulator-virtual"; 126 compatible = "regulator-virtual";
127 virtual-supply = "ldo2"; 127 virtual-supply = "ldo2";
128 }; 128 };
129 virt-ldo3 { 129 virt-ldo3 {
130 compatible = "regulator-virtual"; 130 compatible = "regulator-virtual";
131 virtual-supply = "ldo3"; 131 virtual-supply = "ldo3";
132 }; 132 };
133 virt-ldo4 { 133 virt-ldo4 {
134 compatible = "regulator-virtual"; 134 compatible = "regulator-virtual";
135 virtual-supply = "ldo4"; 135 virtual-supply = "ldo4";
136 }; 136 };
137 virt-ldo5 { 137 virt-ldo5 {
138 compatible = "regulator-virtual"; 138 compatible = "regulator-virtual";
139 virtual-supply = "ldo5"; 139 virtual-supply = "ldo5";
140 }; 140 };
141 virt-ldo6 { 141 virt-ldo6 {
142 compatible = "regulator-virtual"; 142 compatible = "regulator-virtual";
143 virtual-supply = "ldo6"; 143 virtual-supply = "ldo6";
144 }; 144 };
145 virt-ldo7 { 145 virt-ldo7 {
146 compatible = "regulator-virtual"; 146 compatible = "regulator-virtual";
147 virtual-supply = "ldo7"; 147 virtual-supply = "ldo7";
148 }; 148 };
149 }; 149 };
150 }; 150 };
151 151
152 &iomuxc { 152 &iomuxc {
153 pinctrl-names = "default"; 153 pinctrl-names = "default";
154 154
155 imx8mq-evk { 155 imx8mq-evk {
156 pinctrl_fec1: fec1grp { 156 pinctrl_fec1: fec1grp {
157 fsl,pins = < 157 fsl,pins = <
158 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 158 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
159 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 159 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
160 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 160 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
161 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 161 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
162 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 162 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
163 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 163 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
164 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 164 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
165 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 165 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
166 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 166 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
167 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 167 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
168 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 168 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
169 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 169 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
170 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 170 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
171 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 171 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
172 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 172 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
173 >; 173 >;
174 }; 174 };
175 175
176 pinctrl_i2c1: i2c1grp { 176 pinctrl_i2c1: i2c1grp {
177 fsl,pins = < 177 fsl,pins = <
178 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 178 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
179 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 179 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
180 >; 180 >;
181 }; 181 };
182 182
183 pinctrl_i2c2: i2c2grp { 183 pinctrl_i2c2: i2c2grp {
184 fsl,pins = < 184 fsl,pins = <
185 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 185 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
186 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 186 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
187 >; 187 >;
188 }; 188 };
189 189
190 pinctrl_i2c3: i2c3grp {
191 fsl,pins = <
192 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
193 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
194 >;
195 };
190 196
191 pinctrl_pcie0: pcie0grp { 197 pinctrl_pcie0: pcie0grp {
192 fsl,pins = < 198 fsl,pins = <
193 MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 199 MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16
194 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 200 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
195 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 201 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
196 >; 202 >;
197 }; 203 };
198 204
199 pinctrl_pcie1: pcie1grp { 205 pinctrl_pcie1: pcie1grp {
200 fsl,pins = < 206 fsl,pins = <
201 MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 207 MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16
202 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 208 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
203 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 209 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
204 >; 210 >;
205 }; 211 };
206 212
207 pinctrl_pwm2: pwm2grp { 213 pinctrl_pwm2: pwm2grp {
208 fsl,pins = < 214 fsl,pins = <
209 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 215 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
210 >; 216 >;
211 }; 217 };
212 218
213 pinctrl_qspi: qspigrp { 219 pinctrl_qspi: qspigrp {
214 fsl,pins = < 220 fsl,pins = <
215 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 221 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
216 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 222 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
217 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 223 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
218 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 224 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
219 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 225 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
220 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 226 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
221 227
222 >; 228 >;
223 }; 229 };
224 230
225 pinctrl_uart1: uart1grp { 231 pinctrl_uart1: uart1grp {
226 fsl,pins = < 232 fsl,pins = <
227 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 233 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
228 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 234 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
229 >; 235 >;
230 }; 236 };
231 237
232 pinctrl_uart3: uart3grp { 238 pinctrl_uart3: uart3grp {
233 fsl,pins = < 239 fsl,pins = <
234 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 240 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
235 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 241 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
236 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 242 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79
237 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 243 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79
238 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 244 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
239 >; 245 >;
240 }; 246 };
241 247
242 pinctrl_usdhc1: usdhc1grp { 248 pinctrl_usdhc1: usdhc1grp {
243 fsl,pins = < 249 fsl,pins = <
244 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 250 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
245 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 251 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
246 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 252 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
247 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 253 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
248 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 254 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
249 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 255 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
250 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 256 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
251 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 257 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
252 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 258 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
253 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 259 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
254 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 260 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
255 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 261 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
256 >; 262 >;
257 }; 263 };
258 264
259 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 265 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
260 fsl,pins = < 266 fsl,pins = <
261 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 267 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
262 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 268 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
263 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 269 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
264 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 270 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
265 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 271 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
266 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 272 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
267 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 273 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
268 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 274 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
269 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 275 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
270 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 276 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
271 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 277 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
272 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 278 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
273 >; 279 >;
274 }; 280 };
275 281
276 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 282 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
277 fsl,pins = < 283 fsl,pins = <
278 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 284 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
279 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 285 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
280 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 286 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
281 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 287 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
282 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 288 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
283 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 289 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
284 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 290 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
285 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 291 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
286 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 292 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
287 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 293 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
288 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 294 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
289 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 295 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
290 >; 296 >;
291 }; 297 };
292 298
293 pinctrl_usdhc2_gpio: usdhc2grpgpio { 299 pinctrl_usdhc2_gpio: usdhc2grpgpio {
294 fsl,pins = < 300 fsl,pins = <
295 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 301 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
296 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 302 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
297 >; 303 >;
298 }; 304 };
299 305
300 pinctrl_usdhc2: usdhc2grp { 306 pinctrl_usdhc2: usdhc2grp {
301 fsl,pins = < 307 fsl,pins = <
302 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 308 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
303 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 309 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
304 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 310 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
305 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 311 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
306 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 312 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
307 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 313 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
308 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 314 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
309 >; 315 >;
310 }; 316 };
311 317
312 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 318 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
313 fsl,pins = < 319 fsl,pins = <
314 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 320 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
315 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 321 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
316 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 322 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
317 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 323 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
318 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 324 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
319 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 325 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
320 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 326 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
321 >; 327 >;
322 }; 328 };
323 329
324 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 330 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
325 fsl,pins = < 331 fsl,pins = <
326 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 332 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
327 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 333 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
328 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 334 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
329 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 335 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
330 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 336 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
331 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 337 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
332 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 338 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
333 >; 339 >;
334 }; 340 };
335 341
336 pinctrl_sai2: sai2grp { 342 pinctrl_sai2: sai2grp {
337 fsl,pins = < 343 fsl,pins = <
338 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 344 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
339 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 345 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
340 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 346 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
341 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 347 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
342 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 348 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
343 >; 349 >;
344 }; 350 };
345 351
346 pinctrl_wdog: wdoggrp { 352 pinctrl_wdog: wdoggrp {
347 fsl,pins = < 353 fsl,pins = <
348 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 354 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
349 >; 355 >;
350 }; 356 };
351 357
352 pinctrl_pmic: pmicirq { 358 pinctrl_pmic: pmicirq {
353 fsl,pins = < 359 fsl,pins = <
354 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /*0x17059*/ 360 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /*0x17059*/
355 >; 361 >;
356 }; 362 };
357 }; 363 };
358 }; 364 };
359 365
360 &fec1 { 366 &fec1 {
361 pinctrl-names = "default"; 367 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_fec1>; 368 pinctrl-0 = <&pinctrl_fec1>;
363 phy-mode = "rgmii-id"; 369 phy-mode = "rgmii-id";
364 phy-handle = <&ethphy0>; 370 phy-handle = <&ethphy0>;
365 fsl,magic-packet; 371 fsl,magic-packet;
366 status = "okay"; 372 status = "okay";
367 373
368 mdio { 374 mdio {
369 #address-cells = <1>; 375 #address-cells = <1>;
370 #size-cells = <0>; 376 #size-cells = <0>;
371 377
372 ethphy0: ethernet-phy@0 { 378 ethphy0: ethernet-phy@0 {
373 compatible = "ethernet-phy-ieee802.3-c22"; 379 compatible = "ethernet-phy-ieee802.3-c22";
374 reg = <0>; 380 reg = <0>;
375 at803x,led-act-blind-workaround; 381 at803x,led-act-blind-workaround;
376 at803x,eee-disabled; 382 at803x,eee-disabled;
377 }; 383 };
378 }; 384 };
379 }; 385 };
380 386
381 &i2c1 { 387 &i2c1 {
382 clock-frequency = <100000>; 388 clock-frequency = <100000>;
383 pinctrl-names = "default"; 389 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_i2c1>; 390 pinctrl-0 = <&pinctrl_i2c1>;
385 status = "okay"; 391 status = "okay";
386 392
387 pmic: bd71837@4b { 393 pmic: bd71837@4b {
388 reg = <0x4b>; 394 reg = <0x4b>;
389 compatible = "rohm,bd71837"; 395 compatible = "rohm,bd71837";
390 /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */ 396 /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
391 pinctrl-0 = <&pinctrl_pmic>; 397 pinctrl-0 = <&pinctrl_pmic>;
392 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 398 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
393 399
394 bd71837,pmic-buck1-uses-i2c-dvs; 400 bd71837,pmic-buck1-uses-i2c-dvs;
395 bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */ 401 bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */
396 bd71837,pmic-buck2-uses-i2c-dvs; 402 bd71837,pmic-buck2-uses-i2c-dvs;
397 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ 403 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
398 bd71837,pmic-buck3-uses-i2c-dvs; 404 bd71837,pmic-buck3-uses-i2c-dvs;
399 bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */ 405 bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */
400 bd71837,pmic-buck4-uses-i2c-dvs; 406 bd71837,pmic-buck4-uses-i2c-dvs;
401 bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */ 407 bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */
402 408
403 gpo { 409 gpo {
404 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ 410 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
405 }; 411 };
406 412
407 regulators { 413 regulators {
408 #address-cells = <1>; 414 #address-cells = <1>;
409 #size-cells = <0>; 415 #size-cells = <0>;
410 416
411 buck1_reg: regulator@0 { 417 buck1_reg: regulator@0 {
412 reg = <0>; 418 reg = <0>;
413 regulator-compatible = "buck1"; 419 regulator-compatible = "buck1";
414 regulator-min-microvolt = <700000>; 420 regulator-min-microvolt = <700000>;
415 regulator-max-microvolt = <1300000>; 421 regulator-max-microvolt = <1300000>;
416 regulator-boot-on; 422 regulator-boot-on;
417 regulator-always-on; 423 regulator-always-on;
418 regulator-ramp-delay = <1250>; 424 regulator-ramp-delay = <1250>;
419 }; 425 };
420 426
421 buck2_reg: regulator@1 { 427 buck2_reg: regulator@1 {
422 reg = <1>; 428 reg = <1>;
423 regulator-compatible = "buck2"; 429 regulator-compatible = "buck2";
424 regulator-min-microvolt = <700000>; 430 regulator-min-microvolt = <700000>;
425 regulator-max-microvolt = <1300000>; 431 regulator-max-microvolt = <1300000>;
426 regulator-boot-on; 432 regulator-boot-on;
427 regulator-always-on; 433 regulator-always-on;
428 regulator-ramp-delay = <1250>; 434 regulator-ramp-delay = <1250>;
429 }; 435 };
430 436
431 buck3_reg: regulator@2 { 437 buck3_reg: regulator@2 {
432 reg = <2>; 438 reg = <2>;
433 regulator-compatible = "buck3"; 439 regulator-compatible = "buck3";
434 regulator-min-microvolt = <700000>; 440 regulator-min-microvolt = <700000>;
435 regulator-max-microvolt = <1300000>; 441 regulator-max-microvolt = <1300000>;
436 regulator-boot-on; 442 regulator-boot-on;
437 regulator-always-on; 443 regulator-always-on;
438 }; 444 };
439 445
440 buck4_reg: regulator@3 { 446 buck4_reg: regulator@3 {
441 reg = <3>; 447 reg = <3>;
442 regulator-compatible = "buck4"; 448 regulator-compatible = "buck4";
443 regulator-min-microvolt = <700000>; 449 regulator-min-microvolt = <700000>;
444 regulator-max-microvolt = <1300000>; 450 regulator-max-microvolt = <1300000>;
445 regulator-boot-on; 451 regulator-boot-on;
446 regulator-always-on; 452 regulator-always-on;
447 }; 453 };
448 454
449 buck5_reg: regulator@4 { 455 buck5_reg: regulator@4 {
450 reg = <4>; 456 reg = <4>;
451 regulator-compatible = "buck5"; 457 regulator-compatible = "buck5";
452 regulator-min-microvolt = <700000>; 458 regulator-min-microvolt = <700000>;
453 regulator-max-microvolt = <1350000>; 459 regulator-max-microvolt = <1350000>;
454 regulator-boot-on; 460 regulator-boot-on;
455 regulator-always-on; 461 regulator-always-on;
456 }; 462 };
457 463
458 buck6_reg: regulator@5 { 464 buck6_reg: regulator@5 {
459 reg = <5>; 465 reg = <5>;
460 regulator-compatible = "buck6"; 466 regulator-compatible = "buck6";
461 regulator-min-microvolt = <3000000>; 467 regulator-min-microvolt = <3000000>;
462 regulator-max-microvolt = <3300000>; 468 regulator-max-microvolt = <3300000>;
463 regulator-boot-on; 469 regulator-boot-on;
464 regulator-always-on; 470 regulator-always-on;
465 }; 471 };
466 472
467 buck7_reg: regulator@6 { 473 buck7_reg: regulator@6 {
468 reg = <6>; 474 reg = <6>;
469 regulator-compatible = "buck7"; 475 regulator-compatible = "buck7";
470 regulator-min-microvolt = <1605000>; 476 regulator-min-microvolt = <1605000>;
471 regulator-max-microvolt = <1995000>; 477 regulator-max-microvolt = <1995000>;
472 regulator-boot-on; 478 regulator-boot-on;
473 regulator-always-on; 479 regulator-always-on;
474 }; 480 };
475 481
476 buck8_reg: regulator@7 { 482 buck8_reg: regulator@7 {
477 reg = <7>; 483 reg = <7>;
478 regulator-compatible = "buck8"; 484 regulator-compatible = "buck8";
479 regulator-min-microvolt = <800000>; 485 regulator-min-microvolt = <800000>;
480 regulator-max-microvolt = <1400000>; 486 regulator-max-microvolt = <1400000>;
481 regulator-boot-on; 487 regulator-boot-on;
482 regulator-always-on; 488 regulator-always-on;
483 }; 489 };
484 490
485 491
486 ldo1_reg: regulator@8 { 492 ldo1_reg: regulator@8 {
487 reg = <8>; 493 reg = <8>;
488 regulator-compatible = "ldo1"; 494 regulator-compatible = "ldo1";
489 regulator-min-microvolt = <3000000>; 495 regulator-min-microvolt = <3000000>;
490 regulator-max-microvolt = <3300000>; 496 regulator-max-microvolt = <3300000>;
491 regulator-boot-on; 497 regulator-boot-on;
492 regulator-always-on; 498 regulator-always-on;
493 }; 499 };
494 500
495 ldo2_reg: regulator@9 { 501 ldo2_reg: regulator@9 {
496 reg = <9>; 502 reg = <9>;
497 regulator-compatible = "ldo2"; 503 regulator-compatible = "ldo2";
498 regulator-min-microvolt = <900000>; 504 regulator-min-microvolt = <900000>;
499 regulator-max-microvolt = <900000>; 505 regulator-max-microvolt = <900000>;
500 regulator-boot-on; 506 regulator-boot-on;
501 regulator-always-on; 507 regulator-always-on;
502 }; 508 };
503 509
504 ldo3_reg: regulator@10 { 510 ldo3_reg: regulator@10 {
505 reg = <10>; 511 reg = <10>;
506 regulator-compatible = "ldo3"; 512 regulator-compatible = "ldo3";
507 regulator-min-microvolt = <1800000>; 513 regulator-min-microvolt = <1800000>;
508 regulator-max-microvolt = <3300000>; 514 regulator-max-microvolt = <3300000>;
509 regulator-boot-on; 515 regulator-boot-on;
510 regulator-always-on; 516 regulator-always-on;
511 }; 517 };
512 518
513 ldo4_reg: regulator@11 { 519 ldo4_reg: regulator@11 {
514 reg = <11>; 520 reg = <11>;
515 regulator-compatible = "ldo4"; 521 regulator-compatible = "ldo4";
516 regulator-min-microvolt = <900000>; 522 regulator-min-microvolt = <900000>;
517 regulator-max-microvolt = <1800000>; 523 regulator-max-microvolt = <1800000>;
518 regulator-boot-on; 524 regulator-boot-on;
519 regulator-always-on; 525 regulator-always-on;
520 }; 526 };
521 527
522 ldo5_reg: regulator@12 { 528 ldo5_reg: regulator@12 {
523 reg = <12>; 529 reg = <12>;
524 regulator-compatible = "ldo5"; 530 regulator-compatible = "ldo5";
525 regulator-min-microvolt = <1800000>; 531 regulator-min-microvolt = <1800000>;
526 regulator-max-microvolt = <3300000>; 532 regulator-max-microvolt = <3300000>;
527 regulator-boot-on; 533 regulator-boot-on;
528 regulator-always-on; 534 regulator-always-on;
529 }; 535 };
530 536
531 ldo6_reg: regulator@13 { 537 ldo6_reg: regulator@13 {
532 reg = <13>; 538 reg = <13>;
533 regulator-compatible = "ldo6"; 539 regulator-compatible = "ldo6";
534 regulator-min-microvolt = <900000>; 540 regulator-min-microvolt = <900000>;
535 regulator-max-microvolt = <1800000>; 541 regulator-max-microvolt = <1800000>;
536 regulator-boot-on; 542 regulator-boot-on;
537 regulator-always-on; 543 regulator-always-on;
538 }; 544 };
539 545
540 ldo7_reg: regulator@14 { 546 ldo7_reg: regulator@14 {
541 reg = <14>; 547 reg = <14>;
542 regulator-compatible = "ldo7"; 548 regulator-compatible = "ldo7";
543 regulator-min-microvolt = <1800000>; 549 regulator-min-microvolt = <1800000>;
544 regulator-max-microvolt = <3300000>; 550 regulator-max-microvolt = <3300000>;
545 regulator-boot-on; 551 regulator-boot-on;
546 regulator-always-on; 552 regulator-always-on;
547 }; 553 };
548 }; 554 };
549 }; 555 };
550 556
551 adv7535: adv7535@3d { 557 adv7535: adv7535@3d {
552 compatible = "adi,adv7535"; 558 compatible = "adi,adv7535";
553 reg = <0x3d>; /* PD pin is low */ 559 reg = <0x3d>; /* PD pin is low */
554 /* TODO: pin config & irq */ 560 /* TODO: pin config & irq */
555 video-mode = <34>; /* 1920x1080@30HZ */ 561 video-mode = <34>; /* 1920x1080@30HZ */
556 dsi-traffic-mode = <0>; 562 dsi-traffic-mode = <0>;
557 bpp = <24>; 563 bpp = <24>;
558 status = "okay"; 564 status = "okay";
559 port { 565 port {
560 dsi_to_hdmi: endpoint { 566 dsi_to_hdmi: endpoint {
561 remote-endpoint = <&mipi_dsi_ep>; 567 remote-endpoint = <&mipi_dsi_ep>;
562 }; 568 };
563 }; 569 };
564 }; 570 };
565 }; 571 };
566 572
567 &i2c2 { 573 &i2c2 {
568 clock-frequency = <100000>; 574 clock-frequency = <100000>;
569 pinctrl-names = "default"; 575 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_i2c2>; 576 pinctrl-0 = <&pinctrl_i2c2>;
571 status = "disabled"; 577 status = "okay";
578 };
579
580 &i2c3 {
581 clock-frequency = <100000>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_i2c3>;
584 status = "okay";
572 }; 585 };
573 586
574 &pcie0{ 587 &pcie0{
575 pinctrl-names = "default"; 588 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_pcie0>; 589 pinctrl-0 = <&pinctrl_pcie0>;
577 clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; 590 clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
578 disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; 591 disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
579 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; 592 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
580 status = "okay"; 593 status = "okay";
581 }; 594 };
582 595
583 &pcie1{ 596 &pcie1{
584 pinctrl-names = "default"; 597 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_pcie1>; 598 pinctrl-0 = <&pinctrl_pcie1>;
586 clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; 599 clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
587 disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; 600 disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
588 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; 601 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
589 status = "okay"; 602 status = "okay";
590 }; 603 };
591 604
592 &pwm2 { 605 &pwm2 {
593 pinctrl-names = "default"; 606 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_pwm2>; 607 pinctrl-0 = <&pinctrl_pwm2>;
595 status = "okay"; 608 status = "okay";
596 }; 609 };
597 610
598 &uart1 { /* console */ 611 &uart1 { /* console */
599 pinctrl-names = "default"; 612 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_uart1>; 613 pinctrl-0 = <&pinctrl_uart1>;
601 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; 614 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
602 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 615 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
603 status = "okay"; 616 status = "okay";
604 }; 617 };
605 618
606 &lcdif { 619 &lcdif {
607 status = "okay"; 620 status = "okay";
608 disp-dev = "mipi_dsi_northwest"; 621 disp-dev = "mipi_dsi_northwest";
609 display = <&display0>; 622 display = <&display0>;
610 623
611 display0: display@0 { 624 display0: display@0 {
612 bits-per-pixel = <24>; 625 bits-per-pixel = <24>;
613 bus-width = <24>; 626 bus-width = <24>;
614 627
615 display-timings { 628 display-timings {
616 native-mode = <&timing0>; 629 native-mode = <&timing0>;
617 timing0: timing0 { 630 timing0: timing0 {
618 clock-frequency = <9200000>; 631 clock-frequency = <9200000>;
619 hactive = <480>; 632 hactive = <480>;
620 vactive = <272>; 633 vactive = <272>;
621 hfront-porch = <8>; 634 hfront-porch = <8>;
622 hback-porch = <4>; 635 hback-porch = <4>;
623 hsync-len = <41>; 636 hsync-len = <41>;
624 vback-porch = <2>; 637 vback-porch = <2>;
625 vfront-porch = <4>; 638 vfront-porch = <4>;
626 vsync-len = <10>; 639 vsync-len = <10>;
627 640
628 hsync-active = <0>; 641 hsync-active = <0>;
629 vsync-active = <0>; 642 vsync-active = <0>;
630 de-active = <1>; 643 de-active = <1>;
631 pixelclk-active = <0>; 644 pixelclk-active = <0>;
632 }; 645 };
633 }; 646 };
634 }; 647 };
635 }; 648 };
636 649
637 &qspi { 650 &qspi {
638 pinctrl-names = "default"; 651 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_qspi>; 652 pinctrl-0 = <&pinctrl_qspi>;
640 status = "okay"; 653 status = "okay";
641 654
642 flash0: n25q256a@0 { 655 flash0: n25q256a@0 {
643 reg = <0>; 656 reg = <0>;
644 #address-cells = <1>; 657 #address-cells = <1>;
645 #size-cells = <1>; 658 #size-cells = <1>;
646 compatible = "micron,n25q256a"; 659 compatible = "micron,n25q256a";
647 spi-max-frequency = <29000000>; 660 spi-max-frequency = <29000000>;
648 spi-nor,ddr-quad-read-dummy = <6>; 661 spi-nor,ddr-quad-read-dummy = <6>;
649 }; 662 };
650 }; 663 };
651 664
652 &mipi_dsi { 665 &mipi_dsi {
653 reset = <&src>; 666 reset = <&src>;
654 mux-sel = <&gpr>; /* lcdif or dcss */ 667 mux-sel = <&gpr>; /* lcdif or dcss */
655 status = "okay"; 668 status = "okay";
656 port { 669 port {
657 mipi_dsi_ep: endpoint { 670 mipi_dsi_ep: endpoint {
658 remote-endpoint = <&dsi_to_hdmi>; 671 remote-endpoint = <&dsi_to_hdmi>;
659 }; 672 };
660 }; 673 };
661 }; 674 };
662 675
663 &uart3 { /* BT */ 676 &uart3 { /* BT */
664 pinctrl-names = "default"; 677 pinctrl-names = "default";
665 pinctrl-0 = <&pinctrl_uart3>; 678 pinctrl-0 = <&pinctrl_uart3>;
666 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; 679 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
667 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 680 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
668 fsl,uart-has-rtscts; 681 fsl,uart-has-rtscts;
669 resets = <&modem_reset>; 682 resets = <&modem_reset>;
670 status = "okay"; 683 status = "okay";
671 }; 684 };
672 685
673 &usdhc1 { 686 &usdhc1 {
674 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 687 pinctrl-names = "default", "state_100mhz", "state_200mhz";
675 pinctrl-0 = <&pinctrl_usdhc1>; 688 pinctrl-0 = <&pinctrl_usdhc1>;
676 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 689 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
677 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 690 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
678 bus-width = <8>; 691 bus-width = <8>;
679 non-removable; 692 non-removable;
680 status = "okay"; 693 status = "okay";
681 }; 694 };
682 695
683 &usdhc2 { 696 &usdhc2 {
684 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 697 pinctrl-names = "default", "state_100mhz", "state_200mhz";
685 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 698 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
686 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 699 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
687 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 700 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
688 bus-width = <4>; 701 bus-width = <4>;
689 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 702 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
690 vmmc-supply = <&reg_usdhc2_vmmc>; 703 vmmc-supply = <&reg_usdhc2_vmmc>;
691 status = "okay"; 704 status = "okay";
692 }; 705 };
693 706
694 &usb3_phy0 { 707 &usb3_phy0 {
695 status = "okay"; 708 status = "okay";
696 }; 709 };
697 710
698 &usb3_0 { 711 &usb3_0 {
699 status = "okay"; 712 status = "okay";
700 }; 713 };
701 714
702 &usb_dwc3_0 { 715 &usb_dwc3_0 {
703 status = "okay"; 716 status = "okay";
704 dr_mode = "peripheral"; 717 dr_mode = "peripheral";
705 }; 718 };
706 719
707 &usb3_phy1 { 720 &usb3_phy1 {
708 status = "okay"; 721 status = "okay";
709 }; 722 };
710 723
711 &usb3_1 { 724 &usb3_1 {
712 status = "okay"; 725 status = "okay";
713 }; 726 };
714 727
715 &usb_dwc3_1 { 728 &usb_dwc3_1 {
716 status = "okay"; 729 status = "okay";
717 dr_mode = "host"; 730 dr_mode = "host";
718 }; 731 };
719 732
720 &sai2 { 733 &sai2 {
721 pinctrl-names = "default"; 734 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_sai2>; 735 pinctrl-0 = <&pinctrl_sai2>;
723 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, 736 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
724 <&clk IMX8MQ_AUDIO_PLL1>, 737 <&clk IMX8MQ_AUDIO_PLL1>,
725 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, 738 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
726 <&clk IMX8MQ_CLK_SAI2_DIV>; 739 <&clk IMX8MQ_CLK_SAI2_DIV>;
727 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 740 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
728 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; 741 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
729 status = "okay"; 742 status = "okay";
730 }; 743 };
731 744
732 &gpu { 745 &gpu {
733 status = "okay"; 746 status = "okay";
734 }; 747 };
735 748
736 &vpu { 749 &vpu {
737 status = "okay"; 750 status = "okay";
738 }; 751 };
739 752
740 &wdog1 { 753 &wdog1 {
741 pinctrl-names = "default"; 754 pinctrl-names = "default";
742 pinctrl-0 = <&pinctrl_wdog>; 755 pinctrl-0 = <&pinctrl_wdog>;
743 fsl,ext-reset-output; 756 fsl,ext-reset-output;
744 status = "okay"; 757 status = "okay";
745 }; 758 };
746 759