Blackfin: overhaul i2c driver

The current Blackfin i2c driver does not work properly with certain devices due to it breaking up transfers incorrectly. This is a rewrite of the driver and relocates it to the newer place in the source tree. Also remove duplicated I2C speed defines in Blackfin board configs and disable I2C slave address usage since it isn't implemented. Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Blackfin: overhaul i2c driver
The current Blackfin i2c driver does not work properly with certain devices due to it breaking up transfers incorrectly. This is a rewrite of the driver and relocates it to the newer place in the source tree. Also remove duplicated I2C speed defines in Blackfin board configs and disable I2C slave address usage since it isn't implemented. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger
1 parent b6edc719a1
Showing 7 changed files with 293 additions and 470 deletions Side-by-side Diff
cpu/blackfin/Makefile
cpu/blackfin/i2c.c
drivers/i2c/Makefile
drivers/i2c/bfin-twi_i2c.c
include/configs/bf533-ezkit.h
include/configs/bf533-stamp.h
include/configs/bf537-stamp.h
@@ -17,7 +17,7 @@
 CEXTRA   := initcode.o
 SEXTRA   := start.o
 SOBJS    := interrupt.o cache.o
-COBJS    := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
+COBJS    := cpu.o traps.o interrupts.o reset.o serial.o watchdog.o
  
 ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
 COBJS    += initcode.o
-/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
- *
- * Copyright (c) 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/twi.h>
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF) */
-#ifdef TWI0_CLKDIV
-#define bfin_read_TWI_CLKDIV()               bfin_read_TWI0_CLKDIV()
-#define bfin_write_TWI_CLKDIV(val)           bfin_write_TWI0_CLKDIV(val)
-#define bfin_read_TWI_CONTROL()              bfin_read_TWI0_CONTROL()
-#define bfin_write_TWI_CONTROL(val)          bfin_write_TWI0_CONTROL(val)
-#define bfin_read_TWI_SLAVE_CTL()            bfin_read_TWI0_SLAVE_CTL()
-#define bfin_write_TWI_SLAVE_CTL(val)        bfin_write_TWI0_SLAVE_CTL(val)
-#define bfin_read_TWI_SLAVE_STAT()           bfin_read_TWI0_SLAVE_STAT()
-#define bfin_write_TWI_SLAVE_STAT(val)       bfin_write_TWI0_SLAVE_STAT(val)
-#define bfin_read_TWI_SLAVE_ADDR()           bfin_read_TWI0_SLAVE_ADDR()
-#define bfin_write_TWI_SLAVE_ADDR(val)       bfin_write_TWI0_SLAVE_ADDR(val)
-#define bfin_read_TWI_MASTER_CTL()           bfin_read_TWI0_MASTER_CTL()
-#define bfin_write_TWI_MASTER_CTL(val)       bfin_write_TWI0_MASTER_CTL(val)
-#define bfin_read_TWI_MASTER_STAT()          bfin_read_TWI0_MASTER_STAT()
-#define bfin_write_TWI_MASTER_STAT(val)      bfin_write_TWI0_MASTER_STAT(val)
-#define bfin_read_TWI_MASTER_ADDR()          bfin_read_TWI0_MASTER_ADDR()
-#define bfin_write_TWI_MASTER_ADDR(val)      bfin_write_TWI0_MASTER_ADDR(val)
-#define bfin_read_TWI_INT_STAT()             bfin_read_TWI0_INT_STAT()
-#define bfin_write_TWI_INT_STAT(val)         bfin_write_TWI0_INT_STAT(val)
-#define bfin_read_TWI_INT_MASK()             bfin_read_TWI0_INT_MASK()
-#define bfin_write_TWI_INT_MASK(val)         bfin_write_TWI0_INT_MASK(val)
-#define bfin_read_TWI_FIFO_CTL()             bfin_read_TWI0_FIFO_CTL()
-#define bfin_write_TWI_FIFO_CTL(val)         bfin_write_TWI0_FIFO_CTL(val)
-#define bfin_read_TWI_FIFO_STAT()            bfin_read_TWI0_FIFO_STAT()
-#define bfin_write_TWI_FIFO_STAT(val)        bfin_write_TWI0_FIFO_STAT(val)
-#define bfin_read_TWI_XMT_DATA8()            bfin_read_TWI0_XMT_DATA8()
-#define bfin_write_TWI_XMT_DATA8(val)        bfin_write_TWI0_XMT_DATA8(val)
-#define bfin_read_TWI_XMT_DATA_16()          bfin_read_TWI0_XMT_DATA16()
-#define bfin_write_TWI_XMT_DATA16(val)       bfin_write_TWI0_XMT_DATA16(val)
-#define bfin_read_TWI_RCV_DATA8()            bfin_read_TWI0_RCV_DATA8()
-#define bfin_write_TWI_RCV_DATA8(val)        bfin_write_TWI0_RCV_DATA8(val)
-#define bfin_read_TWI_RCV_DATA16()           bfin_read_TWI0_RCV_DATA16()
-#define bfin_write_TWI_RCV_DATA16(val)       bfin_write_TWI0_RCV_DATA16(val)
-#endif
-
-#ifdef DEBUG_I2C
-#define PRINTD(fmt,args...)	do {	\
-	DECLARE_GLOBAL_DATA_PTR;	\
-	if (gd->have_console)		\
-		printf(fmt ,##args);	\
-	} while (0)
-#else
-#define PRINTD(fmt,args...)
-#endif
-
-#ifndef CONFIG_TWICLK_KHZ
-#define CONFIG_TWICLK_KHZ	50
-#endif
-
-/* All transfers are described by this data structure */
-struct i2c_msg {
-	u16 addr;		/* slave address */
-	u16 flags;
-#define I2C_M_STOP		0x2
-#define I2C_M_RD		0x1
-	u16 len;		/* msg length */
-	u8 *buf;		/* pointer to msg data */
-};
-
-/**
- * i2c_reset: - reset the host controller
- */
-static void i2c_reset(void)
-{
-	/* Disable TWI */
-	bfin_write_TWI_CONTROL(0);
-	SSYNC();
-
-	/* Set TWI internal clock as 10MHz */
-	bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
-
-	/* Set Twi interface clock as specified */
-	if (CONFIG_TWICLK_KHZ > 400)
-		bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
-						400) & 0xFF));
-	else
-		bfin_write_TWI_CLKDIV(((5 * 1024 /
-					CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
-						CONFIG_TWICLK_KHZ)
-						& 0xFF));
-
-	/* Enable TWI */
-	bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
-	SSYNC();
-}
-
-int wait_for_completion(struct i2c_msg *msg, int timeout_count)
-{
-	unsigned short twi_int_stat;
-	unsigned short mast_stat;
-	int i;
-
-	for (i = 0; i < timeout_count; i++) {
-		twi_int_stat = bfin_read_TWI_INT_STAT();
-		mast_stat = bfin_read_TWI_MASTER_STAT();
-
-		if (XMTSERV & twi_int_stat) {
-			/* Transmit next data */
-			if (msg->len > 0) {
-				bfin_write_TWI_XMT_DATA8(*(msg->buf++));
-				msg->len--;
-			} else if (msg->flags & I2C_M_STOP)
-				bfin_write_TWI_MASTER_CTL
-				    (bfin_read_TWI_MASTER_CTL() | STOP);
-			SSYNC();
-			/* Clear status */
-			bfin_write_TWI_INT_STAT(XMTSERV);
-			SSYNC();
-			i = 0;
-		}
-		if (RCVSERV & twi_int_stat) {
-			if (msg->len > 0) {
-				/* Receive next data */
-				*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
-				msg->len--;
-			} else if (msg->flags & I2C_M_STOP) {
-				bfin_write_TWI_MASTER_CTL
-				    (bfin_read_TWI_MASTER_CTL() | STOP);
-				SSYNC();
-			}
-			/* Clear interrupt source */
-			bfin_write_TWI_INT_STAT(RCVSERV);
-			SSYNC();
-			i = 0;
-		}
-		if (MERR & twi_int_stat) {
-			bfin_write_TWI_INT_STAT(MERR);
-			bfin_write_TWI_INT_MASK(0);
-			bfin_write_TWI_MASTER_STAT(0x3e);
-			bfin_write_TWI_MASTER_CTL(0);
-			SSYNC();
-			/*
-			 * if both err and complete int stats are set,
-			 * return proper results.
-			 */
-			if (MCOMP & twi_int_stat) {
-				bfin_write_TWI_INT_STAT(MCOMP);
-				bfin_write_TWI_INT_MASK(0);
-				bfin_write_TWI_MASTER_CTL(0);
-				SSYNC();
-				/*
-				 * If it is a quick transfer,
-				 * only address bug no data, not an err.
-				 */
-				if (msg->len == 0 && mast_stat & BUFRDERR)
-					return 0;
-				/*
-				 * If address not acknowledged return -3,
-				 * else return 0.
-				 */
-				else if (!(mast_stat & ANAK))
-					return 0;
-				else
-					return -3;
-			}
-			return -1;
-		}
-		if (MCOMP & twi_int_stat) {
-			bfin_write_TWI_INT_STAT(MCOMP);
-			SSYNC();
-			bfin_write_TWI_INT_MASK(0);
-			bfin_write_TWI_MASTER_CTL(0);
-			SSYNC();
-			return 0;
-		}
-	}
-	if (msg->flags & I2C_M_RD)
-		return -4;
-	else
-		return -2;
-}
-
-/**
- * i2c_transfer: - Transfer one byte over the i2c bus
- *
- * This function can tranfer a byte over the i2c bus in both directions.
- * It is used by the public API functions.
- *
- * @return:	 0: transfer successful
- *		-1: transfer fail
- *		-2: transmit timeout
- *		-3: ACK missing
- *		-4: receive timeout
- *		-5: controller not ready
- */
-int i2c_transfer(struct i2c_msg *msg)
-{
-	int ret = 0;
-	int timeout_count = 10000;
-	int len = msg->len;
-
-	if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
-		ret = -5;
-		goto transfer_error;
-	}
-
-	while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
-		continue;
-
-	/* Set Transmit device address */
-	bfin_write_TWI_MASTER_ADDR(msg->addr);
-
-	/*
-	 * FIFO Initiation.
-	 * Data in FIFO should be discarded before start a new operation.
-	 */
-	bfin_write_TWI_FIFO_CTL(0x3);
-	SSYNC();
-	bfin_write_TWI_FIFO_CTL(0);
-	SSYNC();
-
-	if (!(msg->flags & I2C_M_RD)) {
-		/* Transmit first data */
-		if (msg->len > 0) {
-			PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
-			       len);
-			bfin_write_TWI_XMT_DATA8(*(msg->buf++));
-			msg->len--;
-			SSYNC();
-		}
-	}
-
-	/* clear int stat */
-	bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
-
-	/* Interrupt mask . Enable XMT, RCV interrupt */
-	bfin_write_TWI_INT_MASK(MCOMP | MERR |
-			((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
-	SSYNC();
-
-	if (len > 0 && len <= 255)
-		bfin_write_TWI_MASTER_CTL((len << 6));
-	else if (msg->len > 255) {
-		bfin_write_TWI_MASTER_CTL((0xff << 6));
-		msg->flags &= I2C_M_STOP;
-	} else
-		bfin_write_TWI_MASTER_CTL(0);
-
-	/* Master enable */
-	bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
-			((msg->flags & I2C_M_RD)
-			 ? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
-					 100) ? FAST : 0));
-	SSYNC();
-
-	ret = wait_for_completion(msg, timeout_count);
-	PRINTD("3 in i2c_transfer: ret=%d\n", ret);
-
- transfer_error:
-	switch (ret) {
-	case 1:
-		PRINTD(("i2c_transfer: error: transfer fail\n"));
-		break;
-	case 2:
-		PRINTD(("i2c_transfer: error: transmit timeout\n"));
-		break;
-	case 3:
-		PRINTD(("i2c_transfer: error: ACK missing\n"));
-		break;
-	case 4:
-		PRINTD(("i2c_transfer: error: receive timeout\n"));
-		break;
-	case 5:
-		PRINTD(("i2c_transfer: error: controller not ready\n"));
-		i2c_reset();
-		break;
-	default:
-		break;
-	}
-	return ret;
-
-}
-
-/* ---------------------------------------------------------------------*/
-/* API Functions							*/
-/* ---------------------------------------------------------------------*/
-
-void i2c_init(int speed, int slaveaddr)
-{
-	i2c_reset();
-}
-
-/**
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip:	address of the chip which is searched for
- * @return:	0 if a chip was found, -1 otherwhise
- */
-
-int i2c_probe(uchar chip)
-{
-	struct i2c_msg msg;
-	u8 probebuf;
-
-	i2c_reset();
-
-	probebuf = 0;
-	msg.addr = chip;
-	msg.flags = 0;
-	msg.len = 1;
-	msg.buf = &probebuf;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	msg.addr = chip;
-	msg.flags = I2C_M_RD;
-	msg.len = 1;
-	msg.buf = &probebuf;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	return 0;
-}
-
-/**
- *   i2c_read: - Read multiple bytes from an i2c device
- *
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *		memories, 0 for register type devices with only one
- *		register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-
-int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	struct i2c_msg msg;
-	u8 addr_bytes[3];	/* lowest...highest byte of data address */
-
-	PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
-			addr, alen, len);
-
-	if (alen > 0) {
-		addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
-		addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
-		addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
-		msg.addr = chip;
-		msg.flags = 0;
-		msg.len = alen;
-		msg.buf = addr_bytes;
-		if (i2c_transfer(&msg))
-			return -1;
-	}
-
-	/* start read sequence */
-	PRINTD(("i2c_read: start read sequence\n"));
-	msg.addr = chip;
-	msg.flags = I2C_M_RD;
-	msg.len = len;
-	msg.buf = buffer;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	return 0;
-}
-
-/**
- *   i2c_write: -  Write multiple bytes to an i2c device
- *
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *		memories, 0 for register type devices with only one
- *		register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-
-int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	struct i2c_msg msg;
-	u8 addr_bytes[3];	/* lowest...highest byte of data address */
-
-	PRINTD
-		("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
-		 chip, addr, alen, len, buffer[0]);
-
-	/* chip address write */
-	if (alen > 0) {
-		addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
-		addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
-		addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
-		msg.addr = chip;
-		msg.flags = 0;
-		msg.len = alen;
-		msg.buf = addr_bytes;
-		if (i2c_transfer(&msg))
-			return -1;
-	}
-
-	/* start read sequence */
-	PRINTD(("i2c_write: start write sequence\n"));
-	msg.addr = chip;
-	msg.flags = 0;
-	msg.len = len;
-	msg.buf = buffer;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	return 0;
-
-}
-
-#endif /* CONFIG_HARD_I2C */
@@ -25,6 +25,7 @@
  
 LIB	:= $(obj)libi2c.a
  
+COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
 COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
+/*
+ * i2c.c - driver for Blackfin on-chip TWI/I2C
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/twi.h>
+
+#ifdef DEBUG
+# define dmemset(s, c, n) memset(s, c, n)
+#else
+# define dmemset(s, c, n)
+#endif
+#define debugi(fmt, args...) \
+	debug( \
+		"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \
+		"%-20s:%-3i: " fmt "\n", \
+		bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
+		__func__, __LINE__, ## args)
+
+#ifdef TWI0_CLKDIV
+#define bfin_write_TWI_CLKDIV(val)           bfin_write_TWI0_CLKDIV(val)
+#define bfin_write_TWI_CONTROL(val)          bfin_write_TWI0_CONTROL(val)
+#define bfin_read_TWI_CONTROL(val)           bfin_read_TWI0_CONTROL(val)
+#define bfin_write_TWI_MASTER_ADDR(val)      bfin_write_TWI0_MASTER_ADDR(val)
+#define bfin_write_TWI_XMT_DATA8(val)        bfin_write_TWI0_XMT_DATA8(val)
+#define bfin_read_TWI_RCV_DATA8()            bfin_read_TWI0_RCV_DATA8()
+#define bfin_read_TWI_INT_STAT()             bfin_read_TWI0_INT_STAT()
+#define bfin_write_TWI_INT_STAT(val)         bfin_write_TWI0_INT_STAT(val)
+#define bfin_read_TWI_MASTER_STAT()          bfin_read_TWI0_MASTER_STAT()
+#define bfin_write_TWI_MASTER_STAT(val)      bfin_write_TWI0_MASTER_STAT(val)
+#define bfin_read_TWI_MASTER_CTL()           bfin_read_TWI0_MASTER_CTL()
+#define bfin_write_TWI_MASTER_CTL(val)       bfin_write_TWI0_MASTER_CTL(val)
+#define bfin_write_TWI_INT_MASK(val)         bfin_write_TWI0_INT_MASK(val)
+#define bfin_write_TWI_FIFO_CTL(val)         bfin_write_TWI0_FIFO_CTL(val)
+#endif
+
+#ifdef CONFIG_TWICLK_KHZ
+# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
+#endif
+#if CONFIG_SYS_I2C_SPEED > 400000
+# error The Blackfin I2C hardware can only operate at 400KHz max
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+	u8 flags;
+#define I2C_M_COMBO		0x4
+#define I2C_M_STOP		0x2
+#define I2C_M_READ		0x1
+	int len;		/* msg length */
+	u8 *buf;		/* pointer to msg data */
+	int alen;		/* addr length */
+	u8 *abuf;		/* addr buffer */
+};
+
+/**
+ * wait_for_completion - manage the actual i2c transfer
+ *	@msg: the i2c msg
+ */
+static int wait_for_completion(struct i2c_msg *msg)
+{
+	uint16_t int_stat;
+
+	while (!ctrlc()) {
+		int_stat = bfin_read_TWI_INT_STAT();
+
+		if (int_stat & XMTSERV) {
+			debugi("processing XMTSERV");
+			bfin_write_TWI_INT_STAT(XMTSERV);
+			SSYNC();
+			if (msg->alen) {
+				bfin_write_TWI_XMT_DATA8(*(msg->abuf++));
+				--msg->alen;
+			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
+				bfin_write_TWI_XMT_DATA8(*(msg->buf++));
+				--msg->len;
+			} else {
+				bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
+					(msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP));
+				SSYNC();
+			}
+		}
+		if (int_stat & RCVSERV) {
+			debugi("processing RCVSERV");
+			bfin_write_TWI_INT_STAT(RCVSERV);
+			SSYNC();
+			if (msg->len) {
+				*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
+				--msg->len;
+			} else if (msg->flags & I2C_M_STOP) {
+				bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP);
+				SSYNC();
+			}
+		}
+		if (int_stat & MERR) {
+			debugi("processing MERR");
+			bfin_write_TWI_INT_STAT(MERR);
+			SSYNC();
+			break;
+		}
+		if (int_stat & MCOMP) {
+			debugi("processing MCOMP");
+			bfin_write_TWI_INT_STAT(MCOMP);
+			SSYNC();
+			if (msg->flags & I2C_M_COMBO && msg->len) {
+				bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) |
+					(min(msg->len, 0xff) << 6) | MEN | MDIR);
+				SSYNC();
+			} else
+				break;
+		}
+	}
+
+	return msg->len;
+}
+
+/**
+ * i2c_transfer - setup an i2c transfer
+ *	@return: 0 if things worked, non-0 if things failed
+ *
+ *	Here we just get the i2c stuff all prepped and ready, and then tail off
+ *	into wait_for_completion() for all the bits to go.
+ */
+static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
+{
+	uchar addr_buffer[] = {
+		(addr >>  0),
+		(addr >>  8),
+		(addr >> 16),
+	};
+	struct i2c_msg msg = {
+		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
+		.buf   = buffer,
+		.len   = len,
+		.abuf  = addr_buffer,
+		.alen  = alen,
+	};
+	int ret;
+
+	dmemset(buffer, 0xff, len);
+	debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
+		chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
+
+	/* wait for things to settle */
+	while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
+		if (ctrlc())
+			return 1;
+
+	/* Set Transmit device address */
+	bfin_write_TWI_MASTER_ADDR(chip);
+
+	/* Clear the FIFO before starting things */
+	bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH);
+	SSYNC();
+	bfin_write_TWI_FIFO_CTL(0);
+	SSYNC();
+
+	/* prime the pump */
+	if (msg.alen) {
+		len = msg.alen;
+		debugi("first byte=0x%02x", *msg.abuf);
+		bfin_write_TWI_XMT_DATA8(*(msg.abuf++));
+		--msg.alen;
+	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
+		debugi("first byte=0x%02x", *msg.buf);
+		bfin_write_TWI_XMT_DATA8(*(msg.buf++));
+		--msg.len;
+	}
+
+	/* clear int stat */
+	bfin_write_TWI_MASTER_STAT(-1);
+	bfin_write_TWI_INT_STAT(-1);
+	bfin_write_TWI_INT_MASK(0);
+	SSYNC();
+
+	/* Master enable */
+	bfin_write_TWI_MASTER_CTL(
+			(bfin_read_TWI_MASTER_CTL() & FAST) |
+			(min(len, 0xff) << 6) | MEN |
+			((msg.flags & I2C_M_READ) ? MDIR : 0)
+	);
+	SSYNC();
+	debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL());
+
+	/* process the rest */
+	ret = wait_for_completion(&msg);
+	debugi("ret=%d", ret);
+
+	if (ret) {
+		bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN);
+		bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
+		SSYNC();
+		bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
+		SSYNC();
+	}
+
+	return ret;
+}
+
+/*
+ * i2c_init - initialize the i2c bus
+ *	@speed: bus speed (in HZ)
+ *	@slaveaddr: address of device in slave mode (0 - not slave)
+ *
+ *	Slave mode isn't actually implemented.  It'll stay that way until
+ *	we get a real request for it.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+	uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
+
+	/* Set TWI internal clock as 10MHz */
+	bfin_write_TWI_CONTROL(prescale);
+
+	/* Set TWI interface clock as specified */
+	bfin_write_TWI_CLKDIV(
+		((5 * 1024 / (speed / 1000)) << 8) |
+		((5 * 1024 / (speed / 1000)) & 0xFF)
+	);
+
+	/* Don't turn it on */
+	bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
+
+	/* But enable it */
+	bfin_write_TWI_CONTROL(TWI_ENA | prescale);
+	SSYNC();
+
+	debugi("CONTROL:0x%04x CLKDIV:0x%04x",
+		bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV());
+
+#if CONFIG_SYS_I2C_SLAVE
+# error I2C slave support not tested/supported
+	/* If they want us as a slave, do it */
+	if (slaveaddr) {
+		bfin_write_TWI_SLAVE_ADDR(slaveaddr);
+		bfin_write_TWI_SLAVE_CTL(SEN);
+	}
+#endif
+}
+
+/**
+ * i2c_probe - test if a chip exists at a given i2c address
+ *	@chip: i2c chip addr to search for
+ *	@return: 0 if found, non-0 if not found
+ */
+int i2c_probe(uchar chip)
+{
+	u8 byte;
+	return i2c_read(chip, 0, 0, &byte, 1);
+}
+
+/**
+ * i2c_read - read data from an i2c device
+ *	@chip: i2c chip addr
+ *	@addr: memory (register) address in the chip
+ *	@alen: byte size of address
+ *	@buffer: buffer to store data read from chip
+ *	@len: how many bytes to read
+ *	@return: 0 on success, non-0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
+}
+
+/**
+ * i2c_write - write data to an i2c device
+ *	@chip: i2c chip addr
+ *	@addr: memory (register) address in the chip
+ *	@alen: byte size of address
+ *	@buffer: buffer to store data read from chip
+ *	@len: how many bytes to write
+ *	@return: 0 on success, non-0 on failure
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	return i2c_transfer(chip, addr, alen, buffer, len, 0);
+}
@@ -198,7 +198,7 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
  
 #define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SLAVE		0
  
 #define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
  
@@ -300,7 +300,7 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
  
 #define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SLAVE		0
 #endif /* CONFIG_SOFT_I2C */
  
 /*
@@ -305,13 +305,11 @@
  
 /*
  * I2C settings
- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
  */
-/* #define CONFIG_SOFT_I2C	1*/	/* I2C bit-banged */
-#define CONFIG_HARD_I2C		1	/* I2C TWI */
-#if defined CONFIG_HARD_I2C
-#define CONFIG_TWICLK_KHZ	50
-#endif
+#define CONFIG_HARD_I2C		1
+#define CONFIG_BFIN_TWI_I2C	1
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0
  
 #define CONFIG_EBIU_SDRRC_VAL  0x306
 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d
@@ -320,39 +318,6 @@
 #define CONFIG_EBIU_AMGCTL_VAL		0xFF
 #define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
 #define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
-
-#if defined CONFIG_SOFT_I2C
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL			PF0
-#define PF_SDA			PF1
-
-#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)		if(bit) { \
-					*pFIO_FLAG_S = PF_SDA; \
-					asm("ssync;"); \
-					} \
-				else    { \
-					*pFIO_FLAG_C = PF_SDA; \
-					asm("ssync;"); \
-					}
-#define I2C_SCL(bit)		if(bit) { \
-					*pFIO_FLAG_S = PF_SCL; \
-					asm("ssync;"); \
-					} \
-				else    { \
-					*pFIO_FLAG_C = PF_SCL; \
-					asm("ssync;"); \
-					}
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif
-
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0xFE
  
 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
 /* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
...	...	@@ -17,7 +17,7 @@
17	17	CEXTRA := initcode.o
18	18	SEXTRA := start.o
19	19	SOBJS := interrupt.o cache.o
20		-COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
	20	+COBJS := cpu.o traps.o interrupts.o reset.o serial.o watchdog.o
21	21
22	22	ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
23	23	COBJS += initcode.o
1		-/*
2		- * i2c.c - driver for Blackfin on-chip TWI/I2C
3		- *
4		- * Copyright (c) 2006-2008 Analog Devices Inc.
5		- *
6		- * Licensed under the GPL-2 or later.
7		- */
8		-
9		-#include <common.h>
10		-
11		-#ifdef CONFIG_HARD_I2C
12		-
13		-#include <asm/blackfin.h>
14		-#include <i2c.h>
15		-#include <asm/io.h>
16		-#include <asm/mach-common/bits/twi.h>
17		-
18		-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
19		-#ifdef TWI0_CLKDIV
20		-#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV()
21		-#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
22		-#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL()
23		-#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
24		-#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL()
25		-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val)
26		-#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT()
27		-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val)
28		-#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR()
29		-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val)
30		-#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
31		-#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
32		-#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
33		-#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
34		-#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR()
35		-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
36		-#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
37		-#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
38		-#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK()
39		-#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
40		-#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL()
41		-#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
42		-#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT()
43		-#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val)
44		-#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8()
45		-#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
46		-#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16()
47		-#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val)
48		-#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
49		-#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val)
50		-#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16()
51		-#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val)
52		-#endif
53		-
54		-#ifdef DEBUG_I2C
55		-#define PRINTD(fmt,args...) do { \
56		- DECLARE_GLOBAL_DATA_PTR; \
57		- if (gd->have_console) \
58		- printf(fmt ,##args); \
59		- } while (0)
60		-#else
61		-#define PRINTD(fmt,args...)
62		-#endif
63		-
64		-#ifndef CONFIG_TWICLK_KHZ
65		-#define CONFIG_TWICLK_KHZ 50
66		-#endif
67		-
68		-/* All transfers are described by this data structure */
69		-struct i2c_msg {
70		- u16 addr; /* slave address */
71		- u16 flags;
72		-#define I2C_M_STOP 0x2
73		-#define I2C_M_RD 0x1
74		- u16 len; /* msg length */
75		- u8 buf; / pointer to msg data */
76		-};
77		-
78		-/**
79		- * i2c_reset: - reset the host controller
80		- */
81		-static void i2c_reset(void)
82		-{
83		- /* Disable TWI */
84		- bfin_write_TWI_CONTROL(0);
85		- SSYNC();
86		-
87		- /* Set TWI internal clock as 10MHz */
88		- bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
89		-
90		- /* Set Twi interface clock as specified */
91		- if (CONFIG_TWICLK_KHZ > 400)
92		- bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) \| ((5 * 1024 /
93		- 400) & 0xFF));
94		- else
95		- bfin_write_TWI_CLKDIV(((5 * 1024 /
96		- CONFIG_TWICLK_KHZ) << 8) \| ((5 * 1024 /
97		- CONFIG_TWICLK_KHZ)
98		- & 0xFF));
99		-
100		- /* Enable TWI */
101		- bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() \| TWI_ENA);
102		- SSYNC();
103		-}
104		-
105		-int wait_for_completion(struct i2c_msg *msg, int timeout_count)
106		-{
107		- unsigned short twi_int_stat;
108		- unsigned short mast_stat;
109		- int i;
110		-
111		- for (i = 0; i < timeout_count; i++) {
112		- twi_int_stat = bfin_read_TWI_INT_STAT();
113		- mast_stat = bfin_read_TWI_MASTER_STAT();
114		-
115		- if (XMTSERV & twi_int_stat) {
116		- /* Transmit next data */
117		- if (msg->len > 0) {
118		- bfin_write_TWI_XMT_DATA8(*(msg->buf++));
119		- msg->len--;
120		- } else if (msg->flags & I2C_M_STOP)
121		- bfin_write_TWI_MASTER_CTL
122		- (bfin_read_TWI_MASTER_CTL() \| STOP);
123		- SSYNC();
124		- /* Clear status */
125		- bfin_write_TWI_INT_STAT(XMTSERV);
126		- SSYNC();
127		- i = 0;
128		- }
129		- if (RCVSERV & twi_int_stat) {
130		- if (msg->len > 0) {
131		- /* Receive next data */
132		- *(msg->buf++) = bfin_read_TWI_RCV_DATA8();
133		- msg->len--;
134		- } else if (msg->flags & I2C_M_STOP) {
135		- bfin_write_TWI_MASTER_CTL
136		- (bfin_read_TWI_MASTER_CTL() \| STOP);
137		- SSYNC();
138		- }
139		- /* Clear interrupt source */
140		- bfin_write_TWI_INT_STAT(RCVSERV);
141		- SSYNC();
142		- i = 0;
143		- }
144		- if (MERR & twi_int_stat) {
145		- bfin_write_TWI_INT_STAT(MERR);
146		- bfin_write_TWI_INT_MASK(0);
147		- bfin_write_TWI_MASTER_STAT(0x3e);
148		- bfin_write_TWI_MASTER_CTL(0);
149		- SSYNC();
150		- /*
151		- * if both err and complete int stats are set,
152		- * return proper results.
153		- */
154		- if (MCOMP & twi_int_stat) {
155		- bfin_write_TWI_INT_STAT(MCOMP);
156		- bfin_write_TWI_INT_MASK(0);
157		- bfin_write_TWI_MASTER_CTL(0);
158		- SSYNC();
159		- /*
160		- * If it is a quick transfer,
161		- * only address bug no data, not an err.
162		- */
163		- if (msg->len == 0 && mast_stat & BUFRDERR)
164		- return 0;
165		- /*
166		- * If address not acknowledged return -3,
167		- * else return 0.
168		- */
169		- else if (!(mast_stat & ANAK))
170		- return 0;
171		- else
172		- return -3;
173		- }
174		- return -1;
175		- }
176		- if (MCOMP & twi_int_stat) {
177		- bfin_write_TWI_INT_STAT(MCOMP);
178		- SSYNC();
179		- bfin_write_TWI_INT_MASK(0);
180		- bfin_write_TWI_MASTER_CTL(0);
181		- SSYNC();
182		- return 0;
183		- }
184		- }
185		- if (msg->flags & I2C_M_RD)
186		- return -4;
187		- else
188		- return -2;
189		-}
190		-
191		-/**
192		- * i2c_transfer: - Transfer one byte over the i2c bus
193		- *
194		- * This function can tranfer a byte over the i2c bus in both directions.
195		- * It is used by the public API functions.
196		- *
197		- * @return: 0: transfer successful
198		- * -1: transfer fail
199		- * -2: transmit timeout
200		- * -3: ACK missing
201		- * -4: receive timeout
202		- * -5: controller not ready
203		- */
204		-int i2c_transfer(struct i2c_msg *msg)
205		-{
206		- int ret = 0;
207		- int timeout_count = 10000;
208		- int len = msg->len;
209		-
210		- if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
211		- ret = -5;
212		- goto transfer_error;
213		- }
214		-
215		- while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
216		- continue;
217		-
218		- /* Set Transmit device address */
219		- bfin_write_TWI_MASTER_ADDR(msg->addr);
220		-
221		- /*
222		- * FIFO Initiation.
223		- * Data in FIFO should be discarded before start a new operation.
224		- */
225		- bfin_write_TWI_FIFO_CTL(0x3);
226		- SSYNC();
227		- bfin_write_TWI_FIFO_CTL(0);
228		- SSYNC();
229		-
230		- if (!(msg->flags & I2C_M_RD)) {
231		- /* Transmit first data */
232		- if (msg->len > 0) {
233		- PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
234		- len);
235		- bfin_write_TWI_XMT_DATA8(*(msg->buf++));
236		- msg->len--;
237		- SSYNC();
238		- }
239		- }
240		-
241		- /* clear int stat */
242		- bfin_write_TWI_INT_STAT(MERR \| MCOMP \| XMTSERV \| RCVSERV);
243		-
244		- /* Interrupt mask . Enable XMT, RCV interrupt */
245		- bfin_write_TWI_INT_MASK(MCOMP \| MERR \|
246		- ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
247		- SSYNC();
248		-
249		- if (len > 0 && len <= 255)
250		- bfin_write_TWI_MASTER_CTL((len << 6));
251		- else if (msg->len > 255) {
252		- bfin_write_TWI_MASTER_CTL((0xff << 6));
253		- msg->flags &= I2C_M_STOP;
254		- } else
255		- bfin_write_TWI_MASTER_CTL(0);
256		-
257		- /* Master enable */
258		- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() \| MEN \|
259		- ((msg->flags & I2C_M_RD)
260		- ? MDIR : 0) \| ((CONFIG_TWICLK_KHZ >
261		- 100) ? FAST : 0));
262		- SSYNC();
263		-
264		- ret = wait_for_completion(msg, timeout_count);
265		- PRINTD("3 in i2c_transfer: ret=%d\n", ret);
266		-
267		- transfer_error:
268		- switch (ret) {
269		- case 1:
270		- PRINTD(("i2c_transfer: error: transfer fail\n"));
271		- break;
272		- case 2:
273		- PRINTD(("i2c_transfer: error: transmit timeout\n"));
274		- break;
275		- case 3:
276		- PRINTD(("i2c_transfer: error: ACK missing\n"));
277		- break;
278		- case 4:
279		- PRINTD(("i2c_transfer: error: receive timeout\n"));
280		- break;
281		- case 5:
282		- PRINTD(("i2c_transfer: error: controller not ready\n"));
283		- i2c_reset();
284		- break;
285		- default:
286		- break;
287		- }
288		- return ret;
289		-
290		-}
291		-
292		-/* ---------------------------------------------------------------------*/
293		-/* API Functions */
294		-/* ---------------------------------------------------------------------*/
295		-
296		-void i2c_init(int speed, int slaveaddr)
297		-{
298		- i2c_reset();
299		-}
300		-
301		-/**
302		- * i2c_probe: - Test if a chip answers for a given i2c address
303		- *
304		- * @chip: address of the chip which is searched for
305		- * @return: 0 if a chip was found, -1 otherwhise
306		- */
307		-
308		-int i2c_probe(uchar chip)
309		-{
310		- struct i2c_msg msg;
311		- u8 probebuf;
312		-
313		- i2c_reset();
314		-
315		- probebuf = 0;
316		- msg.addr = chip;
317		- msg.flags = 0;
318		- msg.len = 1;
319		- msg.buf = &probebuf;
320		- if (i2c_transfer(&msg))
321		- return -1;
322		-
323		- msg.addr = chip;
324		- msg.flags = I2C_M_RD;
325		- msg.len = 1;
326		- msg.buf = &probebuf;
327		- if (i2c_transfer(&msg))
328		- return -1;
329		-
330		- return 0;
331		-}
332		-
333		-/**
334		- * i2c_read: - Read multiple bytes from an i2c device
335		- *
336		- * chip: I2C chip address, range 0..127
337		- * addr: Memory (register) address within the chip
338		- * alen: Number of bytes to use for addr (typically 1, 2 for larger
339		- * memories, 0 for register type devices with only one
340		- * register)
341		- * buffer: Where to read/write the data
342		- * len: How many bytes to read/write
343		- *
344		- * Returns: 0 on success, not 0 on failure
345		- */
346		-
347		-int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
348		-{
349		- struct i2c_msg msg;
350		- u8 addr_bytes[3]; /* lowest...highest byte of data address */
351		-
352		- PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
353		- addr, alen, len);
354		-
355		- if (alen > 0) {
356		- addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
357		- addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
358		- addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
359		- msg.addr = chip;
360		- msg.flags = 0;
361		- msg.len = alen;
362		- msg.buf = addr_bytes;
363		- if (i2c_transfer(&msg))
364		- return -1;
365		- }
366		-
367		- /* start read sequence */
368		- PRINTD(("i2c_read: start read sequence\n"));
369		- msg.addr = chip;
370		- msg.flags = I2C_M_RD;
371		- msg.len = len;
372		- msg.buf = buffer;
373		- if (i2c_transfer(&msg))
374		- return -1;
375		-
376		- return 0;
377		-}
378		-
379		-/**
380		- * i2c_write: - Write multiple bytes to an i2c device
381		- *
382		- * chip: I2C chip address, range 0..127
383		- * addr: Memory (register) address within the chip
384		- * alen: Number of bytes to use for addr (typically 1, 2 for larger
385		- * memories, 0 for register type devices with only one
386		- * register)
387		- * buffer: Where to read/write the data
388		- * len: How many bytes to read/write
389		- *
390		- * Returns: 0 on success, not 0 on failure
391		- */
392		-
393		-int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
394		-{
395		- struct i2c_msg msg;
396		- u8 addr_bytes[3]; /* lowest...highest byte of data address */
397		-
398		- PRINTD
399		- ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
400		- chip, addr, alen, len, buffer[0]);
401		-
402		- /* chip address write */
403		- if (alen > 0) {
404		- addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
405		- addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
406		- addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
407		- msg.addr = chip;
408		- msg.flags = 0;
409		- msg.len = alen;
410		- msg.buf = addr_bytes;
411		- if (i2c_transfer(&msg))
412		- return -1;
413		- }
414		-
415		- /* start read sequence */
416		- PRINTD(("i2c_write: start write sequence\n"));
417		- msg.addr = chip;
418		- msg.flags = 0;
419		- msg.len = len;
420		- msg.buf = buffer;
421		- if (i2c_transfer(&msg))
422		- return -1;
423		-
424		- return 0;
425		-
426		-}
427		-
428		-#endif /* CONFIG_HARD_I2C */
...	...	@@ -25,6 +25,7 @@
25	25
26	26	LIB := $(obj)libi2c.a
27	27
	28	+COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
28	29	COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
29	30	COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
30	31	COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
	1	+/*
	2	+ * i2c.c - driver for Blackfin on-chip TWI/I2C
	3	+ *
	4	+ * Copyright (c) 2006-2008 Analog Devices Inc.
	5	+ *
	6	+ * Licensed under the GPL-2 or later.
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <i2c.h>
	11	+
	12	+#include <asm/blackfin.h>
	13	+#include <asm/mach-common/bits/twi.h>
	14	+
	15	+#ifdef DEBUG
	16	+# define dmemset(s, c, n) memset(s, c, n)
	17	+#else
	18	+# define dmemset(s, c, n)
	19	+#endif
	20	+#define debugi(fmt, args...) \
	21	+ debug( \
	22	+ "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \
	23	+ "%-20s:%-3i: " fmt "\n", \
	24	+ bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
	25	+ __func__, __LINE__, ## args)
	26	+
	27	+#ifdef TWI0_CLKDIV
	28	+#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
	29	+#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
	30	+#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val)
	31	+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
	32	+#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
	33	+#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
	34	+#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
	35	+#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
	36	+#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
	37	+#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
	38	+#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
	39	+#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
	40	+#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
	41	+#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
	42	+#endif
	43	+
	44	+#ifdef CONFIG_TWICLK_KHZ
	45	+# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
	46	+#endif
	47	+#if CONFIG_SYS_I2C_SPEED > 400000
	48	+# error The Blackfin I2C hardware can only operate at 400KHz max
	49	+#endif
	50	+
	51	+/* All transfers are described by this data structure */
	52	+struct i2c_msg {
	53	+ u8 flags;
	54	+#define I2C_M_COMBO 0x4
	55	+#define I2C_M_STOP 0x2
	56	+#define I2C_M_READ 0x1
	57	+ int len; /* msg length */
	58	+ u8 buf; / pointer to msg data */
	59	+ int alen; /* addr length */
	60	+ u8 abuf; / addr buffer */
	61	+};
	62	+
	63	+/**
	64	+ * wait_for_completion - manage the actual i2c transfer
	65	+ * @msg: the i2c msg
	66	+ */
	67	+static int wait_for_completion(struct i2c_msg *msg)
	68	+{
	69	+ uint16_t int_stat;
	70	+
	71	+ while (!ctrlc()) {
	72	+ int_stat = bfin_read_TWI_INT_STAT();
	73	+
	74	+ if (int_stat & XMTSERV) {
	75	+ debugi("processing XMTSERV");
	76	+ bfin_write_TWI_INT_STAT(XMTSERV);
	77	+ SSYNC();
	78	+ if (msg->alen) {
	79	+ bfin_write_TWI_XMT_DATA8(*(msg->abuf++));
	80	+ --msg->alen;
	81	+ } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
	82	+ bfin_write_TWI_XMT_DATA8(*(msg->buf++));
	83	+ --msg->len;
	84	+ } else {
	85	+ bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() \|
	86	+ (msg->flags & I2C_M_COMBO ? RSTART \| MDIR : STOP));
	87	+ SSYNC();
	88	+ }
	89	+ }
	90	+ if (int_stat & RCVSERV) {
	91	+ debugi("processing RCVSERV");
	92	+ bfin_write_TWI_INT_STAT(RCVSERV);
	93	+ SSYNC();
	94	+ if (msg->len) {
	95	+ *(msg->buf++) = bfin_read_TWI_RCV_DATA8();
	96	+ --msg->len;
	97	+ } else if (msg->flags & I2C_M_STOP) {
	98	+ bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() \| STOP);
	99	+ SSYNC();
	100	+ }
	101	+ }
	102	+ if (int_stat & MERR) {
	103	+ debugi("processing MERR");
	104	+ bfin_write_TWI_INT_STAT(MERR);
	105	+ SSYNC();
	106	+ break;
	107	+ }
	108	+ if (int_stat & MCOMP) {
	109	+ debugi("processing MCOMP");
	110	+ bfin_write_TWI_INT_STAT(MCOMP);
	111	+ SSYNC();
	112	+ if (msg->flags & I2C_M_COMBO && msg->len) {
	113	+ bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) \|
	114	+ (min(msg->len, 0xff) << 6) \| MEN \| MDIR);
	115	+ SSYNC();
	116	+ } else
	117	+ break;
	118	+ }
	119	+ }
	120	+
	121	+ return msg->len;
	122	+}
	123	+
	124	+/**
	125	+ * i2c_transfer - setup an i2c transfer
	126	+ * @return: 0 if things worked, non-0 if things failed
	127	+ *
	128	+ * Here we just get the i2c stuff all prepped and ready, and then tail off
	129	+ * into wait_for_completion() for all the bits to go.
	130	+ */
	131	+static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
	132	+{
	133	+ uchar addr_buffer[] = {
	134	+ (addr >> 0),
	135	+ (addr >> 8),
	136	+ (addr >> 16),
	137	+ };
	138	+ struct i2c_msg msg = {
	139	+ .flags = flags \| (len >= 0xff ? I2C_M_STOP : 0),
	140	+ .buf = buffer,
	141	+ .len = len,
	142	+ .abuf = addr_buffer,
	143	+ .alen = alen,
	144	+ };
	145	+ int ret;
	146	+
	147	+ dmemset(buffer, 0xff, len);
	148	+ debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
	149	+ chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
	150	+
	151	+ /* wait for things to settle */
	152	+ while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
	153	+ if (ctrlc())
	154	+ return 1;
	155	+
	156	+ /* Set Transmit device address */
	157	+ bfin_write_TWI_MASTER_ADDR(chip);
	158	+
	159	+ /* Clear the FIFO before starting things */
	160	+ bfin_write_TWI_FIFO_CTL(XMTFLUSH \| RCVFLUSH);
	161	+ SSYNC();
	162	+ bfin_write_TWI_FIFO_CTL(0);
	163	+ SSYNC();
	164	+
	165	+ /* prime the pump */
	166	+ if (msg.alen) {
	167	+ len = msg.alen;
	168	+ debugi("first byte=0x%02x", *msg.abuf);
	169	+ bfin_write_TWI_XMT_DATA8(*(msg.abuf++));
	170	+ --msg.alen;
	171	+ } else if (!(msg.flags & I2C_M_READ) && msg.len) {
	172	+ debugi("first byte=0x%02x", *msg.buf);
	173	+ bfin_write_TWI_XMT_DATA8(*(msg.buf++));
	174	+ --msg.len;
	175	+ }
	176	+
	177	+ /* clear int stat */
	178	+ bfin_write_TWI_MASTER_STAT(-1);
	179	+ bfin_write_TWI_INT_STAT(-1);
	180	+ bfin_write_TWI_INT_MASK(0);
	181	+ SSYNC();
	182	+
	183	+ /* Master enable */
	184	+ bfin_write_TWI_MASTER_CTL(
	185	+ (bfin_read_TWI_MASTER_CTL() & FAST) \|
	186	+ (min(len, 0xff) << 6) \| MEN \|
	187	+ ((msg.flags & I2C_M_READ) ? MDIR : 0)
	188	+ );
	189	+ SSYNC();
	190	+ debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL());
	191	+
	192	+ /* process the rest */
	193	+ ret = wait_for_completion(&msg);
	194	+ debugi("ret=%d", ret);
	195	+
	196	+ if (ret) {
	197	+ bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN);
	198	+ bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
	199	+ SSYNC();
	200	+ bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() \| TWI_ENA);
	201	+ SSYNC();
	202	+ }
	203	+
	204	+ return ret;
	205	+}
	206	+
	207	+/*
	208	+ * i2c_init - initialize the i2c bus
	209	+ * @speed: bus speed (in HZ)
	210	+ * @slaveaddr: address of device in slave mode (0 - not slave)
	211	+ *
	212	+ * Slave mode isn't actually implemented. It'll stay that way until
	213	+ * we get a real request for it.
	214	+ */
	215	+void i2c_init(int speed, int slaveaddr)
	216	+{
	217	+ uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
	218	+
	219	+ /* Set TWI internal clock as 10MHz */
	220	+ bfin_write_TWI_CONTROL(prescale);
	221	+
	222	+ /* Set TWI interface clock as specified */
	223	+ bfin_write_TWI_CLKDIV(
	224	+ ((5 * 1024 / (speed / 1000)) << 8) \|
	225	+ ((5 * 1024 / (speed / 1000)) & 0xFF)
	226	+ );
	227	+
	228	+ /* Don't turn it on */
	229	+ bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
	230	+
	231	+ /* But enable it */
	232	+ bfin_write_TWI_CONTROL(TWI_ENA \| prescale);
	233	+ SSYNC();
	234	+
	235	+ debugi("CONTROL:0x%04x CLKDIV:0x%04x",
	236	+ bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV());
	237	+
	238	+#if CONFIG_SYS_I2C_SLAVE
	239	+# error I2C slave support not tested/supported
	240	+ /* If they want us as a slave, do it */
	241	+ if (slaveaddr) {
	242	+ bfin_write_TWI_SLAVE_ADDR(slaveaddr);
	243	+ bfin_write_TWI_SLAVE_CTL(SEN);
	244	+ }
	245	+#endif
	246	+}
	247	+
	248	+/**
	249	+ * i2c_probe - test if a chip exists at a given i2c address
	250	+ * @chip: i2c chip addr to search for
	251	+ * @return: 0 if found, non-0 if not found
	252	+ */
	253	+int i2c_probe(uchar chip)
	254	+{
	255	+ u8 byte;
	256	+ return i2c_read(chip, 0, 0, &byte, 1);
	257	+}
	258	+
	259	+/**
	260	+ * i2c_read - read data from an i2c device
	261	+ * @chip: i2c chip addr
	262	+ * @addr: memory (register) address in the chip
	263	+ * @alen: byte size of address
	264	+ * @buffer: buffer to store data read from chip
	265	+ * @len: how many bytes to read
	266	+ * @return: 0 on success, non-0 on failure
	267	+ */
	268	+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
	269	+{
	270	+ return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
	271	+}
	272	+
	273	+/**
	274	+ * i2c_write - write data to an i2c device
	275	+ * @chip: i2c chip addr
	276	+ * @addr: memory (register) address in the chip
	277	+ * @alen: byte size of address
	278	+ * @buffer: buffer to store data read from chip
	279	+ * @len: how many bytes to write
	280	+ * @return: 0 on success, non-0 on failure
	281	+ */
	282	+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
	283	+{
	284	+ return i2c_transfer(chip, addr, alen, buffer, len, 0);
	285	+}
...	...	@@ -198,7 +198,7 @@
198	198	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
199	199
200	200	#define CONFIG_SYS_I2C_SPEED 50000
201		-#define CONFIG_SYS_I2C_SLAVE 0xFE
	201	+#define CONFIG_SYS_I2C_SLAVE 0
202	202
203	203	#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
204	204
...	...	@@ -300,7 +300,7 @@
300	300	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
301	301
302	302	#define CONFIG_SYS_I2C_SPEED 50000
303		-#define CONFIG_SYS_I2C_SLAVE 0xFE
	303	+#define CONFIG_SYS_I2C_SLAVE 0
304	304	#endif /* CONFIG_SOFT_I2C */
305	305
306	306	/*
...	...	@@ -305,13 +305,11 @@
305	305
306	306	/*
307	307	* I2C settings
308		- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
309	308	*/
310		-/* #define CONFIG_SOFT_I2C 1/ / I2C bit-banged */
311		-#define CONFIG_HARD_I2C 1 /* I2C TWI */
312		-#if defined CONFIG_HARD_I2C
313		-#define CONFIG_TWICLK_KHZ 50
314		-#endif
	309	+#define CONFIG_HARD_I2C 1
	310	+#define CONFIG_BFIN_TWI_I2C 1
	311	+#define CFG_I2C_SPEED 50000
	312	+#define CFG_I2C_SLAVE 0
315	313
316	314	#define CONFIG_EBIU_SDRRC_VAL 0x306
317	315	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
...	...	@@ -320,39 +318,6 @@
320	318	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
321	319	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
322	320	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
323		-
324		-#if defined CONFIG_SOFT_I2C
325		-/*
326		- * Software (bit-bang) I2C driver configuration
327		- */
328		-#define PF_SCL PF0
329		-#define PF_SDA PF1
330		-
331		-#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
332		-#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
333		-#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
334		-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
335		-#define I2C_SDA(bit) if(bit) { \
336		- *pFIO_FLAG_S = PF_SDA; \
337		- asm("ssync;"); \
338		- } \
339		- else { \
340		- *pFIO_FLAG_C = PF_SDA; \
341		- asm("ssync;"); \
342		- }
343		-#define I2C_SCL(bit) if(bit) { \
344		- *pFIO_FLAG_S = PF_SCL; \
345		- asm("ssync;"); \
346		- } \
347		- else { \
348		- *pFIO_FLAG_C = PF_SCL; \
349		- asm("ssync;"); \
350		- }
351		-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
352		-#endif
353		-
354		-#define CONFIG_SYS_I2C_SPEED 50000
355		-#define CONFIG_SYS_I2C_SLAVE 0xFE
356	321
357	322	/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
358	323	/* #define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)