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Commit bead08800a2f054a90849e0c244022013fbe0196

Authored by shaohui xie
Committed by Joe Hershberger
1 parent cebf3f558e
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

net: fman: fix 2.5G SGMII settings 

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 3 changed files with 25 additions and 10 deletions Side-by-side Diff

drivers/net/fm/eth.c
Diff comments   View file @ bead088
... ... @@ -45,9 +45,12 @@
45 45  
46 46 qsgmii_loop:
47 47 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
48   - value = PHY_SGMII_IF_MODE_SGMII;
49   - if (!sgmii_2500)
50   - value |= PHY_SGMII_IF_MODE_AN;
  48 + if (sgmii_2500)
  49 + value = PHY_SGMII_CR_PHY_RESET |
  50 + PHY_SGMII_IF_SPEED_GIGABIT |
  51 + PHY_SGMII_IF_MODE_SGMII;
  52 + else
  53 + value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
51 54  
52 55 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
53 56  
54 57  
... ... @@ -55,15 +58,24 @@
55 58 value = PHY_SGMII_DEV_ABILITY_SGMII;
56 59 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
57 60  
58   - /* Adjust link timer for SGMII -
59   - 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
60   - memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
61   - memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
  61 + if (sgmii_2500) {
  62 + /* Adjust link timer for 2.5G SGMII,
  63 + * 1.6 ms in units of 3.2 ns:
  64 + * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
  65 + */
  66 + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
  67 + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
  68 + } else {
  69 + /* Adjust link timer for SGMII,
  70 + * 1.6 ms in units of 8 ns:
  71 + * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
  72 + */
  73 + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
  74 + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
  75 + }
62 76  
63 77 /* Restart AN */
64   - value = PHY_SGMII_CR_DEF_VAL;
65   - if (!sgmii_2500)
66   - value |= PHY_SGMII_CR_RESET_AN;
  78 + value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
67 79 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
68 80  
69 81 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
... ... @@ -391,6 +403,7 @@
391 403  
392 404 /* For some reason we need to set SPEED_100 */
393 405 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
  406 + (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
394 407 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
395 408 mac->set_if_mode)
396 409 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
drivers/net/fm/memac.c
Diff comments   View file @ bead088
... ... @@ -90,6 +90,7 @@
90 90 if_mode |= (IF_MODE_GMII | IF_MODE_RM);
91 91 break;
92 92 case PHY_INTERFACE_MODE_SGMII:
  93 + case PHY_INTERFACE_MODE_SGMII_2500:
93 94 case PHY_INTERFACE_MODE_QSGMII:
94 95 if_mode &= ~IF_MODE_MASK;
95 96 if_mode |= (IF_MODE_GMII);
... ... @@ -226,6 +226,7 @@
226 226 #define PHY_SGMII_CR_PHY_RESET 0x8000
227 227 #define PHY_SGMII_CR_RESET_AN 0x0200
228 228 #define PHY_SGMII_CR_DEF_VAL 0x1140
  229 +#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
229 230 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
230 231 #define PHY_SGMII_IF_MODE_AN 0x0002
231 232 #define PHY_SGMII_IF_MODE_SGMII 0x0001