x86: Use CONFIG_SERIAL_MULTI

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

x86: Use CONFIG_SERIAL_MULTI
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Graeme Russ · Wolfgang Denk
1 parent 167cdad137
Showing 7 changed files with 32 additions and 516 deletions Side-by-side Diff
arch/i386/cpu/Makefile
arch/i386/cpu/serial.c
arch/i386/lib/board.c
board/eNET/eNET.c
common/serial.c
include/configs/eNET.h
include/serial.h
@@ -29,7 +29,7 @@
 LIB	= $(obj)lib$(CPU).a
  
 START	= start.o start16.o resetvec.o
-COBJS	= serial.o interrupts.o cpu.o
+COBJS	= interrupts.o cpu.o
  
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/*------------------------------------------------------------------------------+ */
-
-/*
- * This source code is dual-licensed.  You may use it under the terms of the
- * GNU General Public License version 2, or under the license below.
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis.  Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications.  No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT   I B M   CORPORATION 1995
- * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- */
-/*------------------------------------------------------------------------------- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <asm/ibmpc.h>
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-#include <malloc.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_RBR    0x00
-#define UART_THR    0x00
-#define UART_IER    0x01
-#define UART_IIR    0x02
-#define UART_FCR    0x02
-#define UART_LCR    0x03
-#define UART_MCR    0x04
-#define UART_LSR    0x05
-#define UART_MSR    0x06
-#define UART_SCR    0x07
-#define UART_DLL    0x00
-#define UART_DLM    0x01
-
-/*-----------------------------------------------------------------------------+
-  | Line Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncLSRDataReady1            0x01
-#define asyncLSROverrunError1         0x02
-#define asyncLSRParityError1          0x04
-#define asyncLSRFramingError1         0x08
-#define asyncLSRBreakInterrupt1       0x10
-#define asyncLSRTxHoldEmpty1          0x20
-#define asyncLSRTxShiftEmpty1         0x40
-#define asyncLSRRxFifoError1          0x80
-
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-/*-----------------------------------------------------------------------------+
-  | Fifo
-  +-----------------------------------------------------------------------------*/
-typedef struct {
-	char *rx_buffer;
-	ulong rx_put;
-	ulong rx_get;
-	int cts;
-} serial_buffer_t;
-
-volatile serial_buffer_t buf_info;
-static int serial_buffer_active=0;
-#endif
-
-
-static int serial_div(int baudrate)
-{
-
-	switch (baudrate) {
-	case 1200:
-		return 96;
-	case 9600:
-		return 12;
-	case 19200:
-		return 6;
-	case 38400:
-		return 3;
-	case 57600:
-		return 2;
-	case 115200:
-		return 1;
-	}
-
-	return 12;
-}
-
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-int serial_init(void)
-{
-	volatile char val;
-	int bdiv = serial_div(gd->baudrate);
-
-	outb(0x80, UART0_BASE + UART_LCR);	/* set DLAB bit */
-	outb(bdiv, UART0_BASE + UART_DLL);	/* set baudrate divisor */
-	outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
-	outb(0x03, UART0_BASE + UART_LCR);	/* clear DLAB; set 8 bits, no parity */
-	outb(0x01, UART0_BASE + UART_FCR);	/* enable FIFO */
-	outb(0x0b, UART0_BASE + UART_MCR);	/* Set DTR and RTS active */
-	val = inb(UART0_BASE + UART_LSR);	/* clear line status */
-	val = inb(UART0_BASE + UART_RBR);	/* read receive buffer */
-	outb(0x00, UART0_BASE + UART_SCR);	/* set scratchpad */
-	outb(0x00, UART0_BASE + UART_IER);	/* set interrupt enable reg */
-
-	return 0;
-}
-
-
-void serial_setbrg(void)
-{
-	unsigned short bdiv;
-
-	bdiv = serial_div(gd->baudrate);
-
-	outb(0x80, UART0_BASE + UART_LCR);	/* set DLAB bit */
-	outb(bdiv&0xff, UART0_BASE + UART_DLL);	/* set baudrate divisor */
-	outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
-	outb(0x03, UART0_BASE + UART_LCR);	/* clear DLAB; set 8 bits, no parity */
-}
-
-
-void serial_putc(const char c)
-{
-	int i;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	/* check THRE bit, wait for transmiter available */
-	for (i = 1; i < 3500; i++) {
-		if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) {
-			break;
-		}
-		udelay(100);
-	}
-	outb(c, UART0_BASE + UART_THR);	/* put character out */
-}
-
-
-void serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
-
-int serial_getc(void)
-{
-	unsigned char status = 0;
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-	if (serial_buffer_active) {
-		return serial_buffered_getc();
-	}
-#endif
-
-	while (1) {
-#if defined(CONFIG_HW_WATCHDOG)
-		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
-#endif	/* CONFIG_HW_WATCHDOG */
-		status = inb(UART0_BASE + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError1 |
-				asyncLSROverrunError1 |
-				asyncLSRParityError1  |
-				asyncLSRBreakInterrupt1 )) != 0) {
-			outb(asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
-		}
-	}
-	return (0x000000ff & (int) inb (UART0_BASE));
-}
-
-
-int serial_tstc(void)
-{
-	unsigned char status;
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-	if (serial_buffer_active) {
-		return serial_buffered_tstc();
-	}
-#endif
-
-	status = inb(UART0_BASE + UART_LSR);
-	if ((status & asyncLSRDataReady1) != 0x0) {
-		return (1);
-	}
-	if ((status & ( asyncLSRFramingError1 |
-			asyncLSROverrunError1 |
-			asyncLSRParityError1  |
-			asyncLSRBreakInterrupt1 )) != 0) {
-		outb(asyncLSRFramingError1 |
-		      asyncLSROverrunError1 |
-		      asyncLSRParityError1  |
-		      asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
-	}
-	return 0;
-}
-
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-
-void serial_isr(void *arg)
-{
-	int space;
-	int c;
-	int rx_put = buf_info.rx_put;
-
-	if (buf_info.rx_get <= rx_put) {
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get);
-	} else {
-		space = buf_info.rx_get - rx_put;
-	}
-
-	while (inb(UART0_BASE + UART_LSR) & 1) {
-		c = inb(UART0_BASE);
-		if (space) {
-			buf_info.rx_buffer[rx_put++] = c;
-			space--;
-
-			if (rx_put == buf_info.rx_get) {
-				buf_info.rx_get++;
-				if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
-					buf_info.rx_get = 0;
-				}
-			}
-
-			if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
-				rx_put = 0;
-				if (0 == buf_info.rx_get) {
-					buf_info.rx_get = 1;
-				}
-
-			}
-
-		}
-		if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
-			/* Stop flow by setting RTS inactive */
-			outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02),
-			      UART0_BASE + UART_MCR);
-		}
-	}
-	buf_info.rx_put = rx_put;
-}
-
-void serial_buffered_init(void)
-{
-	serial_puts ("Switching to interrupt driven serial input mode.\n");
-	buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
-	buf_info.rx_put = 0;
-	buf_info.rx_get = 0;
-
-	if (inb (UART0_BASE + UART_MSR) & 0x10) {
-		serial_puts ("Check CTS signal present on serial port: OK.\n");
-		buf_info.cts = 1;
-	} else {
-		serial_puts ("WARNING: CTS signal not present on serial port.\n");
-		buf_info.cts = 0;
-	}
-
-	irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
-			      serial_isr /*interrupt_handler_t *handler */ ,
-			      (void *) &buf_info /*void *arg */ );
-
-	/* Enable "RX Data Available" Interrupt on UART */
-	/* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
-	outb(0x01, UART0_BASE + UART_IER);
-
-	/* Set DTR and RTS active, enable interrupts  */
-	outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
-
-	/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
-	outb( /*(1 << 6) |*/  1, UART0_BASE + UART_FCR);
-
-	serial_buffer_active = 1;
-}
-
-void serial_buffered_putc (const char c)
-{
-	int i;
-	/* Wait for CTS */
-#if defined(CONFIG_HW_WATCHDOG)
-	while (!(inb (UART0_BASE + UART_MSR) & 0x10))
-		WATCHDOG_RESET ();
-#else
-	if (buf_info.cts)  {
-		for (i=0;i<1000;i++) {
-			if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
-				break;
-			}
-		}
-		if (i!=1000) {
-			buf_info.cts = 0;
-		}
-	} else {
-		if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
-			buf_info.cts = 1;
-		}
-	}
-
-#endif
-	serial_putc (c);
-}
-
-void serial_buffered_puts(const char *s)
-{
-	serial_puts (s);
-}
-
-int serial_buffered_getc(void)
-{
-	int space;
-	int c;
-	int rx_get = buf_info.rx_get;
-	int rx_put;
-
-#if defined(CONFIG_HW_WATCHDOG)
-	while (rx_get == buf_info.rx_put)
-		WATCHDOG_RESET ();
-#else
-	while (rx_get == buf_info.rx_put);
-#endif
-	c = buf_info.rx_buffer[rx_get++];
-	if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) {
-		rx_get = 0;
-	}
-	buf_info.rx_get = rx_get;
-
-	rx_put = buf_info.rx_put;
-	if (rx_get <= rx_put) {
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
-	} else {
-		space = rx_get - rx_put;
-	}
-	if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
-		/* Start flow by setting RTS active */
-		outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR);
-	}
-
-	return c;
-}
-
-int serial_buffered_tstc(void)
-{
-	return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
-}
-
-#endif	/* CONFIG_SERIAL_SOFTWARE_FIFO */
-
-
-#if defined(CONFIG_CMD_KGDB)
-/*
-  AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
-  number 0 or number 1
-  - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
-  configuration has been already done
-  - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
-  configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
-*/
-#if (CONFIG_KGDB_SER_INDEX & 2)
-void kgdb_serial_init(void)
-{
-	volatile char val;
-	bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
-
-	/*
-	 * Init onboard 16550 UART
-	 */
-	outb(0x80, UART1_BASE + UART_LCR);	/* set DLAB bit */
-	outb((bdiv & 0xff), UART1_BASE + UART_DLL);	/* set divisor for 9600 baud */
-	outb((bdiv >> 8  ), UART1_BASE + UART_DLM);	/* set divisor for 9600 baud */
-	outb(0x03, UART1_BASE + UART_LCR);	/* line control 8 bits no parity */
-	outb(0x00, UART1_BASE + UART_FCR);	/* disable FIFO */
-	outb(0x00, UART1_BASE + UART_MCR);	/* no modem control DTR RTS */
-	val = inb(UART1_BASE + UART_LSR);	/* clear line status */
-	val = inb(UART1_BASE + UART_RBR);	/* read receive buffer */
-	outb(0x00, UART1_BASE + UART_SCR);	/* set scratchpad */
-	outb(0x00, UART1_BASE + UART_IER);	/* set interrupt enable reg */
-}
-
-
-void putDebugChar(const char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-
-	outb(c, UART1_BASE + UART_THR);	/* put character out */
-
-	/* check THRE bit, wait for transfer done */
-	while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20);
-}
-
-
-void putDebugStr(const char *s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
-
-int getDebugChar(void)
-{
-	unsigned char status = 0;
-
-	while (1) {
-		status = inb(UART1_BASE + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0) {
-			break;
-		}
-		if ((status & ( asyncLSRFramingError1 |
-				asyncLSROverrunError1 |
-				asyncLSRParityError1  |
-				asyncLSRBreakInterrupt1 )) != 0) {
-			outb(asyncLSRFramingError1 |
-			     asyncLSROverrunError1 |
-			     asyncLSRParityError1  |
-			     asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR);
-		}
-	}
-	return (0x000000ff & (int) inb(UART1_BASE));
-}
-
-
-void kgdb_interruptible(int yes)
-{
-	return;
-}
-
-#else	/* ! (CONFIG_KGDB_SER_INDEX & 2) */
-
-void kgdb_serial_init(void)
-{
-	serial_printf ("[on serial] ");
-}
-
-void putDebugChar(int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr(const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar(void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible(int yes)
-{
-	return;
-}
-#endif	/* (CONFIG_KGDB_SER_INDEX & 2) */
-#endif
@@ -37,6 +37,7 @@
 #include <malloc.h>
 #include <net.h>
 #include <ide.h>
+#include <serial.h>
 #include <asm/u-boot-i386.h>
 #include <elf.h>
  
@@ -149,7 +150,6 @@
 typedef int (init_fnc_t) (void);
  
 init_fnc_t *init_sequence[] = {
-	serial_init,
 	cpu_init_r,		/* basic cpu dependent setup */
 	board_early_init_r,	/* basic board dependent setup */
 	dram_init,		/* configure available RAM banks */
@@ -277,6 +277,9 @@
 	}
 	show_boot_progress(0x23);
  
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
 	/* configure available FLASH banks */
 	size = flash_init();
 	display_flash_config(size);
@@ -111,8 +111,9 @@
 	writew(0x0615, &sc520_mmcr->romcs1ctl);
 	writew(0x0615, &sc520_mmcr->romcs2ctl);
  
-	writeb(0x02, &sc520_mmcr->adddecctl);
+	writeb(0x00, &sc520_mmcr->adddecctl);
 	writeb(0x07, &sc520_mmcr->uart1ctl);
+	writeb(0x07, &sc520_mmcr->uart2ctl);
 	writeb(0x06, &sc520_mmcr->sysarbctl);
 	writew(0x0003, &sc520_mmcr->sysarbmenb);
  
@@ -41,7 +41,8 @@
 #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
    || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
    || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
-   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
+   || defined(CONFIG_SYS_SC520)
 #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
 #if (CONFIG_CONS_INDEX==1)
 	return &eserial1_device;
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
  
+#include <asm/ibmpc.h>
 /*
  * board/config.h - configuration options, board specific
  */
@@ -55,6 +56,26 @@
 #undef CONFIG_HW_WATCHDOG
  
  /*-----------------------------------------------------------------------
+  * Serial Configuration
+  */
+#define CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		1843200
+#define CONFIG_BAUDRATE			9600
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		UART1_BASE
+#define CONFIG_SYS_NS16550_COM3		(0x1000 + UART0_BASE)
+#define CONFIG_SYS_NS16550_COM4		(0x1000 + UART1_BASE)
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+ /*-----------------------------------------------------------------------
   * Video Configuration
   */
 #undef CONFIG_VIDEO			/* No Video Hardware */
@@ -65,8 +86,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
  
-#define CONFIG_BAUDRATE		9600
-
 /*-----------------------------------------------------------------------
  * Command line configuration.
  */
@@ -122,9 +141,6 @@
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
  
 #define	CONFIG_SYS_HZ			1024		/* incrementer freq: 1kHz */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
  
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
@@ -26,7 +26,8 @@
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
     defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \
-    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+    defined(CONFIG_SYS_SC520)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
 #if defined(CONFIG_SYS_NS16550_SERIAL)
...	...	@@ -29,7 +29,7 @@
29	29	LIB = $(obj)lib$(CPU).a
30	30
31	31	START = start.o start16.o resetvec.o
32		-COBJS = serial.o interrupts.o cpu.o
	32	+COBJS = interrupts.o cpu.o
33	33
34	34	SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
35	35	OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1		-/*
2		- * (C) Copyright 2002
3		- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
4		- *
5		- * (C) Copyright 2000
6		- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7		- *
8		- * See file CREDITS for list of people who contributed to this
9		- * project.
10		- *
11		- * This program is free software; you can redistribute it and/or
12		- * modify it under the terms of the GNU General Public License as
13		- * published by the Free Software Foundation; either version 2 of
14		- * the License, or (at your option) any later version.
15		- *
16		- * This program is distributed in the hope that it will be useful,
17		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
18		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19		- * GNU General Public License for more details.
20		- *
21		- * You should have received a copy of the GNU General Public License
22		- * along with this program; if not, write to the Free Software
23		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24		- * MA 02111-1307 USA
25		- */
26		-/------------------------------------------------------------------------------+ /
27		-
28		-/*
29		- * This source code is dual-licensed. You may use it under the terms of the
30		- * GNU General Public License version 2, or under the license below.
31		- *
32		- * This source code has been made available to you by IBM on an AS-IS
33		- * basis. Anyone receiving this source is licensed under IBM
34		- * copyrights to use it in any way he or she deems fit, including
35		- * copying it, modifying it, compiling it, and redistributing it either
36		- * with or without modifications. No license under IBM patents or
37		- * patent applications is to be implied by the copyright license.
38		- *
39		- * Any user of this software should understand that IBM cannot provide
40		- * technical support for this software and will not be responsible for
41		- * any consequences resulting from the use of this software.
42		- *
43		- * Any person who transfers this source code or any derivative work
44		- * must include the IBM copyright notice, this paragraph, and the
45		- * preceding two paragraphs in the transferred software.
46		- *
47		- * COPYRIGHT I B M CORPORATION 1995
48		- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
49		- */
50		-/------------------------------------------------------------------------------- /
51		-
52		-#include <common.h>
53		-#include <watchdog.h>
54		-#include <asm/io.h>
55		-#include <asm/ibmpc.h>
56		-
57		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
58		-#include <malloc.h>
59		-#endif
60		-
61		-DECLARE_GLOBAL_DATA_PTR;
62		-
63		-#define UART_RBR 0x00
64		-#define UART_THR 0x00
65		-#define UART_IER 0x01
66		-#define UART_IIR 0x02
67		-#define UART_FCR 0x02
68		-#define UART_LCR 0x03
69		-#define UART_MCR 0x04
70		-#define UART_LSR 0x05
71		-#define UART_MSR 0x06
72		-#define UART_SCR 0x07
73		-#define UART_DLL 0x00
74		-#define UART_DLM 0x01
75		-
76		-/*-----------------------------------------------------------------------------+
77		- \| Line Status Register.
78		- +-----------------------------------------------------------------------------*/
79		-#define asyncLSRDataReady1 0x01
80		-#define asyncLSROverrunError1 0x02
81		-#define asyncLSRParityError1 0x04
82		-#define asyncLSRFramingError1 0x08
83		-#define asyncLSRBreakInterrupt1 0x10
84		-#define asyncLSRTxHoldEmpty1 0x20
85		-#define asyncLSRTxShiftEmpty1 0x40
86		-#define asyncLSRRxFifoError1 0x80
87		-
88		-
89		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
90		-/*-----------------------------------------------------------------------------+
91		- \| Fifo
92		- +-----------------------------------------------------------------------------*/
93		-typedef struct {
94		- char *rx_buffer;
95		- ulong rx_put;
96		- ulong rx_get;
97		- int cts;
98		-} serial_buffer_t;
99		-
100		-volatile serial_buffer_t buf_info;
101		-static int serial_buffer_active=0;
102		-#endif
103		-
104		-
105		-static int serial_div(int baudrate)
106		-{
107		-
108		- switch (baudrate) {
109		- case 1200:
110		- return 96;
111		- case 9600:
112		- return 12;
113		- case 19200:
114		- return 6;
115		- case 38400:
116		- return 3;
117		- case 57600:
118		- return 2;
119		- case 115200:
120		- return 1;
121		- }
122		-
123		- return 12;
124		-}
125		-
126		-
127		-/*
128		- * Minimal serial functions needed to use one of the SMC ports
129		- * as serial console interface.
130		- */
131		-
132		-int serial_init(void)
133		-{
134		- volatile char val;
135		- int bdiv = serial_div(gd->baudrate);
136		-
137		- outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
138		- outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */
139		- outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
140		- outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
141		- outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */
142		- outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */
143		- val = inb(UART0_BASE + UART_LSR); /* clear line status */
144		- val = inb(UART0_BASE + UART_RBR); /* read receive buffer */
145		- outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */
146		- outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */
147		-
148		- return 0;
149		-}
150		-
151		-
152		-void serial_setbrg(void)
153		-{
154		- unsigned short bdiv;
155		-
156		- bdiv = serial_div(gd->baudrate);
157		-
158		- outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
159		- outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */
160		- outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
161		- outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
162		-}
163		-
164		-
165		-void serial_putc(const char c)
166		-{
167		- int i;
168		-
169		- if (c == '\n')
170		- serial_putc ('\r');
171		-
172		- /* check THRE bit, wait for transmiter available */
173		- for (i = 1; i < 3500; i++) {
174		- if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) {
175		- break;
176		- }
177		- udelay(100);
178		- }
179		- outb(c, UART0_BASE + UART_THR); /* put character out */
180		-}
181		-
182		-
183		-void serial_puts(const char *s)
184		-{
185		- while (*s) {
186		- serial_putc(*s++);
187		- }
188		-}
189		-
190		-
191		-int serial_getc(void)
192		-{
193		- unsigned char status = 0;
194		-
195		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
196		- if (serial_buffer_active) {
197		- return serial_buffered_getc();
198		- }
199		-#endif
200		-
201		- while (1) {
202		-#if defined(CONFIG_HW_WATCHDOG)
203		- WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
204		-#endif /* CONFIG_HW_WATCHDOG */
205		- status = inb(UART0_BASE + UART_LSR);
206		- if ((status & asyncLSRDataReady1) != 0x0) {
207		- break;
208		- }
209		- if ((status & ( asyncLSRFramingError1 \|
210		- asyncLSROverrunError1 \|
211		- asyncLSRParityError1 \|
212		- asyncLSRBreakInterrupt1 )) != 0) {
213		- outb(asyncLSRFramingError1 \|
214		- asyncLSROverrunError1 \|
215		- asyncLSRParityError1 \|
216		- asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
217		- }
218		- }
219		- return (0x000000ff & (int) inb (UART0_BASE));
220		-}
221		-
222		-
223		-int serial_tstc(void)
224		-{
225		- unsigned char status;
226		-
227		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
228		- if (serial_buffer_active) {
229		- return serial_buffered_tstc();
230		- }
231		-#endif
232		-
233		- status = inb(UART0_BASE + UART_LSR);
234		- if ((status & asyncLSRDataReady1) != 0x0) {
235		- return (1);
236		- }
237		- if ((status & ( asyncLSRFramingError1 \|
238		- asyncLSROverrunError1 \|
239		- asyncLSRParityError1 \|
240		- asyncLSRBreakInterrupt1 )) != 0) {
241		- outb(asyncLSRFramingError1 \|
242		- asyncLSROverrunError1 \|
243		- asyncLSRParityError1 \|
244		- asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
245		- }
246		- return 0;
247		-}
248		-
249		-
250		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
251		-
252		-void serial_isr(void *arg)
253		-{
254		- int space;
255		- int c;
256		- int rx_put = buf_info.rx_put;
257		-
258		- if (buf_info.rx_get <= rx_put) {
259		- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get);
260		- } else {
261		- space = buf_info.rx_get - rx_put;
262		- }
263		-
264		- while (inb(UART0_BASE + UART_LSR) & 1) {
265		- c = inb(UART0_BASE);
266		- if (space) {
267		- buf_info.rx_buffer[rx_put++] = c;
268		- space--;
269		-
270		- if (rx_put == buf_info.rx_get) {
271		- buf_info.rx_get++;
272		- if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
273		- buf_info.rx_get = 0;
274		- }
275		- }
276		-
277		- if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
278		- rx_put = 0;
279		- if (0 == buf_info.rx_get) {
280		- buf_info.rx_get = 1;
281		- }
282		-
283		- }
284		-
285		- }
286		- if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
287		- /* Stop flow by setting RTS inactive */
288		- outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02),
289		- UART0_BASE + UART_MCR);
290		- }
291		- }
292		- buf_info.rx_put = rx_put;
293		-}
294		-
295		-void serial_buffered_init(void)
296		-{
297		- serial_puts ("Switching to interrupt driven serial input mode.\n");
298		- buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
299		- buf_info.rx_put = 0;
300		- buf_info.rx_get = 0;
301		-
302		- if (inb (UART0_BASE + UART_MSR) & 0x10) {
303		- serial_puts ("Check CTS signal present on serial port: OK.\n");
304		- buf_info.cts = 1;
305		- } else {
306		- serial_puts ("WARNING: CTS signal not present on serial port.\n");
307		- buf_info.cts = 0;
308		- }
309		-
310		- irq_install_handler ( VECNUM_U0 /UART0 / /int vec / ,
311		- serial_isr /interrupt_handler_t handler */ ,
312		- (void ) &buf_info /void arg / );
313		-
314		- /* Enable "RX Data Available" Interrupt on UART */
315		- /* outb(inb(UART0_BASE + UART_IER) \|0x01, UART0_BASE + UART_IER); */
316		- outb(0x01, UART0_BASE + UART_IER);
317		-
318		- /* Set DTR and RTS active, enable interrupts */
319		- outb(inb (UART0_BASE + UART_MCR) \| 0x0b, UART0_BASE + UART_MCR);
320		-
321		- /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
322		- outb( /(1 << 6) \|/ 1, UART0_BASE + UART_FCR);
323		-
324		- serial_buffer_active = 1;
325		-}
326		-
327		-void serial_buffered_putc (const char c)
328		-{
329		- int i;
330		- /* Wait for CTS */
331		-#if defined(CONFIG_HW_WATCHDOG)
332		- while (!(inb (UART0_BASE + UART_MSR) & 0x10))
333		- WATCHDOG_RESET ();
334		-#else
335		- if (buf_info.cts) {
336		- for (i=0;i<1000;i++) {
337		- if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
338		- break;
339		- }
340		- }
341		- if (i!=1000) {
342		- buf_info.cts = 0;
343		- }
344		- } else {
345		- if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
346		- buf_info.cts = 1;
347		- }
348		- }
349		-
350		-#endif
351		- serial_putc (c);
352		-}
353		-
354		-void serial_buffered_puts(const char *s)
355		-{
356		- serial_puts (s);
357		-}
358		-
359		-int serial_buffered_getc(void)
360		-{
361		- int space;
362		- int c;
363		- int rx_get = buf_info.rx_get;
364		- int rx_put;
365		-
366		-#if defined(CONFIG_HW_WATCHDOG)
367		- while (rx_get == buf_info.rx_put)
368		- WATCHDOG_RESET ();
369		-#else
370		- while (rx_get == buf_info.rx_put);
371		-#endif
372		- c = buf_info.rx_buffer[rx_get++];
373		- if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) {
374		- rx_get = 0;
375		- }
376		- buf_info.rx_get = rx_get;
377		-
378		- rx_put = buf_info.rx_put;
379		- if (rx_get <= rx_put) {
380		- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
381		- } else {
382		- space = rx_get - rx_put;
383		- }
384		- if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
385		- /* Start flow by setting RTS active */
386		- outb(inb (UART0_BASE + UART_MCR) \| 0x02, UART0_BASE + UART_MCR);
387		- }
388		-
389		- return c;
390		-}
391		-
392		-int serial_buffered_tstc(void)
393		-{
394		- return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
395		-}
396		-
397		-#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
398		-
399		-
400		-#if defined(CONFIG_CMD_KGDB)
401		-/*
402		- AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
403		- number 0 or number 1
404		- - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
405		- configuration has been already done
406		- - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
407		- configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
408		-*/
409		-#if (CONFIG_KGDB_SER_INDEX & 2)
410		-void kgdb_serial_init(void)
411		-{
412		- volatile char val;
413		- bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
414		-
415		- /*
416		- * Init onboard 16550 UART
417		- */
418		- outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */
419		- outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */
420		- outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */
421		- outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */
422		- outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */
423		- outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */
424		- val = inb(UART1_BASE + UART_LSR); /* clear line status */
425		- val = inb(UART1_BASE + UART_RBR); /* read receive buffer */
426		- outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */
427		- outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */
428		-}
429		-
430		-
431		-void putDebugChar(const char c)
432		-{
433		- if (c == '\n')
434		- serial_putc ('\r');
435		-
436		- outb(c, UART1_BASE + UART_THR); /* put character out */
437		-
438		- /* check THRE bit, wait for transfer done */
439		- while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20);
440		-}
441		-
442		-
443		-void putDebugStr(const char *s)
444		-{
445		- while (*s) {
446		- serial_putc(*s++);
447		- }
448		-}
449		-
450		-
451		-int getDebugChar(void)
452		-{
453		- unsigned char status = 0;
454		-
455		- while (1) {
456		- status = inb(UART1_BASE + UART_LSR);
457		- if ((status & asyncLSRDataReady1) != 0x0) {
458		- break;
459		- }
460		- if ((status & ( asyncLSRFramingError1 \|
461		- asyncLSROverrunError1 \|
462		- asyncLSRParityError1 \|
463		- asyncLSRBreakInterrupt1 )) != 0) {
464		- outb(asyncLSRFramingError1 \|
465		- asyncLSROverrunError1 \|
466		- asyncLSRParityError1 \|
467		- asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR);
468		- }
469		- }
470		- return (0x000000ff & (int) inb(UART1_BASE));
471		-}
472		-
473		-
474		-void kgdb_interruptible(int yes)
475		-{
476		- return;
477		-}
478		-
479		-#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
480		-
481		-void kgdb_serial_init(void)
482		-{
483		- serial_printf ("[on serial] ");
484		-}
485		-
486		-void putDebugChar(int c)
487		-{
488		- serial_putc (c);
489		-}
490		-
491		-void putDebugStr(const char *str)
492		-{
493		- serial_puts (str);
494		-}
495		-
496		-int getDebugChar(void)
497		-{
498		- return serial_getc ();
499		-}
500		-
501		-void kgdb_interruptible(int yes)
502		-{
503		- return;
504		-}
505		-#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
506		-#endif
...	...	@@ -37,6 +37,7 @@
37	37	#include <malloc.h>
38	38	#include <net.h>
39	39	#include <ide.h>
	40	+#include <serial.h>
40	41	#include <asm/u-boot-i386.h>
41	42	#include <elf.h>
42	43
...	...	@@ -149,7 +150,6 @@
149	150	typedef int (init_fnc_t) (void);
150	151
151	152	init_fnc_t *init_sequence[] = {
152		- serial_init,
153	153	cpu_init_r, /* basic cpu dependent setup */
154	154	board_early_init_r, /* basic board dependent setup */
155	155	dram_init, /* configure available RAM banks */
...	...	@@ -277,6 +277,9 @@
277	277	}
278	278	show_boot_progress(0x23);
279	279
	280	+#ifdef CONFIG_SERIAL_MULTI
	281	+ serial_initialize();
	282	+#endif
280	283	/* configure available FLASH banks */
281	284	size = flash_init();
282	285	display_flash_config(size);
...	...	@@ -111,8 +111,9 @@
111	111	writew(0x0615, &sc520_mmcr->romcs1ctl);
112	112	writew(0x0615, &sc520_mmcr->romcs2ctl);
113	113
114		- writeb(0x02, &sc520_mmcr->adddecctl);
	114	+ writeb(0x00, &sc520_mmcr->adddecctl);
115	115	writeb(0x07, &sc520_mmcr->uart1ctl);
	116	+ writeb(0x07, &sc520_mmcr->uart2ctl);
116	117	writeb(0x06, &sc520_mmcr->sysarbctl);
117	118	writew(0x0003, &sc520_mmcr->sysarbmenb);
118	119
...	...	@@ -41,7 +41,8 @@
41	41	#elif defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440) \
42	42	\|\| defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| defined(CONFIG_405EX) \
43	43	\|\| defined(CONFIG_MPC5xxx) \|\| defined(CONFIG_MPC83xx) \
44		- \|\| defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
	44	+ \|\| defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx) \
	45	+ \|\| defined(CONFIG_SYS_SC520)
45	46	#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
46	47	#if (CONFIG_CONS_INDEX==1)
47	48	return &eserial1_device;
...	...	@@ -21,6 +21,7 @@
21	21	* MA 02111-1307 USA
22	22	*/
23	23
	24	+#include <asm/ibmpc.h>
24	25	/*
25	26	* board/config.h - configuration options, board specific
26	27	*/
...	...	@@ -55,6 +56,26 @@
55	56	#undef CONFIG_HW_WATCHDOG
56	57
57	58	/*-----------------------------------------------------------------------
	59	+ * Serial Configuration
	60	+ */
	61	+#define CONFIG_SERIAL_MULTI
	62	+#undef CONFIG_SERIAL_SOFTWARE_FIFO
	63	+#define CONFIG_CONS_INDEX 1
	64	+#define CONFIG_SYS_NS16550
	65	+#define CONFIG_SYS_NS16550_SERIAL
	66	+#define CONFIG_SYS_NS16550_REG_SIZE 1
	67	+#define CONFIG_SYS_NS16550_CLK 1843200
	68	+#define CONFIG_BAUDRATE 9600
	69	+#define CONFIG_SYS_BAUDRATE_TABLE \
	70	+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	71	+
	72	+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
	73	+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
	74	+#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
	75	+#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
	76	+#define CONFIG_SYS_NS16550_PORT_MAPPED
	77	+
	78	+ /*-----------------------------------------------------------------------
58	79	* Video Configuration
59	80	*/
60	81	#undef CONFIG_VIDEO /* No Video Hardware */
...	...	@@ -65,8 +86,6 @@
65	86	*/
66	87	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
67	88
68		-#define CONFIG_BAUDRATE 9600
69		-
70	89	/*-----------------------------------------------------------------------
71	90	* Command line configuration.
72	91	*/
...	...	@@ -122,9 +141,6 @@
122	141	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
123	142
124	143	#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
125		-
126		- /* valid baudrates */
127		-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
128	144
129	145	/*-----------------------------------------------------------------------
130	146	* SDRAM Configuration
...	...	@@ -26,7 +26,8 @@
26	26	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440) \|\| \
27	27	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| defined(CONFIG_405EX) \|\| \
28	28	defined(CONFIG_MPC5xxx) \|\| defined(CONFIG_MPC83xx) \|\| \
29		- defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
	29	+ defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx) \|\| \
	30	+ defined(CONFIG_SYS_SC520)
30	31	extern struct serial_device serial0_device;
31	32	extern struct serial_device serial1_device;
32	33	#if defined(CONFIG_SYS_NS16550_SERIAL)