stm32f7: sdram: move sdram driver code to ram drivers area

Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>

stm32f7: sdram: move sdram driver code to ram drivers area
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
Vikas Manocha · Tom Rini
1 parent 890bafd752
Showing 5 changed files with 135 additions and 112 deletions Side-by-side Diff
board/st/stm32f746-disco/stm32f746-disco.c
configs/stm32f746-disco_defconfig
drivers/ram/Kconfig
drivers/ram/Makefile
drivers/ram/stm32_sdram.c
@@ -10,7 +10,6 @@
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
 #include <dm/platdata.h>
 #include <dm/platform_data/serial_stm32x7.h>
 #include <asm/arch/stm32_periph.h>
  
@@ -106,57 +105,8 @@
 	return rv;
 }
  
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
-	u32 tmp = freq/1000000;
-	return (tmp * ns) / 1000;
-}
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS	3	/* 3 cycles */
-#define SDRAM_NB	1	/* Number of banks */
-#define SDRAM_MWID	1	/* 16 bit memory */
-
-#define SDRAM_NR	0x1	/* 12-bit row */
-#define SDRAM_NC	0x0	/* 8-bit col */
-#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
-#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD	NS2CLK(12)
-#define SDRAM_TRCD	NS2CLK(18)
-#define SDRAM_TRP	NS2CLK(18)
-#define SDRAM_TRAS	NS2CLK(42)
-#define SDRAM_TRC	NS2CLK(60)
-#define SDRAM_TRFC	NS2CLK(60)
-#define SDRAM_TCDL	(1 - 1)
-#define SDRAM_TRDL	NS2CLK(12)
-#define SDRAM_TBDL	(1 - 1)
-#define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
-#define SDRAM_TCCD	(1 - 1)
-
-#define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
-#define SDRAM_TMRD	1		/* Page 10, Mode Register Set */
-
-
-/* Last data in to row precharge, need also comply ineq on page 1648 */
-#define SDRAM_TWR	max(\
-	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
-	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
-)
-
-
-#define SDRAM_MODE_BL_SHIFT	0
-#define SDRAM_MODE_CAS_SHIFT	4
-#define SDRAM_MODE_BL		0
-#define SDRAM_MODE_CAS		SDRAM_CAS
-
 int dram_init(void)
 {
-	u32 freq;
 	int rv;
  
 	rv = fmc_setup_gpio();
  
  
@@ -164,76 +114,15 @@
 		return rv;
  
 	clock_setup(FMC_CLOCK_CFG);
+	stm32_sdram_init();
  
 	/*
-	 * Get frequency for NS2CLK calculation.
-	 */
-	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
-	writel(
-		CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
-		| SDRAM_NB << FMC_SDCR_NB_SHIFT
-		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
-		| SDRAM_NR << FMC_SDCR_NR_SHIFT
-		| SDRAM_NC << FMC_SDCR_NC_SHIFT
-		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-		&STM32_SDRAM_FMC->sdcr1);
-
-	writel(
-		SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
-		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
-		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
-		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
-		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
-		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
-		&STM32_SDRAM_FMC->sdtr1);
-
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
-		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
-		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
-		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
-		&STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	FMC_BUSY_WAIT();
-
-	/* Refresh timer */
-	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
-
-	/*
 	 * Fill in global info with description of SRAM configuration
 	 */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
 	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
  
 	gd->ram_size = CONFIG_SYS_RAM_SIZE;
-
 	return rv;
 }
  
@@ -43,4 +43,10 @@
 CONFIG_STM32_QSPI=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_CLK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
@@ -16,4 +16,12 @@
 	  If this is acceptable and you have a need to use RAM drivers in
 	  SPL, enable this option. It might provide a cleaner interface to
 	  setting up RAM (e.g. SDRAM / DDR) within SPL.
+
+config STM32_SDRAM
+	bool "Enable STM32 SDRAM support"
+	depends on RAM
+	help
+	  STM32F7 family devices support flexible memory controller(FMC) to
+	  support external memories like sdram, psram & nand.
+	  This driver is for the sdram memory interface with the FMC.
@@ -6,4 +6,5 @@
 #
 obj-$(CONFIG_RAM) += ram-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/fmc.h>
+#include <asm/arch/stm32.h>
+
+static inline u32 _ns2clk(u32 ns, u32 freq)
+{
+	u32 tmp = freq/1000000;
+	return (tmp * ns) / 1000;
+}
+
+#define NS2CLK(ns) (_ns2clk(ns, freq))
+
+/*
+ * Following are timings for IS42S16400J, from corresponding datasheet
+ */
+#define SDRAM_CAS	3	/* 3 cycles */
+#define SDRAM_NB	1	/* Number of banks */
+#define SDRAM_MWID	1	/* 16 bit memory */
+
+#define SDRAM_NR	0x1	/* 12-bit row */
+#define SDRAM_NC	0x0	/* 8-bit col */
+#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
+#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
+
+#define SDRAM_TRRD	NS2CLK(12)
+#define SDRAM_TRCD	NS2CLK(18)
+#define SDRAM_TRP	NS2CLK(18)
+#define SDRAM_TRAS	NS2CLK(42)
+#define SDRAM_TRC	NS2CLK(60)
+#define SDRAM_TRFC	NS2CLK(60)
+#define SDRAM_TCDL	(1 - 1)
+#define SDRAM_TRDL	NS2CLK(12)
+#define SDRAM_TBDL	(1 - 1)
+#define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
+#define SDRAM_TCCD	(1 - 1)
+
+#define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
+#define SDRAM_TMRD	1		/* Page 10, Mode Register Set */
+
+
+/* Last data in to row precharge, need also comply ineq on page 1648 */
+#define SDRAM_TWR	max(\
+		(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
+		(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
+		)
+
+
+#define SDRAM_MODE_BL_SHIFT	0
+#define SDRAM_MODE_CAS_SHIFT	4
+#define SDRAM_MODE_BL		0
+#define SDRAM_MODE_CAS		SDRAM_CAS
+
+int stm32_sdram_init(void)
+{
+	u32 freq;
+
+	/*
+	 * Get frequency for NS2CLK calculation.
+	 */
+	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
+
+	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
+			| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
+			| SDRAM_NB << FMC_SDCR_NB_SHIFT
+			| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
+			| SDRAM_NR << FMC_SDCR_NR_SHIFT
+			| SDRAM_NC << FMC_SDCR_NC_SHIFT
+			| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
+			| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
+			&STM32_SDRAM_FMC->sdcr1);
+
+	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
+			| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
+			| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
+			| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
+			| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
+			| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
+			| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
+			&STM32_SDRAM_FMC->sdtr1);
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
+	       &STM32_SDRAM_FMC->sdcmr);
+	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
+	       &STM32_SDRAM_FMC->sdcmr);
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
+		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
+	       | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
+	       << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
+	       &STM32_SDRAM_FMC->sdcmr);
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
+	       &STM32_SDRAM_FMC->sdcmr);
+	FMC_BUSY_WAIT();
+
+	/* Refresh timer */
+	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
+
+	return 0;
+}
...	...	@@ -10,7 +10,6 @@
10	10	#include <asm/armv7m.h>
11	11	#include <asm/arch/stm32.h>
12	12	#include <asm/arch/gpio.h>
13		-#include <asm/arch/fmc.h>
14	13	#include <dm/platdata.h>
15	14	#include <dm/platform_data/serial_stm32x7.h>
16	15	#include <asm/arch/stm32_periph.h>
17	16
...	...	@@ -106,57 +105,8 @@
106	105	return rv;
107	106	}
108	107
109		-static inline u32 _ns2clk(u32 ns, u32 freq)
110		-{
111		- u32 tmp = freq/1000000;
112		- return (tmp * ns) / 1000;
113		-}
114		-
115		-#define NS2CLK(ns) (_ns2clk(ns, freq))
116		-
117		-/*
118		- * Following are timings for IS42S16400J, from corresponding datasheet
119		- */
120		-#define SDRAM_CAS 3 /* 3 cycles */
121		-#define SDRAM_NB 1 /* Number of banks */
122		-#define SDRAM_MWID 1 /* 16 bit memory */
123		-
124		-#define SDRAM_NR 0x1 /* 12-bit row */
125		-#define SDRAM_NC 0x0 /* 8-bit col */
126		-#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
127		-#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
128		-
129		-#define SDRAM_TRRD NS2CLK(12)
130		-#define SDRAM_TRCD NS2CLK(18)
131		-#define SDRAM_TRP NS2CLK(18)
132		-#define SDRAM_TRAS NS2CLK(42)
133		-#define SDRAM_TRC NS2CLK(60)
134		-#define SDRAM_TRFC NS2CLK(60)
135		-#define SDRAM_TCDL (1 - 1)
136		-#define SDRAM_TRDL NS2CLK(12)
137		-#define SDRAM_TBDL (1 - 1)
138		-#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
139		-#define SDRAM_TCCD (1 - 1)
140		-
141		-#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
142		-#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
143		-
144		-
145		-/* Last data in to row precharge, need also comply ineq on page 1648 */
146		-#define SDRAM_TWR max(\
147		- (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
148		- (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
149		-)
150		-
151		-
152		-#define SDRAM_MODE_BL_SHIFT 0
153		-#define SDRAM_MODE_CAS_SHIFT 4
154		-#define SDRAM_MODE_BL 0
155		-#define SDRAM_MODE_CAS SDRAM_CAS
156		-
157	108	int dram_init(void)
158	109	{
159		- u32 freq;
160	110	int rv;
161	111
162	112	rv = fmc_setup_gpio();
163	113
164	114
...	...	@@ -164,76 +114,15 @@
164	114	return rv;
165	115
166	116	clock_setup(FMC_CLOCK_CFG);
	117	+ stm32_sdram_init();
167	118
168	119	/*
169		- * Get frequency for NS2CLK calculation.
170		- */
171		- freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
172		-
173		- writel(
174		- CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
175		- \| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
176		- \| SDRAM_NB << FMC_SDCR_NB_SHIFT
177		- \| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
178		- \| SDRAM_NR << FMC_SDCR_NR_SHIFT
179		- \| SDRAM_NC << FMC_SDCR_NC_SHIFT
180		- \| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
181		- \| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
182		- &STM32_SDRAM_FMC->sdcr1);
183		-
184		- writel(
185		- SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
186		- \| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
187		- \| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
188		- \| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
189		- \| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
190		- \| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
191		- \| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
192		- &STM32_SDRAM_FMC->sdtr1);
193		-
194		- writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_START_CLOCK,
195		- &STM32_SDRAM_FMC->sdcmr);
196		-
197		- udelay(200); /* 200 us delay, page 10, "Power-Up" */
198		- FMC_BUSY_WAIT();
199		-
200		- writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_PRECHARGE,
201		- &STM32_SDRAM_FMC->sdcmr);
202		-
203		- udelay(100);
204		- FMC_BUSY_WAIT();
205		-
206		- writel((FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_AUTOREFRESH
207		- \| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
208		-
209		- udelay(100);
210		- FMC_BUSY_WAIT();
211		-
212		- writel(FMC_SDCMR_BANK_1 \| (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
213		- \| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
214		- << FMC_SDCMR_MODE_REGISTER_SHIFT \| FMC_SDCMR_MODE_WRITE_MODE,
215		- &STM32_SDRAM_FMC->sdcmr);
216		-
217		- udelay(100);
218		-
219		- FMC_BUSY_WAIT();
220		-
221		- writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_NORMAL,
222		- &STM32_SDRAM_FMC->sdcmr);
223		-
224		- FMC_BUSY_WAIT();
225		-
226		- /* Refresh timer */
227		- writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
228		-
229		- /*
230	120	* Fill in global info with description of SRAM configuration
231	121	*/
232	122	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
233	123	gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
234	124
235	125	gd->ram_size = CONFIG_SYS_RAM_SIZE;
236		-
237	126	return rv;
238	127	}
239	128
...	...	@@ -43,4 +43,10 @@
43	43	CONFIG_STM32_QSPI=y
44	44	CONFIG_OF_LIBFDT_OVERLAY=y
45	45	# CONFIG_EFI_LOADER is not set
	46	+CONFIG_CLK=y
	47	+CONFIG_PINCTRL=y
	48	+# CONFIG_PINCTRL_FULL is not set
	49	+CONFIG_PINCTRL_STM32=y
	50	+CONFIG_RAM=y
	51	+CONFIG_STM32_SDRAM=y
...	...	@@ -16,4 +16,12 @@
16	16	If this is acceptable and you have a need to use RAM drivers in
17	17	SPL, enable this option. It might provide a cleaner interface to
18	18	setting up RAM (e.g. SDRAM / DDR) within SPL.
	19	+
	20	+config STM32_SDRAM
	21	+ bool "Enable STM32 SDRAM support"
	22	+ depends on RAM
	23	+ help
	24	+ STM32F7 family devices support flexible memory controller(FMC) to
	25	+ support external memories like sdram, psram & nand.
	26	+ This driver is for the sdram memory interface with the FMC.
...	...	@@ -6,4 +6,5 @@
6	6	#
7	7	obj-$(CONFIG_RAM) += ram-uclass.o
8	8	obj-$(CONFIG_SANDBOX) += sandbox_ram.o
	9	+obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
	1	+/*
	2	+ * (C) Copyright 2017
	3	+ * Vikas Manocha, <vikas.manocha@st.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#include <common.h>
	9	+#include <asm/io.h>
	10	+#include <asm/arch/fmc.h>
	11	+#include <asm/arch/stm32.h>
	12	+
	13	+static inline u32 _ns2clk(u32 ns, u32 freq)
	14	+{
	15	+ u32 tmp = freq/1000000;
	16	+ return (tmp * ns) / 1000;
	17	+}
	18	+
	19	+#define NS2CLK(ns) (_ns2clk(ns, freq))
	20	+
	21	+/*
	22	+ * Following are timings for IS42S16400J, from corresponding datasheet
	23	+ */
	24	+#define SDRAM_CAS 3 /* 3 cycles */
	25	+#define SDRAM_NB 1 /* Number of banks */
	26	+#define SDRAM_MWID 1 /* 16 bit memory */
	27	+
	28	+#define SDRAM_NR 0x1 /* 12-bit row */
	29	+#define SDRAM_NC 0x0 /* 8-bit col */
	30	+#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
	31	+#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
	32	+
	33	+#define SDRAM_TRRD NS2CLK(12)
	34	+#define SDRAM_TRCD NS2CLK(18)
	35	+#define SDRAM_TRP NS2CLK(18)
	36	+#define SDRAM_TRAS NS2CLK(42)
	37	+#define SDRAM_TRC NS2CLK(60)
	38	+#define SDRAM_TRFC NS2CLK(60)
	39	+#define SDRAM_TCDL (1 - 1)
	40	+#define SDRAM_TRDL NS2CLK(12)
	41	+#define SDRAM_TBDL (1 - 1)
	42	+#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
	43	+#define SDRAM_TCCD (1 - 1)
	44	+
	45	+#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
	46	+#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
	47	+
	48	+
	49	+/* Last data in to row precharge, need also comply ineq on page 1648 */
	50	+#define SDRAM_TWR max(\
	51	+ (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
	52	+ (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
	53	+ )
	54	+
	55	+
	56	+#define SDRAM_MODE_BL_SHIFT 0
	57	+#define SDRAM_MODE_CAS_SHIFT 4
	58	+#define SDRAM_MODE_BL 0
	59	+#define SDRAM_MODE_CAS SDRAM_CAS
	60	+
	61	+int stm32_sdram_init(void)
	62	+{
	63	+ u32 freq;
	64	+
	65	+ /*
	66	+ * Get frequency for NS2CLK calculation.
	67	+ */
	68	+ freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
	69	+
	70	+ writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
	71	+ \| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
	72	+ \| SDRAM_NB << FMC_SDCR_NB_SHIFT
	73	+ \| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
	74	+ \| SDRAM_NR << FMC_SDCR_NR_SHIFT
	75	+ \| SDRAM_NC << FMC_SDCR_NC_SHIFT
	76	+ \| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
	77	+ \| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
	78	+ &STM32_SDRAM_FMC->sdcr1);
	79	+
	80	+ writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
	81	+ \| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
	82	+ \| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
	83	+ \| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
	84	+ \| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
	85	+ \| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
	86	+ \| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
	87	+ &STM32_SDRAM_FMC->sdtr1);
	88	+
	89	+ writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_START_CLOCK,
	90	+ &STM32_SDRAM_FMC->sdcmr);
	91	+ udelay(200); /* 200 us delay, page 10, "Power-Up" */
	92	+ FMC_BUSY_WAIT();
	93	+
	94	+ writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_PRECHARGE,
	95	+ &STM32_SDRAM_FMC->sdcmr);
	96	+ udelay(100);
	97	+ FMC_BUSY_WAIT();
	98	+
	99	+ writel((FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_AUTOREFRESH
	100	+ \| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
	101	+ udelay(100);
	102	+ FMC_BUSY_WAIT();
	103	+
	104	+ writel(FMC_SDCMR_BANK_1 \| (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
	105	+ \| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
	106	+ << FMC_SDCMR_MODE_REGISTER_SHIFT \| FMC_SDCMR_MODE_WRITE_MODE,
	107	+ &STM32_SDRAM_FMC->sdcmr);
	108	+ udelay(100);
	109	+ FMC_BUSY_WAIT();
	110	+
	111	+ writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_NORMAL,
	112	+ &STM32_SDRAM_FMC->sdcmr);
	113	+ FMC_BUSY_WAIT();
	114	+
	115	+ /* Refresh timer */
	116	+ writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
	117	+
	118	+ return 0;
	119	+}