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Commit bf494d7e9b4ad73325b2aef2dc7b90b05dd90264

Authored by Peng Fan
Committed by Stefano Babic
1 parent 1b9654322e
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx8: add scfw macro definition 

Add SCFW macro definition.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Showing 7 changed files with 636 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8/sci/rpc.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2017-2018 NXP
  4 + *
  5 + */
  6 +
  7 +#ifndef SC_RPC_H
  8 +#define SC_RPC_H
  9 +
  10 +/* Note: Check SCFW API Released DOC before you want to modify something */
  11 +#define SC_RPC_VERSION 1U
  12 +
  13 +#define SC_RPC_MAX_MSG 8U
  14 +
  15 +#define RPC_VER(MSG) ((MSG)->version)
  16 +#define RPC_SIZE(MSG) ((MSG)->size)
  17 +#define RPC_SVC(MSG) ((MSG)->svc)
  18 +#define RPC_FUNC(MSG) ((MSG)->func)
  19 +#define RPC_R8(MSG) ((MSG)->func)
  20 +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
  21 +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
  22 +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
  23 +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
  24 +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
  25 +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
  26 +
  27 +#define SC_RPC_SVC_UNKNOWN 0U
  28 +#define SC_RPC_SVC_RETURN 1U
  29 +#define SC_RPC_SVC_PM 2U
  30 +#define SC_RPC_SVC_RM 3U
  31 +#define SC_RPC_SVC_TIMER 5U
  32 +#define SC_RPC_SVC_PAD 6U
  33 +#define SC_RPC_SVC_MISC 7U
  34 +#define SC_RPC_SVC_IRQ 8U
  35 +#define SC_RPC_SVC_ABORT 9U
  36 +
  37 +/* Types */
  38 +
  39 +struct sc_rpc_msg_s {
  40 + u8 version;
  41 + u8 size;
  42 + u8 svc;
  43 + u8 func;
  44 + union {
  45 + s32 i32[(SC_RPC_MAX_MSG - 1U)];
  46 + s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
  47 + s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
  48 + u32 u32[(SC_RPC_MAX_MSG - 1U)];
  49 + u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
  50 + u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
  51 + } DATA;
  52 +};
  53 +
  54 +/* PM RPC */
  55 +#define PM_FUNC_UNKNOWN 0
  56 +#define PM_FUNC_SET_SYS_POWER_MODE 19U
  57 +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
  58 +#define PM_FUNC_GET_SYS_POWER_MODE 2U
  59 +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U
  60 +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U
  61 +#define PM_FUNC_REQ_LOW_POWER_MODE 16U
  62 +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
  63 +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U
  64 +#define PM_FUNC_SET_CPU_RESUME 21U
  65 +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U
  66 +#define PM_FUNC_SET_CLOCK_RATE 5U
  67 +#define PM_FUNC_GET_CLOCK_RATE 6U
  68 +#define PM_FUNC_CLOCK_ENABLE 7U
  69 +#define PM_FUNC_SET_CLOCK_PARENT 14U
  70 +#define PM_FUNC_GET_CLOCK_PARENT 15U
  71 +#define PM_FUNC_RESET 13U
  72 +#define PM_FUNC_RESET_REASON 10U
  73 +#define PM_FUNC_BOOT 8U
  74 +#define PM_FUNC_REBOOT 9U
  75 +#define PM_FUNC_REBOOT_PARTITION 12U
  76 +#define PM_FUNC_CPU_START 11U
  77 +
  78 +/* MISC RPC */
  79 +#define MISC_FUNC_UNKNOWN 0
  80 +#define MISC_FUNC_SET_CONTROL 1U
  81 +#define MISC_FUNC_GET_CONTROL 2U
  82 +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U
  83 +#define MISC_FUNC_SET_DMA_GROUP 5U
  84 +#define MISC_FUNC_SECO_IMAGE_LOAD 8U
  85 +#define MISC_FUNC_SECO_AUTHENTICATE 9U
  86 +#define MISC_FUNC_SECO_FUSE_WRITE 20U
  87 +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U
  88 +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
  89 +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U
  90 +#define MISC_FUNC_SECO_BUILD_INFO 24U
  91 +#define MISC_FUNC_DEBUG_OUT 10U
  92 +#define MISC_FUNC_WAVEFORM_CAPTURE 6U
  93 +#define MISC_FUNC_BUILD_INFO 15U
  94 +#define MISC_FUNC_UNIQUE_ID 19U
  95 +#define MISC_FUNC_SET_ARI 3U
  96 +#define MISC_FUNC_BOOT_STATUS 7U
  97 +#define MISC_FUNC_BOOT_DONE 14U
  98 +#define MISC_FUNC_OTP_FUSE_READ 11U
  99 +#define MISC_FUNC_OTP_FUSE_WRITE 17U
  100 +#define MISC_FUNC_SET_TEMP 12U
  101 +#define MISC_FUNC_GET_TEMP 13U
  102 +#define MISC_FUNC_GET_BOOT_DEV 16U
  103 +#define MISC_FUNC_GET_BUTTON_STATUS 18U
  104 +
  105 +/* PAD RPC */
  106 +#define PAD_FUNC_UNKNOWN 0
  107 +#define PAD_FUNC_SET_MUX 1U
  108 +#define PAD_FUNC_GET_MUX 6U
  109 +#define PAD_FUNC_SET_GP 2U
  110 +#define PAD_FUNC_GET_GP 7U
  111 +#define PAD_FUNC_SET_WAKEUP 4U
  112 +#define PAD_FUNC_GET_WAKEUP 9U
  113 +#define PAD_FUNC_SET_ALL 5U
  114 +#define PAD_FUNC_GET_ALL 10U
  115 +#define PAD_FUNC_SET 15U
  116 +#define PAD_FUNC_GET 16U
  117 +#define PAD_FUNC_SET_GP_28FDSOI 11U
  118 +#define PAD_FUNC_GET_GP_28FDSOI 12U
  119 +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U
  120 +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U
  121 +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U
  122 +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U
  123 +
  124 +/* RM RPC */
  125 +#define RM_FUNC_UNKNOWN 0
  126 +#define RM_FUNC_PARTITION_ALLOC 1U
  127 +#define RM_FUNC_SET_CONFIDENTIAL 31U
  128 +#define RM_FUNC_PARTITION_FREE 2U
  129 +#define RM_FUNC_GET_DID 26U
  130 +#define RM_FUNC_PARTITION_STATIC 3U
  131 +#define RM_FUNC_PARTITION_LOCK 4U
  132 +#define RM_FUNC_GET_PARTITION 5U
  133 +#define RM_FUNC_SET_PARENT 6U
  134 +#define RM_FUNC_MOVE_ALL 7U
  135 +#define RM_FUNC_ASSIGN_RESOURCE 8U
  136 +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U
  137 +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U
  138 +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U
  139 +#define RM_FUNC_SET_MASTER_SID 11U
  140 +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U
  141 +#define RM_FUNC_IS_RESOURCE_OWNED 13U
  142 +#define RM_FUNC_IS_RESOURCE_MASTER 14U
  143 +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U
  144 +#define RM_FUNC_GET_RESOURCE_INFO 16U
  145 +#define RM_FUNC_MEMREG_ALLOC 17U
  146 +#define RM_FUNC_MEMREG_SPLIT 29U
  147 +#define RM_FUNC_MEMREG_FREE 18U
  148 +#define RM_FUNC_FIND_MEMREG 30U
  149 +#define RM_FUNC_ASSIGN_MEMREG 19U
  150 +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U
  151 +#define RM_FUNC_IS_MEMREG_OWNED 21U
  152 +#define RM_FUNC_GET_MEMREG_INFO 22U
  153 +#define RM_FUNC_ASSIGN_PAD 23U
  154 +#define RM_FUNC_SET_PAD_MOVABLE 24U
  155 +#define RM_FUNC_IS_PAD_OWNED 25U
  156 +#define RM_FUNC_DUMP 27U
  157 +
  158 +#endif /* SC_RPC_H */
arch/arm/include/asm/arch-imx8/sci/sci.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef _SC_SCI_H
  7 +#define _SC_SCI_H
  8 +
  9 +#include <asm/arch/sci/types.h>
  10 +#include <asm/arch/sci/svc/misc/api.h>
  11 +#include <asm/arch/sci/svc/pad/api.h>
  12 +#include <asm/arch/sci/svc/pm/api.h>
  13 +#include <asm/arch/sci/svc/rm/api.h>
  14 +#include <asm/arch/sci/rpc.h>
  15 +#include <dt-bindings/soc/imx_rsrc.h>
  16 +#include <linux/errno.h>
  17 +
  18 +static inline int sc_err_to_linux(sc_err_t err)
  19 +{
  20 + int ret;
  21 +
  22 + switch (err) {
  23 + case SC_ERR_NONE:
  24 + return 0;
  25 + case SC_ERR_VERSION:
  26 + case SC_ERR_CONFIG:
  27 + case SC_ERR_PARM:
  28 + ret = -EINVAL;
  29 + break;
  30 + case SC_ERR_NOACCESS:
  31 + case SC_ERR_LOCKED:
  32 + case SC_ERR_UNAVAILABLE:
  33 + ret = -EACCES;
  34 + break;
  35 + case SC_ERR_NOTFOUND:
  36 + case SC_ERR_NOPOWER:
  37 + ret = -ENODEV;
  38 + break;
  39 + case SC_ERR_IPC:
  40 + ret = -EIO;
  41 + break;
  42 + case SC_ERR_BUSY:
  43 + ret = -EBUSY;
  44 + break;
  45 + case SC_ERR_FAIL:
  46 + ret = -EIO;
  47 + break;
  48 + default:
  49 + ret = 0;
  50 + break;
  51 + }
  52 +
  53 + debug("%s %d %d\n", __func__, err, ret);
  54 +
  55 + return ret;
  56 +}
  57 +
  58 +#endif
arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef SC_MISC_API_H
  7 +#define SC_MISC_API_H
  8 +
  9 +/* Defines for sc_misc_boot_status_t */
  10 +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
  11 +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
  12 +
  13 +/* Defines for sc_misc_seco_auth_cmd_t */
  14 +#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */
  15 +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */
  16 +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */
  17 +
  18 +/* Defines for sc_misc_temp_t */
  19 +#define SC_MISC_TEMP 0U /* Temp sensor */
  20 +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
  21 +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
  22 +
  23 +/* Defines for sc_misc_seco_auth_cmd_t */
  24 +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
  25 +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
  26 +#define SC_MISC_REL_CONTAINER 2U /* Release container */
  27 +
  28 +typedef u8 sc_misc_boot_status_t;
  29 +
  30 +#endif /* SC_MISC_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef SC_PAD_API_H
  7 +#define SC_PAD_API_H
  8 +
  9 +/* Defines for sc_pad_config_t */
  10 +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
  11 +#define SC_PAD_CONFIG_OD 1U /* Open Drain */
  12 +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
  13 +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
  14 +
  15 +/* Defines for sc_pad_iso_t */
  16 +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
  17 +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
  18 +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
  19 +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
  20 +
  21 +/* Defines for sc_pad_28fdsoi_dse_t */
  22 +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
  23 +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
  24 +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
  25 +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
  26 +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
  27 +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
  28 +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
  29 +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */
  30 +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
  31 +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
  32 +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
  33 +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
  34 +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */
  35 +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */
  36 +
  37 +/* Defines for sc_pad_28fdsoi_ps_t */
  38 +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
  39 +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
  40 +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
  41 +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
  42 +
  43 +/* Defines for sc_pad_28fdsoi_pus_t */
  44 +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
  45 +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
  46 +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
  47 +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
  48 +
  49 +/* Defines for sc_pad_wakeup_t */
  50 +#define SC_PAD_WAKEUP_OFF 0U /* Off */
  51 +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
  52 +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
  53 +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
  54 +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
  55 +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
  56 +
  57 +#endif /* SC_PAD_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef SC_PM_API_H
  7 +#define SC_PM_API_H
  8 +
  9 +/* Defines for sc_pm_power_mode_t */
  10 +#define SC_PM_PW_MODE_OFF 0U /* Power off */
  11 +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
  12 +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
  13 +#define SC_PM_PW_MODE_ON 3U /* Power on */
  14 +
  15 +/* Defines for sc_pm_clk_t */
  16 +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
  17 +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
  18 +#define SC_PM_CLK_PER 2U /* Peripheral clock */
  19 +#define SC_PM_CLK_PHY 3U /* Phy clock */
  20 +#define SC_PM_CLK_MISC 4U /* Misc clock */
  21 +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
  22 +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
  23 +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
  24 +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
  25 +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
  26 +#define SC_PM_CLK_CPU 2U /* CPU clock */
  27 +#define SC_PM_CLK_PLL 4U /* PLL */
  28 +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
  29 +
  30 +/* Defines for sc_pm_clk_mode_t */
  31 +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
  32 +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
  33 +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
  34 +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
  35 +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
  36 +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
  37 +
  38 +typedef u8 sc_pm_power_mode_t;
  39 +typedef u8 sc_pm_clk_t;
  40 +typedef u8 sc_pm_clk_mode_t;
  41 +typedef u8 sc_pm_clk_parent_t;
  42 +typedef u32 sc_pm_clock_rate_t;
  43 +
  44 +#endif /* SC_PM_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef SC_RM_API_H
  7 +#define SC_RM_API_H
  8 +
  9 +#include <asm/arch/sci/types.h>
  10 +
  11 +/* Defines for type widths */
  12 +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */
  13 +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */
  14 +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */
  15 +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */
  16 +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */
  17 +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */
  18 +
  19 +/* Defines for ALL parameters */
  20 +#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */
  21 +#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */
  22 +
  23 +/* Defines for sc_rm_spa_t */
  24 +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
  25 +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
  26 +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
  27 +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
  28 +
  29 +/* Defines for sc_rm_perm_t */
  30 +#define SC_RM_PERM_NONE 0U /* No access */
  31 +#define SC_RM_PERM_SEC_R 1U /* Secure RO */
  32 +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
  33 +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
  34 +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
  35 +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
  36 +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
  37 +#define SC_RM_PERM_FULL 7U /* Full access */
  38 +
  39 +/* Types */
  40 +
  41 +/*!
  42 + * This type is used to declare a resource partition.
  43 + */
  44 +typedef u8 sc_rm_pt_t;
  45 +
  46 +/*!
  47 + * This type is used to declare a memory region.
  48 + */
  49 +typedef u8 sc_rm_mr_t;
  50 +
  51 +/*!
  52 + * This type is used to declare a resource domain ID used by the
  53 + * isolation HW.
  54 + */
  55 +typedef u8 sc_rm_did_t;
  56 +
  57 +/*!
  58 + * This type is used to declare an SMMU StreamID.
  59 + */
  60 +typedef u16 sc_rm_sid_t;
  61 +
  62 +/*!
  63 + * This type is a used to declare master transaction attributes.
  64 + */
  65 +typedef u8 sc_rm_spa_t;
  66 +
  67 +typedef u8 sc_rm_perm_t;
  68 +
  69 +#endif /* SC_RM_API_H */
arch/arm/include/asm/arch-imx8/sci/types.h
Diff comments   View file @ bf494d7
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef SC_TYPES_H
  7 +#define SC_TYPES_H
  8 +
  9 +/* Includes */
  10 +#include <linux/types.h>
  11 +
  12 +/* Defines */
  13 +/*
  14 + * This type is used to declare a handle for an IPC communication
  15 + * channel. Its meaning is specific to the IPC implementation.
  16 + */
  17 +typedef u64 sc_ipc_t;
  18 +
  19 +/* Defines for common frequencies */
  20 +#define SC_32KHZ 32768U /* 32KHz */
  21 +#define SC_10MHZ 10000000U /* 10MHz */
  22 +#define SC_20MHZ 20000000U /* 20MHz */
  23 +#define SC_25MHZ 25000000U /* 25MHz */
  24 +#define SC_27MHZ 27000000U /* 27MHz */
  25 +#define SC_40MHZ 40000000U /* 40MHz */
  26 +#define SC_45MHZ 45000000U /* 45MHz */
  27 +#define SC_50MHZ 50000000U /* 50MHz */
  28 +#define SC_60MHZ 60000000U /* 60MHz */
  29 +#define SC_66MHZ 66666666U /* 66MHz */
  30 +#define SC_74MHZ 74250000U /* 74.25MHz */
  31 +#define SC_80MHZ 80000000U /* 80MHz */
  32 +#define SC_83MHZ 83333333U /* 83MHz */
  33 +#define SC_84MHZ 84375000U /* 84.37MHz */
  34 +#define SC_100MHZ 100000000U /* 100MHz */
  35 +#define SC_125MHZ 125000000U /* 125MHz */
  36 +#define SC_133MHZ 133333333U /* 133MHz */
  37 +#define SC_135MHZ 135000000U /* 135MHz */
  38 +#define SC_150MHZ 150000000U /* 150MHz */
  39 +#define SC_160MHZ 160000000U /* 160MHz */
  40 +#define SC_166MHZ 166666666U /* 166MHz */
  41 +#define SC_175MHZ 175000000U /* 175MHz */
  42 +#define SC_180MHZ 180000000U /* 180MHz */
  43 +#define SC_200MHZ 200000000U /* 200MHz */
  44 +#define SC_250MHZ 250000000U /* 250MHz */
  45 +#define SC_266MHZ 266666666U /* 266MHz */
  46 +#define SC_300MHZ 300000000U /* 300MHz */
  47 +#define SC_312MHZ 312500000U /* 312.5MHZ */
  48 +#define SC_320MHZ 320000000U /* 320MHz */
  49 +#define SC_325MHZ 325000000U /* 325MHz */
  50 +#define SC_333MHZ 333333333U /* 333MHz */
  51 +#define SC_350MHZ 350000000U /* 350MHz */
  52 +#define SC_372MHZ 372000000U /* 372MHz */
  53 +#define SC_375MHZ 375000000U /* 375MHz */
  54 +#define SC_400MHZ 400000000U /* 400MHz */
  55 +#define SC_500MHZ 500000000U /* 500MHz */
  56 +#define SC_594MHZ 594000000U /* 594MHz */
  57 +#define SC_625MHZ 625000000U /* 625MHz */
  58 +#define SC_640MHZ 640000000U /* 640MHz */
  59 +#define SC_650MHZ 650000000U /* 650MHz */
  60 +#define SC_667MHZ 666666667U /* 667MHz */
  61 +#define SC_675MHZ 675000000U /* 675MHz */
  62 +#define SC_700MHZ 700000000U /* 700MHz */
  63 +#define SC_720MHZ 720000000U /* 720MHz */
  64 +#define SC_750MHZ 750000000U /* 750MHz */
  65 +#define SC_800MHZ 800000000U /* 800MHz */
  66 +#define SC_850MHZ 850000000U /* 850MHz */
  67 +#define SC_900MHZ 900000000U /* 900MHz */
  68 +#define SC_1000MHZ 1000000000U /* 1GHz */
  69 +#define SC_1060MHZ 1060000000U /* 1.06GHz */
  70 +#define SC_1188MHZ 1188000000U /* 1.188GHz */
  71 +#define SC_1260MHZ 1260000000U /* 1.26GHz */
  72 +#define SC_1280MHZ 1280000000U /* 1.28GHz */
  73 +#define SC_1300MHZ 1300000000U /* 1.3GHz */
  74 +#define SC_1400MHZ 1400000000U /* 1.4GHz */
  75 +#define SC_1500MHZ 1500000000U /* 1.5GHz */
  76 +#define SC_1600MHZ 1600000000U /* 1.6GHz */
  77 +#define SC_1800MHZ 1800000000U /* 1.8GHz */
  78 +#define SC_2000MHZ 2000000000U /* 2.0GHz */
  79 +#define SC_2112MHZ 2112000000U /* 2.12GHz */
  80 +
  81 +/* Defines for 24M related frequencies */
  82 +#define SC_8MHZ 8000000U /* 8MHz */
  83 +#define SC_12MHZ 12000000U /* 12MHz */
  84 +#define SC_19MHZ 19800000U /* 19.8MHz */
  85 +#define SC_24MHZ 24000000U /* 24MHz */
  86 +#define SC_48MHZ 48000000U /* 48MHz */
  87 +#define SC_120MHZ 120000000U /* 120MHz */
  88 +#define SC_132MHZ 132000000U /* 132MHz */
  89 +#define SC_144MHZ 144000000U /* 144MHz */
  90 +#define SC_192MHZ 192000000U /* 192MHz */
  91 +#define SC_211MHZ 211200000U /* 211.2MHz */
  92 +#define SC_240MHZ 240000000U /* 240MHz */
  93 +#define SC_264MHZ 264000000U /* 264MHz */
  94 +#define SC_352MHZ 352000000U /* 352MHz */
  95 +#define SC_360MHZ 360000000U /* 360MHz */
  96 +#define SC_384MHZ 384000000U /* 384MHz */
  97 +#define SC_396MHZ 396000000U /* 396MHz */
  98 +#define SC_432MHZ 432000000U /* 432MHz */
  99 +#define SC_480MHZ 480000000U /* 480MHz */
  100 +#define SC_600MHZ 600000000U /* 600MHz */
  101 +#define SC_744MHZ 744000000U /* 744MHz */
  102 +#define SC_792MHZ 792000000U /* 792MHz */
  103 +#define SC_864MHZ 864000000U /* 864MHz */
  104 +#define SC_960MHZ 960000000U /* 960MHz */
  105 +#define SC_1056MHZ 1056000000U /* 1056MHz */
  106 +#define SC_1104MHZ 1104000000U /* 1104MHz */
  107 +#define SC_1200MHZ 1200000000U /* 1.2GHz */
  108 +#define SC_1464MHZ 1464000000U /* 1.464GHz */
  109 +#define SC_2400MHZ 2400000000U /* 2.4GHz */
  110 +
  111 +/* Defines for A/V related frequencies */
  112 +#define SC_62MHZ 62937500U /* 62.9375MHz */
  113 +#define SC_755MHZ 755250000U /* 755.25MHz */
  114 +
  115 +/* Defines for type widths */
  116 +#define SC_FADDR_W 36U /* Width of sc_faddr_t */
  117 +#define SC_BOOL_W 1U /* Width of sc_bool_t */
  118 +#define SC_ERR_W 4U /* Width of sc_err_t */
  119 +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
  120 +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */
  121 +
  122 +/* Defines for sc_bool_t */
  123 +#define SC_FALSE ((sc_bool_t)0U)
  124 +#define SC_TRUE ((sc_bool_t)1U)
  125 +
  126 +/* Defines for sc_err_t */
  127 +#define SC_ERR_NONE 0U /* Success */
  128 +#define SC_ERR_VERSION 1U /* Incompatible API version */
  129 +#define SC_ERR_CONFIG 2U /* Configuration error */
  130 +#define SC_ERR_PARM 3U /* Bad parameter */
  131 +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */
  132 +#define SC_ERR_LOCKED 5U /* Permission error (locked) */
  133 +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */
  134 +#define SC_ERR_NOTFOUND 7U /* Not found */
  135 +#define SC_ERR_NOPOWER 8U /* No power */
  136 +#define SC_ERR_IPC 9U /* Generic IPC error */
  137 +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */
  138 +#define SC_ERR_FAIL 11U /* General I/O failure */
  139 +#define SC_ERR_LAST 12U
  140 +
  141 +/* Defines for sc_ctrl_t. */
  142 +#define SC_C_TEMP 0U
  143 +#define SC_C_TEMP_HI 1U
  144 +#define SC_C_TEMP_LOW 2U
  145 +#define SC_C_PXL_LINK_MST1_ADDR 3U
  146 +#define SC_C_PXL_LINK_MST2_ADDR 4U
  147 +#define SC_C_PXL_LINK_MST_ENB 5U
  148 +#define SC_C_PXL_LINK_MST1_ENB 6U
  149 +#define SC_C_PXL_LINK_MST2_ENB 7U
  150 +#define SC_C_PXL_LINK_SLV1_ADDR 8U
  151 +#define SC_C_PXL_LINK_SLV2_ADDR 9U
  152 +#define SC_C_PXL_LINK_MST_VLD 10U
  153 +#define SC_C_PXL_LINK_MST1_VLD 11U
  154 +#define SC_C_PXL_LINK_MST2_VLD 12U
  155 +#define SC_C_SINGLE_MODE 13U
  156 +#define SC_C_ID 14U
  157 +#define SC_C_PXL_CLK_POLARITY 15U
  158 +#define SC_C_LINESTATE 16U
  159 +#define SC_C_PCIE_G_RST 17U
  160 +#define SC_C_PCIE_BUTTON_RST 18U
  161 +#define SC_C_PCIE_PERST 19U
  162 +#define SC_C_PHY_RESET 20U
  163 +#define SC_C_PXL_LINK_RATE_CORRECTION 21U
  164 +#define SC_C_PANIC 22U
  165 +#define SC_C_PRIORITY_GROUP 23U
  166 +#define SC_C_TXCLK 24U
  167 +#define SC_C_CLKDIV 25U
  168 +#define SC_C_DISABLE_50 26U
  169 +#define SC_C_DISABLE_125 27U
  170 +#define SC_C_SEL_125 28U
  171 +#define SC_C_MODE 29U
  172 +#define SC_C_SYNC_CTRL0 30U
  173 +#define SC_C_KACHUNK_CNT 31U
  174 +#define SC_C_KACHUNK_SEL 32U
  175 +#define SC_C_SYNC_CTRL1 33U
  176 +#define SC_C_DPI_RESET 34U
  177 +#define SC_C_MIPI_RESET 35U
  178 +#define SC_C_DUAL_MODE 36U
  179 +#define SC_C_VOLTAGE 37U
  180 +#define SC_C_PXL_LINK_SEL 38U
  181 +#define SC_C_OFS_SEL 39U
  182 +#define SC_C_OFS_AUDIO 40U
  183 +#define SC_C_OFS_PERIPH 41U
  184 +#define SC_C_OFS_IRQ 42U
  185 +#define SC_C_RST0 43U
  186 +#define SC_C_RST1 44U
  187 +#define SC_C_SEL0 45U
  188 +#define SC_C_LAST 46U
  189 +
  190 +#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
  191 +
  192 +/* Types */
  193 +
  194 +/* This type is used to store a boolean */
  195 +typedef u8 sc_bool_t;
  196 +
  197 +/* This type is used to store a system (full-size) address. */
  198 +typedef u64 sc_faddr_t;
  199 +
  200 +/* This type is used to indicate error response for most functions. */
  201 +typedef u8 sc_err_t;
  202 +
  203 +/*
  204 + * This type is used to indicate a resource. Resources include peripherals
  205 + * and bus masters (but not memory regions). Note items from list should
  206 + * never be changed or removed (only added to at the end of the list).
  207 + */
  208 +typedef u16 sc_rsrc_t;
  209 +
  210 +/* This type is used to indicate a control. */
  211 +typedef u8 sc_ctrl_t;
  212 +
  213 +/*
  214 + * This type is used to indicate a pad. Valid values are SoC specific.
  215 + *
  216 + * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  217 + */
  218 +typedef u16 sc_pad_t;
  219 +
  220 +#endif /* SC_TYPES_H */